1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /****************************************************************************** 3*4882a593Smuzhiyun PTP Header file 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Copyright (C) 2013 Vayavya Labs Pvt Ltd 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun Author: Rayagond Kokatanur <rayagond@vayavyalabs.com> 9*4882a593Smuzhiyun ******************************************************************************/ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __STMMAC_PTP_H__ 12*4882a593Smuzhiyun #define __STMMAC_PTP_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define PTP_XGMAC_OFFSET 0xd00 15*4882a593Smuzhiyun #define PTP_GMAC4_OFFSET 0xb00 16*4882a593Smuzhiyun #define PTP_GMAC3_X_OFFSET 0x700 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* IEEE 1588 PTP register offsets */ 19*4882a593Smuzhiyun #define PTP_TCR 0x00 /* Timestamp Control Reg */ 20*4882a593Smuzhiyun #define PTP_SSIR 0x04 /* Sub-Second Increment Reg */ 21*4882a593Smuzhiyun #define PTP_STSR 0x08 /* System Time – Seconds Regr */ 22*4882a593Smuzhiyun #define PTP_STNSR 0x0c /* System Time – Nanoseconds Reg */ 23*4882a593Smuzhiyun #define PTP_STSUR 0x10 /* System Time – Seconds Update Reg */ 24*4882a593Smuzhiyun #define PTP_STNSUR 0x14 /* System Time – Nanoseconds Update Reg */ 25*4882a593Smuzhiyun #define PTP_TAR 0x18 /* Timestamp Addend Reg */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define PTP_STNSUR_ADDSUB_SHIFT 31 28*4882a593Smuzhiyun #define PTP_DIGITAL_ROLLOVER_MODE 0x3B9ACA00 /* 10e9-1 ns */ 29*4882a593Smuzhiyun #define PTP_BINARY_ROLLOVER_MODE 0x80000000 /* ~0.466 ns */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* PTP Timestamp control register defines */ 32*4882a593Smuzhiyun #define PTP_TCR_TSENA BIT(0) /* Timestamp Enable */ 33*4882a593Smuzhiyun #define PTP_TCR_TSCFUPDT BIT(1) /* Timestamp Fine/Coarse Update */ 34*4882a593Smuzhiyun #define PTP_TCR_TSINIT BIT(2) /* Timestamp Initialize */ 35*4882a593Smuzhiyun #define PTP_TCR_TSUPDT BIT(3) /* Timestamp Update */ 36*4882a593Smuzhiyun #define PTP_TCR_TSTRIG BIT(4) /* Timestamp Interrupt Trigger Enable */ 37*4882a593Smuzhiyun #define PTP_TCR_TSADDREG BIT(5) /* Addend Reg Update */ 38*4882a593Smuzhiyun #define PTP_TCR_TSENALL BIT(8) /* Enable Timestamp for All Frames */ 39*4882a593Smuzhiyun #define PTP_TCR_TSCTRLSSR BIT(9) /* Digital or Binary Rollover Control */ 40*4882a593Smuzhiyun /* Enable PTP packet Processing for Version 2 Format */ 41*4882a593Smuzhiyun #define PTP_TCR_TSVER2ENA BIT(10) 42*4882a593Smuzhiyun /* Enable Processing of PTP over Ethernet Frames */ 43*4882a593Smuzhiyun #define PTP_TCR_TSIPENA BIT(11) 44*4882a593Smuzhiyun /* Enable Processing of PTP Frames Sent over IPv6-UDP */ 45*4882a593Smuzhiyun #define PTP_TCR_TSIPV6ENA BIT(12) 46*4882a593Smuzhiyun /* Enable Processing of PTP Frames Sent over IPv4-UDP */ 47*4882a593Smuzhiyun #define PTP_TCR_TSIPV4ENA BIT(13) 48*4882a593Smuzhiyun /* Enable Timestamp Snapshot for Event Messages */ 49*4882a593Smuzhiyun #define PTP_TCR_TSEVNTENA BIT(14) 50*4882a593Smuzhiyun /* Enable Snapshot for Messages Relevant to Master */ 51*4882a593Smuzhiyun #define PTP_TCR_TSMSTRENA BIT(15) 52*4882a593Smuzhiyun /* Select PTP packets for Taking Snapshots 53*4882a593Smuzhiyun * On gmac4 specifically: 54*4882a593Smuzhiyun * Enable SYNC, Pdelay_Req, Pdelay_Resp when TSEVNTENA is enabled. 55*4882a593Smuzhiyun * or 56*4882a593Smuzhiyun * Enable SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, 57*4882a593Smuzhiyun * Pdelay_Resp_Follow_Up if TSEVNTENA is disabled 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define PTP_TCR_SNAPTYPSEL_1 BIT(16) 60*4882a593Smuzhiyun /* Enable MAC address for PTP Frame Filtering */ 61*4882a593Smuzhiyun #define PTP_TCR_TSENMACADDR BIT(18) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* SSIR defines */ 64*4882a593Smuzhiyun #define PTP_SSIR_SSINC_MASK 0xff 65*4882a593Smuzhiyun #define GMAC4_PTP_SSIR_SSINC_SHIFT 16 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* __STMMAC_PTP_H__ */ 68