1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*******************************************************************************
3*4882a593Smuzhiyun This contains the functions to handle the pci driver.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun Copyright (C) 2011-2012 Vayavya Labs Pvt Ltd
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
9*4882a593Smuzhiyun Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*4882a593Smuzhiyun *******************************************************************************/
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/clk-provider.h>
13*4882a593Smuzhiyun #include <linux/pci.h>
14*4882a593Smuzhiyun #include <linux/dmi.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "stmmac.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct stmmac_pci_info {
19*4882a593Smuzhiyun int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
common_default_data(struct plat_stmmacenet_data * plat)22*4882a593Smuzhiyun static void common_default_data(struct plat_stmmacenet_data *plat)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
25*4882a593Smuzhiyun plat->has_gmac = 1;
26*4882a593Smuzhiyun plat->force_sf_dma_mode = 1;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun plat->mdio_bus_data->needs_reset = true;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Set default value for multicast hash bins */
31*4882a593Smuzhiyun plat->multicast_filter_bins = HASH_TABLE_SIZE;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Set default value for unicast filter entries */
34*4882a593Smuzhiyun plat->unicast_filter_entries = 1;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Set the maxmtu to a default of JUMBO_LEN */
37*4882a593Smuzhiyun plat->maxmtu = JUMBO_LEN;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Set default number of RX and TX queues to use */
40*4882a593Smuzhiyun plat->tx_queues_to_use = 1;
41*4882a593Smuzhiyun plat->rx_queues_to_use = 1;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Disable Priority config by default */
44*4882a593Smuzhiyun plat->tx_queues_cfg[0].use_prio = false;
45*4882a593Smuzhiyun plat->rx_queues_cfg[0].use_prio = false;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Disable RX queues routing by default */
48*4882a593Smuzhiyun plat->rx_queues_cfg[0].pkt_route = 0x0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
stmmac_default_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)51*4882a593Smuzhiyun static int stmmac_default_data(struct pci_dev *pdev,
52*4882a593Smuzhiyun struct plat_stmmacenet_data *plat)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun /* Set common default data first */
55*4882a593Smuzhiyun common_default_data(plat);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun plat->bus_id = 1;
58*4882a593Smuzhiyun plat->phy_addr = 0;
59*4882a593Smuzhiyun plat->phy_interface = PHY_INTERFACE_MODE_GMII;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun plat->dma_cfg->pbl = 32;
62*4882a593Smuzhiyun plat->dma_cfg->pblx8 = true;
63*4882a593Smuzhiyun /* TODO: AXI */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static const struct stmmac_pci_info stmmac_pci_info = {
69*4882a593Smuzhiyun .setup = stmmac_default_data,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
snps_gmac5_default_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)72*4882a593Smuzhiyun static int snps_gmac5_default_data(struct pci_dev *pdev,
73*4882a593Smuzhiyun struct plat_stmmacenet_data *plat)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun int i;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun plat->clk_csr = 5;
78*4882a593Smuzhiyun plat->has_gmac4 = 1;
79*4882a593Smuzhiyun plat->force_sf_dma_mode = 1;
80*4882a593Smuzhiyun plat->tso_en = 1;
81*4882a593Smuzhiyun plat->pmt = 1;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* Set default value for multicast hash bins */
84*4882a593Smuzhiyun plat->multicast_filter_bins = HASH_TABLE_SIZE;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* Set default value for unicast filter entries */
87*4882a593Smuzhiyun plat->unicast_filter_entries = 1;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Set the maxmtu to a default of JUMBO_LEN */
90*4882a593Smuzhiyun plat->maxmtu = JUMBO_LEN;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* Set default number of RX and TX queues to use */
93*4882a593Smuzhiyun plat->tx_queues_to_use = 4;
94*4882a593Smuzhiyun plat->rx_queues_to_use = 4;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
97*4882a593Smuzhiyun for (i = 0; i < plat->tx_queues_to_use; i++) {
98*4882a593Smuzhiyun plat->tx_queues_cfg[i].use_prio = false;
99*4882a593Smuzhiyun plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
100*4882a593Smuzhiyun plat->tx_queues_cfg[i].weight = 25;
101*4882a593Smuzhiyun if (i > 0)
102*4882a593Smuzhiyun plat->tx_queues_cfg[i].tbs_en = 1;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
106*4882a593Smuzhiyun for (i = 0; i < plat->rx_queues_to_use; i++) {
107*4882a593Smuzhiyun plat->rx_queues_cfg[i].use_prio = false;
108*4882a593Smuzhiyun plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
109*4882a593Smuzhiyun plat->rx_queues_cfg[i].pkt_route = 0x0;
110*4882a593Smuzhiyun plat->rx_queues_cfg[i].chan = i;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun plat->bus_id = 1;
114*4882a593Smuzhiyun plat->phy_addr = -1;
115*4882a593Smuzhiyun plat->phy_interface = PHY_INTERFACE_MODE_GMII;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun plat->dma_cfg->pbl = 32;
118*4882a593Smuzhiyun plat->dma_cfg->pblx8 = true;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Axi Configuration */
121*4882a593Smuzhiyun plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL);
122*4882a593Smuzhiyun if (!plat->axi)
123*4882a593Smuzhiyun return -ENOMEM;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun plat->axi->axi_wr_osr_lmt = 31;
126*4882a593Smuzhiyun plat->axi->axi_rd_osr_lmt = 31;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun plat->axi->axi_fb = false;
129*4882a593Smuzhiyun plat->axi->axi_blen[0] = 4;
130*4882a593Smuzhiyun plat->axi->axi_blen[1] = 8;
131*4882a593Smuzhiyun plat->axi->axi_blen[2] = 16;
132*4882a593Smuzhiyun plat->axi->axi_blen[3] = 32;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static const struct stmmac_pci_info snps_gmac5_pci_info = {
138*4882a593Smuzhiyun .setup = snps_gmac5_default_data,
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /**
142*4882a593Smuzhiyun * stmmac_pci_probe
143*4882a593Smuzhiyun *
144*4882a593Smuzhiyun * @pdev: pci device pointer
145*4882a593Smuzhiyun * @id: pointer to table of device id/id's.
146*4882a593Smuzhiyun *
147*4882a593Smuzhiyun * Description: This probing function gets called for all PCI devices which
148*4882a593Smuzhiyun * match the ID table and are not "owned" by other driver yet. This function
149*4882a593Smuzhiyun * gets passed a "struct pci_dev *" for each device whose entry in the ID table
150*4882a593Smuzhiyun * matches the device. The probe functions returns zero when the driver choose
151*4882a593Smuzhiyun * to take "ownership" of the device or an error code(-ve no) otherwise.
152*4882a593Smuzhiyun */
stmmac_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)153*4882a593Smuzhiyun static int stmmac_pci_probe(struct pci_dev *pdev,
154*4882a593Smuzhiyun const struct pci_device_id *id)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
157*4882a593Smuzhiyun struct plat_stmmacenet_data *plat;
158*4882a593Smuzhiyun struct stmmac_resources res;
159*4882a593Smuzhiyun int i;
160*4882a593Smuzhiyun int ret;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
163*4882a593Smuzhiyun if (!plat)
164*4882a593Smuzhiyun return -ENOMEM;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
167*4882a593Smuzhiyun sizeof(*plat->mdio_bus_data),
168*4882a593Smuzhiyun GFP_KERNEL);
169*4882a593Smuzhiyun if (!plat->mdio_bus_data)
170*4882a593Smuzhiyun return -ENOMEM;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
173*4882a593Smuzhiyun GFP_KERNEL);
174*4882a593Smuzhiyun if (!plat->dma_cfg)
175*4882a593Smuzhiyun return -ENOMEM;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* Enable pci device */
178*4882a593Smuzhiyun ret = pcim_enable_device(pdev);
179*4882a593Smuzhiyun if (ret) {
180*4882a593Smuzhiyun dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
181*4882a593Smuzhiyun __func__);
182*4882a593Smuzhiyun return ret;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* Get the base address of device */
186*4882a593Smuzhiyun for (i = 0; i < PCI_STD_NUM_BARS; i++) {
187*4882a593Smuzhiyun if (pci_resource_len(pdev, i) == 0)
188*4882a593Smuzhiyun continue;
189*4882a593Smuzhiyun ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev));
190*4882a593Smuzhiyun if (ret)
191*4882a593Smuzhiyun return ret;
192*4882a593Smuzhiyun break;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun pci_set_master(pdev);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun ret = info->setup(pdev, plat);
198*4882a593Smuzhiyun if (ret)
199*4882a593Smuzhiyun return ret;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun pci_enable_msi(pdev);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun memset(&res, 0, sizeof(res));
204*4882a593Smuzhiyun res.addr = pcim_iomap_table(pdev)[i];
205*4882a593Smuzhiyun res.wol_irq = pdev->irq;
206*4882a593Smuzhiyun res.irq = pdev->irq;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun return stmmac_dvr_probe(&pdev->dev, plat, &res);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /**
212*4882a593Smuzhiyun * stmmac_pci_remove
213*4882a593Smuzhiyun *
214*4882a593Smuzhiyun * @pdev: platform device pointer
215*4882a593Smuzhiyun * Description: this function calls the main to free the net resources
216*4882a593Smuzhiyun * and releases the PCI resources.
217*4882a593Smuzhiyun */
stmmac_pci_remove(struct pci_dev * pdev)218*4882a593Smuzhiyun static void stmmac_pci_remove(struct pci_dev *pdev)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun int i;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun stmmac_dvr_remove(&pdev->dev);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun for (i = 0; i < PCI_STD_NUM_BARS; i++) {
225*4882a593Smuzhiyun if (pci_resource_len(pdev, i) == 0)
226*4882a593Smuzhiyun continue;
227*4882a593Smuzhiyun pcim_iounmap_regions(pdev, BIT(i));
228*4882a593Smuzhiyun break;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
stmmac_pci_suspend(struct device * dev)232*4882a593Smuzhiyun static int __maybe_unused stmmac_pci_suspend(struct device *dev)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun struct pci_dev *pdev = to_pci_dev(dev);
235*4882a593Smuzhiyun int ret;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ret = stmmac_suspend(dev);
238*4882a593Smuzhiyun if (ret)
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun ret = pci_save_state(pdev);
242*4882a593Smuzhiyun if (ret)
243*4882a593Smuzhiyun return ret;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun pci_disable_device(pdev);
246*4882a593Smuzhiyun pci_wake_from_d3(pdev, true);
247*4882a593Smuzhiyun return 0;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
stmmac_pci_resume(struct device * dev)250*4882a593Smuzhiyun static int __maybe_unused stmmac_pci_resume(struct device *dev)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun struct pci_dev *pdev = to_pci_dev(dev);
253*4882a593Smuzhiyun int ret;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun pci_restore_state(pdev);
256*4882a593Smuzhiyun pci_set_power_state(pdev, PCI_D0);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun ret = pci_enable_device(pdev);
259*4882a593Smuzhiyun if (ret)
260*4882a593Smuzhiyun return ret;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun pci_set_master(pdev);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun return stmmac_resume(dev);
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* synthetic ID, no official vendor */
270*4882a593Smuzhiyun #define PCI_VENDOR_ID_STMMAC 0x0700
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun #define PCI_DEVICE_ID_STMMAC_STMMAC 0x1108
273*4882a593Smuzhiyun #define PCI_DEVICE_ID_SYNOPSYS_GMAC5_ID 0x7102
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static const struct pci_device_id stmmac_id_table[] = {
276*4882a593Smuzhiyun { PCI_DEVICE_DATA(STMMAC, STMMAC, &stmmac_pci_info) },
277*4882a593Smuzhiyun { PCI_DEVICE_DATA(STMICRO, MAC, &stmmac_pci_info) },
278*4882a593Smuzhiyun { PCI_DEVICE_DATA(SYNOPSYS, GMAC5_ID, &snps_gmac5_pci_info) },
279*4882a593Smuzhiyun {}
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, stmmac_id_table);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun static struct pci_driver stmmac_pci_driver = {
285*4882a593Smuzhiyun .name = STMMAC_RESOURCE_NAME,
286*4882a593Smuzhiyun .id_table = stmmac_id_table,
287*4882a593Smuzhiyun .probe = stmmac_pci_probe,
288*4882a593Smuzhiyun .remove = stmmac_pci_remove,
289*4882a593Smuzhiyun .driver = {
290*4882a593Smuzhiyun .pm = &stmmac_pm_ops,
291*4882a593Smuzhiyun },
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun module_pci_driver(stmmac_pci_driver);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet PCI driver");
297*4882a593Smuzhiyun MODULE_AUTHOR("Rayagond Kokatanur <rayagond.kokatanur@vayavyalabs.com>");
298*4882a593Smuzhiyun MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
299*4882a593Smuzhiyun MODULE_LICENSE("GPL");
300