1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*******************************************************************************
3*4882a593Smuzhiyun Copyright (C) 2013 Vayavya Labs Pvt Ltd
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun This implements all the API for managing HW timestamp & PTP.
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
9*4882a593Smuzhiyun Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*4882a593Smuzhiyun *******************************************************************************/
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/iopoll.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include "common.h"
16*4882a593Smuzhiyun #include "stmmac_ptp.h"
17*4882a593Smuzhiyun
config_hw_tstamping(void __iomem * ioaddr,u32 data)18*4882a593Smuzhiyun static void config_hw_tstamping(void __iomem *ioaddr, u32 data)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun writel(data, ioaddr + PTP_TCR);
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
config_sub_second_increment(void __iomem * ioaddr,u32 ptp_clock,int gmac4,u32 * ssinc)23*4882a593Smuzhiyun static void config_sub_second_increment(void __iomem *ioaddr,
24*4882a593Smuzhiyun u32 ptp_clock, int gmac4, u32 *ssinc)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun u32 value = readl(ioaddr + PTP_TCR);
27*4882a593Smuzhiyun unsigned long data;
28*4882a593Smuzhiyun u32 reg_value;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second
31*4882a593Smuzhiyun * increment to twice the number of nanoseconds of a clock cycle.
32*4882a593Smuzhiyun * The calculation of the default_addend value by the caller will set it
33*4882a593Smuzhiyun * to mid-range = 2^31 when the remainder of this division is zero,
34*4882a593Smuzhiyun * which will make the accumulator overflow once every 2 ptp_clock
35*4882a593Smuzhiyun * cycles, adding twice the number of nanoseconds of a clock cycle :
36*4882a593Smuzhiyun * 2000000000ULL / ptp_clock.
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun if (value & PTP_TCR_TSCFUPDT)
39*4882a593Smuzhiyun data = (2000000000ULL / ptp_clock);
40*4882a593Smuzhiyun else
41*4882a593Smuzhiyun data = (1000000000ULL / ptp_clock);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* 0.465ns accuracy */
44*4882a593Smuzhiyun if (!(value & PTP_TCR_TSCTRLSSR))
45*4882a593Smuzhiyun data = (data * 1000) / 465;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun data &= PTP_SSIR_SSINC_MASK;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun reg_value = data;
50*4882a593Smuzhiyun if (gmac4)
51*4882a593Smuzhiyun reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun writel(reg_value, ioaddr + PTP_SSIR);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (ssinc)
56*4882a593Smuzhiyun *ssinc = data;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
init_systime(void __iomem * ioaddr,u32 sec,u32 nsec)59*4882a593Smuzhiyun static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun u32 value;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun writel(sec, ioaddr + PTP_STSUR);
64*4882a593Smuzhiyun writel(nsec, ioaddr + PTP_STNSUR);
65*4882a593Smuzhiyun /* issue command to initialize the system time value */
66*4882a593Smuzhiyun value = readl(ioaddr + PTP_TCR);
67*4882a593Smuzhiyun value |= PTP_TCR_TSINIT;
68*4882a593Smuzhiyun writel(value, ioaddr + PTP_TCR);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* wait for present system time initialize to complete */
71*4882a593Smuzhiyun return readl_poll_timeout_atomic(ioaddr + PTP_TCR, value,
72*4882a593Smuzhiyun !(value & PTP_TCR_TSINIT),
73*4882a593Smuzhiyun 10, 100000);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
config_addend(void __iomem * ioaddr,u32 addend)76*4882a593Smuzhiyun static int config_addend(void __iomem *ioaddr, u32 addend)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun u32 value;
79*4882a593Smuzhiyun int limit;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun writel(addend, ioaddr + PTP_TAR);
82*4882a593Smuzhiyun /* issue command to update the addend value */
83*4882a593Smuzhiyun value = readl(ioaddr + PTP_TCR);
84*4882a593Smuzhiyun value |= PTP_TCR_TSADDREG;
85*4882a593Smuzhiyun writel(value, ioaddr + PTP_TCR);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* wait for present addend update to complete */
88*4882a593Smuzhiyun limit = 10;
89*4882a593Smuzhiyun while (limit--) {
90*4882a593Smuzhiyun if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG))
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun mdelay(10);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun if (limit < 0)
95*4882a593Smuzhiyun return -EBUSY;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
adjust_systime(void __iomem * ioaddr,u32 sec,u32 nsec,int add_sub,int gmac4)100*4882a593Smuzhiyun static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
101*4882a593Smuzhiyun int add_sub, int gmac4)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun u32 value;
104*4882a593Smuzhiyun int limit;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (add_sub) {
107*4882a593Smuzhiyun /* If the new sec value needs to be subtracted with
108*4882a593Smuzhiyun * the system time, then MAC_STSUR reg should be
109*4882a593Smuzhiyun * programmed with (2^32 – <new_sec_value>)
110*4882a593Smuzhiyun */
111*4882a593Smuzhiyun if (gmac4)
112*4882a593Smuzhiyun sec = -sec;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun value = readl(ioaddr + PTP_TCR);
115*4882a593Smuzhiyun if (value & PTP_TCR_TSCTRLSSR)
116*4882a593Smuzhiyun nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
117*4882a593Smuzhiyun else
118*4882a593Smuzhiyun nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun writel(sec, ioaddr + PTP_STSUR);
122*4882a593Smuzhiyun value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec;
123*4882a593Smuzhiyun writel(value, ioaddr + PTP_STNSUR);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* issue command to initialize the system time value */
126*4882a593Smuzhiyun value = readl(ioaddr + PTP_TCR);
127*4882a593Smuzhiyun value |= PTP_TCR_TSUPDT;
128*4882a593Smuzhiyun writel(value, ioaddr + PTP_TCR);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* wait for present system time adjust/update to complete */
131*4882a593Smuzhiyun limit = 10;
132*4882a593Smuzhiyun while (limit--) {
133*4882a593Smuzhiyun if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT))
134*4882a593Smuzhiyun break;
135*4882a593Smuzhiyun mdelay(10);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun if (limit < 0)
138*4882a593Smuzhiyun return -EBUSY;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
get_systime(void __iomem * ioaddr,u64 * systime)143*4882a593Smuzhiyun static void get_systime(void __iomem *ioaddr, u64 *systime)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun u64 ns, sec0, sec1;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* Get the TSS value */
148*4882a593Smuzhiyun sec1 = readl_relaxed(ioaddr + PTP_STSR);
149*4882a593Smuzhiyun do {
150*4882a593Smuzhiyun sec0 = sec1;
151*4882a593Smuzhiyun /* Get the TSSS value */
152*4882a593Smuzhiyun ns = readl_relaxed(ioaddr + PTP_STNSR);
153*4882a593Smuzhiyun /* Get the TSS value */
154*4882a593Smuzhiyun sec1 = readl_relaxed(ioaddr + PTP_STSR);
155*4882a593Smuzhiyun } while (sec0 != sec1);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun if (systime)
158*4882a593Smuzhiyun *systime = ns + (sec1 * 1000000000ULL);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun const struct stmmac_hwtimestamp stmmac_ptp = {
162*4882a593Smuzhiyun .config_hw_tstamping = config_hw_tstamping,
163*4882a593Smuzhiyun .init_systime = init_systime,
164*4882a593Smuzhiyun .config_sub_second_increment = config_sub_second_increment,
165*4882a593Smuzhiyun .config_addend = config_addend,
166*4882a593Smuzhiyun .adjust_systime = adjust_systime,
167*4882a593Smuzhiyun .get_systime = get_systime,
168*4882a593Smuzhiyun };
169