1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*******************************************************************************
3*4882a593Smuzhiyun Copyright (C) 2007-2009 STMicroelectronics Ltd
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7*4882a593Smuzhiyun *******************************************************************************/
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __STMMAC_H__
10*4882a593Smuzhiyun #define __STMMAC_H__
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define STMMAC_RESOURCE_NAME "stmmaceth"
13*4882a593Smuzhiyun #define DRV_MODULE_VERSION "Jan_2016"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/clk.h>
16*4882a593Smuzhiyun #include <linux/if_vlan.h>
17*4882a593Smuzhiyun #include <linux/stmmac.h>
18*4882a593Smuzhiyun #include <linux/phylink.h>
19*4882a593Smuzhiyun #include <linux/pci.h>
20*4882a593Smuzhiyun #include "common.h"
21*4882a593Smuzhiyun #include <linux/ptp_clock_kernel.h>
22*4882a593Smuzhiyun #include <linux/net_tstamp.h>
23*4882a593Smuzhiyun #include <linux/reset.h>
24*4882a593Smuzhiyun #include <net/page_pool.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct stmmac_resources {
27*4882a593Smuzhiyun void __iomem *addr;
28*4882a593Smuzhiyun const char *mac;
29*4882a593Smuzhiyun int wol_irq;
30*4882a593Smuzhiyun int lpi_irq;
31*4882a593Smuzhiyun int irq;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct stmmac_tx_info {
35*4882a593Smuzhiyun dma_addr_t buf;
36*4882a593Smuzhiyun bool map_as_page;
37*4882a593Smuzhiyun unsigned len;
38*4882a593Smuzhiyun bool last_segment;
39*4882a593Smuzhiyun bool is_jumbo;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define STMMAC_TBS_AVAIL BIT(0)
43*4882a593Smuzhiyun #define STMMAC_TBS_EN BIT(1)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Frequently used values are kept adjacent for cache effect */
46*4882a593Smuzhiyun struct stmmac_tx_queue {
47*4882a593Smuzhiyun u32 tx_count_frames;
48*4882a593Smuzhiyun int tbs;
49*4882a593Smuzhiyun struct timer_list txtimer;
50*4882a593Smuzhiyun u32 queue_index;
51*4882a593Smuzhiyun struct stmmac_priv *priv_data;
52*4882a593Smuzhiyun struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
53*4882a593Smuzhiyun struct dma_edesc *dma_entx;
54*4882a593Smuzhiyun struct dma_desc *dma_tx;
55*4882a593Smuzhiyun struct sk_buff **tx_skbuff;
56*4882a593Smuzhiyun struct stmmac_tx_info *tx_skbuff_dma;
57*4882a593Smuzhiyun unsigned int cur_tx;
58*4882a593Smuzhiyun unsigned int dirty_tx;
59*4882a593Smuzhiyun dma_addr_t dma_tx_phy;
60*4882a593Smuzhiyun u32 tx_tail_addr;
61*4882a593Smuzhiyun u32 mss;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct stmmac_rx_buffer {
65*4882a593Smuzhiyun struct page *page;
66*4882a593Smuzhiyun struct page *sec_page;
67*4882a593Smuzhiyun dma_addr_t addr;
68*4882a593Smuzhiyun dma_addr_t sec_addr;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct stmmac_rx_queue {
72*4882a593Smuzhiyun u32 rx_count_frames;
73*4882a593Smuzhiyun u32 queue_index;
74*4882a593Smuzhiyun struct page_pool *page_pool;
75*4882a593Smuzhiyun struct stmmac_rx_buffer *buf_pool;
76*4882a593Smuzhiyun struct stmmac_priv *priv_data;
77*4882a593Smuzhiyun struct dma_extended_desc *dma_erx;
78*4882a593Smuzhiyun struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
79*4882a593Smuzhiyun unsigned int cur_rx;
80*4882a593Smuzhiyun unsigned int dirty_rx;
81*4882a593Smuzhiyun u32 rx_zeroc_thresh;
82*4882a593Smuzhiyun dma_addr_t dma_rx_phy;
83*4882a593Smuzhiyun u32 rx_tail_addr;
84*4882a593Smuzhiyun unsigned int state_saved;
85*4882a593Smuzhiyun struct {
86*4882a593Smuzhiyun struct sk_buff *skb;
87*4882a593Smuzhiyun unsigned int len;
88*4882a593Smuzhiyun unsigned int error;
89*4882a593Smuzhiyun } state;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct stmmac_channel {
93*4882a593Smuzhiyun struct napi_struct rx_napi ____cacheline_aligned_in_smp;
94*4882a593Smuzhiyun struct napi_struct tx_napi ____cacheline_aligned_in_smp;
95*4882a593Smuzhiyun struct stmmac_priv *priv_data;
96*4882a593Smuzhiyun spinlock_t lock;
97*4882a593Smuzhiyun u32 index;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct stmmac_tc_entry {
101*4882a593Smuzhiyun bool in_use;
102*4882a593Smuzhiyun bool in_hw;
103*4882a593Smuzhiyun bool is_last;
104*4882a593Smuzhiyun bool is_frag;
105*4882a593Smuzhiyun void *frag_ptr;
106*4882a593Smuzhiyun unsigned int table_pos;
107*4882a593Smuzhiyun u32 handle;
108*4882a593Smuzhiyun u32 prio;
109*4882a593Smuzhiyun struct {
110*4882a593Smuzhiyun u32 match_data;
111*4882a593Smuzhiyun u32 match_en;
112*4882a593Smuzhiyun u8 af:1;
113*4882a593Smuzhiyun u8 rf:1;
114*4882a593Smuzhiyun u8 im:1;
115*4882a593Smuzhiyun u8 nc:1;
116*4882a593Smuzhiyun u8 res1:4;
117*4882a593Smuzhiyun u8 frame_offset;
118*4882a593Smuzhiyun u8 ok_index;
119*4882a593Smuzhiyun u8 dma_ch_no;
120*4882a593Smuzhiyun u32 res2;
121*4882a593Smuzhiyun } __packed val;
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #define STMMAC_PPS_MAX 4
125*4882a593Smuzhiyun struct stmmac_pps_cfg {
126*4882a593Smuzhiyun bool available;
127*4882a593Smuzhiyun struct timespec64 start;
128*4882a593Smuzhiyun struct timespec64 period;
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun struct stmmac_rss {
132*4882a593Smuzhiyun int enable;
133*4882a593Smuzhiyun u8 key[STMMAC_RSS_HASH_KEY_SIZE];
134*4882a593Smuzhiyun u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun #define STMMAC_FLOW_ACTION_DROP BIT(0)
138*4882a593Smuzhiyun struct stmmac_flow_entry {
139*4882a593Smuzhiyun unsigned long cookie;
140*4882a593Smuzhiyun unsigned long action;
141*4882a593Smuzhiyun u8 ip_proto;
142*4882a593Smuzhiyun int in_use;
143*4882a593Smuzhiyun int idx;
144*4882a593Smuzhiyun int is_l4;
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun struct stmmac_priv {
148*4882a593Smuzhiyun /* Frequently used values are kept adjacent for cache effect */
149*4882a593Smuzhiyun u32 tx_coal_frames;
150*4882a593Smuzhiyun u32 tx_coal_timer;
151*4882a593Smuzhiyun u32 rx_coal_frames;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun int tx_coalesce;
154*4882a593Smuzhiyun int hwts_tx_en;
155*4882a593Smuzhiyun bool tx_path_in_lpi_mode;
156*4882a593Smuzhiyun bool tso;
157*4882a593Smuzhiyun int sph;
158*4882a593Smuzhiyun u32 sarc_type;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun unsigned int dma_buf_sz;
161*4882a593Smuzhiyun unsigned int rx_copybreak;
162*4882a593Smuzhiyun u32 rx_riwt;
163*4882a593Smuzhiyun int hwts_rx_en;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun void __iomem *ioaddr;
166*4882a593Smuzhiyun struct net_device *dev;
167*4882a593Smuzhiyun struct device *device;
168*4882a593Smuzhiyun struct mac_device_info *hw;
169*4882a593Smuzhiyun int (*hwif_quirks)(struct stmmac_priv *priv);
170*4882a593Smuzhiyun struct mutex lock;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* RX Queue */
173*4882a593Smuzhiyun struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
174*4882a593Smuzhiyun unsigned int dma_rx_size;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* TX Queue */
177*4882a593Smuzhiyun struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
178*4882a593Smuzhiyun unsigned int dma_tx_size;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun /* Generic channel for NAPI */
181*4882a593Smuzhiyun struct stmmac_channel channel[STMMAC_CH_MAX];
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun int speed;
184*4882a593Smuzhiyun unsigned int flow_ctrl;
185*4882a593Smuzhiyun unsigned int pause;
186*4882a593Smuzhiyun struct mii_bus *mii;
187*4882a593Smuzhiyun int mii_irq[PHY_MAX_ADDR];
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun struct phylink_config phylink_config;
190*4882a593Smuzhiyun struct phylink *phylink;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
193*4882a593Smuzhiyun struct stmmac_safety_stats sstats;
194*4882a593Smuzhiyun struct plat_stmmacenet_data *plat;
195*4882a593Smuzhiyun struct dma_features dma_cap;
196*4882a593Smuzhiyun struct stmmac_counters mmc;
197*4882a593Smuzhiyun int hw_cap_support;
198*4882a593Smuzhiyun int synopsys_id;
199*4882a593Smuzhiyun u32 msg_enable;
200*4882a593Smuzhiyun int wolopts;
201*4882a593Smuzhiyun int wol_irq;
202*4882a593Smuzhiyun int clk_csr;
203*4882a593Smuzhiyun struct timer_list eee_ctrl_timer;
204*4882a593Smuzhiyun int lpi_irq;
205*4882a593Smuzhiyun int eee_enabled;
206*4882a593Smuzhiyun int eee_active;
207*4882a593Smuzhiyun int tx_lpi_timer;
208*4882a593Smuzhiyun int tx_lpi_enabled;
209*4882a593Smuzhiyun int eee_tw_timer;
210*4882a593Smuzhiyun unsigned int mode;
211*4882a593Smuzhiyun unsigned int chain_mode;
212*4882a593Smuzhiyun int extend_desc;
213*4882a593Smuzhiyun struct hwtstamp_config tstamp_config;
214*4882a593Smuzhiyun struct ptp_clock *ptp_clock;
215*4882a593Smuzhiyun struct ptp_clock_info ptp_clock_ops;
216*4882a593Smuzhiyun unsigned int default_addend;
217*4882a593Smuzhiyun u32 sub_second_inc;
218*4882a593Smuzhiyun u32 systime_flags;
219*4882a593Smuzhiyun u32 adv_ts;
220*4882a593Smuzhiyun int use_riwt;
221*4882a593Smuzhiyun int irq_wake;
222*4882a593Smuzhiyun spinlock_t ptp_lock;
223*4882a593Smuzhiyun void __iomem *mmcaddr;
224*4882a593Smuzhiyun void __iomem *ptpaddr;
225*4882a593Smuzhiyun unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
228*4882a593Smuzhiyun struct dentry *dbgfs_dir;
229*4882a593Smuzhiyun #endif
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun unsigned long state;
232*4882a593Smuzhiyun struct workqueue_struct *wq;
233*4882a593Smuzhiyun struct work_struct service_task;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun /* TC Handling */
236*4882a593Smuzhiyun unsigned int tc_entries_max;
237*4882a593Smuzhiyun unsigned int tc_off_max;
238*4882a593Smuzhiyun struct stmmac_tc_entry *tc_entries;
239*4882a593Smuzhiyun unsigned int flow_entries_max;
240*4882a593Smuzhiyun struct stmmac_flow_entry *flow_entries;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /* Pulse Per Second output */
243*4882a593Smuzhiyun struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /* Receive Side Scaling */
246*4882a593Smuzhiyun struct stmmac_rss rss;
247*4882a593Smuzhiyun };
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun enum stmmac_state {
250*4882a593Smuzhiyun STMMAC_DOWN,
251*4882a593Smuzhiyun STMMAC_RESET_REQUESTED,
252*4882a593Smuzhiyun STMMAC_RESETING,
253*4882a593Smuzhiyun STMMAC_SERVICE_SCHED,
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun int stmmac_mdio_unregister(struct net_device *ndev);
257*4882a593Smuzhiyun int stmmac_mdio_register(struct net_device *ndev);
258*4882a593Smuzhiyun int stmmac_mdio_reset(struct mii_bus *mii);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun #ifdef CONFIG_STMMAC_ETHTOOL
261*4882a593Smuzhiyun void stmmac_set_ethtool_ops(struct net_device *netdev);
262*4882a593Smuzhiyun #else
stmmac_set_ethtool_ops(struct net_device * netdev)263*4882a593Smuzhiyun static inline void stmmac_set_ethtool_ops(struct net_device *netdev)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun #endif
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags);
269*4882a593Smuzhiyun void stmmac_ptp_register(struct stmmac_priv *priv);
270*4882a593Smuzhiyun void stmmac_ptp_unregister(struct stmmac_priv *priv);
271*4882a593Smuzhiyun int stmmac_resume(struct device *dev);
272*4882a593Smuzhiyun int stmmac_suspend(struct device *dev);
273*4882a593Smuzhiyun int stmmac_dvr_remove(struct device *dev);
274*4882a593Smuzhiyun int stmmac_dvr_probe(struct device *device,
275*4882a593Smuzhiyun struct plat_stmmacenet_data *plat_dat,
276*4882a593Smuzhiyun struct stmmac_resources *res);
277*4882a593Smuzhiyun void stmmac_disable_eee_mode(struct stmmac_priv *priv);
278*4882a593Smuzhiyun bool stmmac_eee_init(struct stmmac_priv *priv);
279*4882a593Smuzhiyun int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
280*4882a593Smuzhiyun int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
281*4882a593Smuzhiyun int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
284*4882a593Smuzhiyun void stmmac_selftest_run(struct net_device *dev,
285*4882a593Smuzhiyun struct ethtool_test *etest, u64 *buf);
286*4882a593Smuzhiyun void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
287*4882a593Smuzhiyun int stmmac_selftest_get_count(struct stmmac_priv *priv);
288*4882a593Smuzhiyun #else
stmmac_selftest_run(struct net_device * dev,struct ethtool_test * etest,u64 * buf)289*4882a593Smuzhiyun static inline void stmmac_selftest_run(struct net_device *dev,
290*4882a593Smuzhiyun struct ethtool_test *etest, u64 *buf)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun /* Not enabled */
293*4882a593Smuzhiyun }
stmmac_selftest_get_strings(struct stmmac_priv * priv,u8 * data)294*4882a593Smuzhiyun static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
295*4882a593Smuzhiyun u8 *data)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun /* Not enabled */
298*4882a593Smuzhiyun }
stmmac_selftest_get_count(struct stmmac_priv * priv)299*4882a593Smuzhiyun static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun return -EOPNOTSUPP;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun #endif /* CONFIG_STMMAC_SELFTESTS */
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun #endif /* __STMMAC_H__ */
306