1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /******************************************************************************* 3*4882a593Smuzhiyun MMC Header file 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Copyright (C) 2011 STMicroelectronics Ltd 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9*4882a593Smuzhiyun *******************************************************************************/ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __MMC_H__ 12*4882a593Smuzhiyun #define __MMC_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* MMC control register */ 15*4882a593Smuzhiyun /* When set, all counter are reset */ 16*4882a593Smuzhiyun #define MMC_CNTRL_COUNTER_RESET 0x1 17*4882a593Smuzhiyun /* When set, do not roll over zero after reaching the max value*/ 18*4882a593Smuzhiyun #define MMC_CNTRL_COUNTER_STOP_ROLLOVER 0x2 19*4882a593Smuzhiyun #define MMC_CNTRL_RESET_ON_READ 0x4 /* Reset after reading */ 20*4882a593Smuzhiyun #define MMC_CNTRL_COUNTER_FREEZER 0x8 /* Freeze counter values to the 21*4882a593Smuzhiyun * current value.*/ 22*4882a593Smuzhiyun #define MMC_CNTRL_PRESET 0x10 23*4882a593Smuzhiyun #define MMC_CNTRL_FULL_HALF_PRESET 0x20 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define MMC_GMAC4_OFFSET 0x700 26*4882a593Smuzhiyun #define MMC_GMAC3_X_OFFSET 0x100 27*4882a593Smuzhiyun #define MMC_XGMAC_OFFSET 0x800 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct stmmac_counters { 30*4882a593Smuzhiyun unsigned int mmc_tx_octetcount_gb; 31*4882a593Smuzhiyun unsigned int mmc_tx_framecount_gb; 32*4882a593Smuzhiyun unsigned int mmc_tx_broadcastframe_g; 33*4882a593Smuzhiyun unsigned int mmc_tx_multicastframe_g; 34*4882a593Smuzhiyun unsigned int mmc_tx_64_octets_gb; 35*4882a593Smuzhiyun unsigned int mmc_tx_65_to_127_octets_gb; 36*4882a593Smuzhiyun unsigned int mmc_tx_128_to_255_octets_gb; 37*4882a593Smuzhiyun unsigned int mmc_tx_256_to_511_octets_gb; 38*4882a593Smuzhiyun unsigned int mmc_tx_512_to_1023_octets_gb; 39*4882a593Smuzhiyun unsigned int mmc_tx_1024_to_max_octets_gb; 40*4882a593Smuzhiyun unsigned int mmc_tx_unicast_gb; 41*4882a593Smuzhiyun unsigned int mmc_tx_multicast_gb; 42*4882a593Smuzhiyun unsigned int mmc_tx_broadcast_gb; 43*4882a593Smuzhiyun unsigned int mmc_tx_underflow_error; 44*4882a593Smuzhiyun unsigned int mmc_tx_singlecol_g; 45*4882a593Smuzhiyun unsigned int mmc_tx_multicol_g; 46*4882a593Smuzhiyun unsigned int mmc_tx_deferred; 47*4882a593Smuzhiyun unsigned int mmc_tx_latecol; 48*4882a593Smuzhiyun unsigned int mmc_tx_exesscol; 49*4882a593Smuzhiyun unsigned int mmc_tx_carrier_error; 50*4882a593Smuzhiyun unsigned int mmc_tx_octetcount_g; 51*4882a593Smuzhiyun unsigned int mmc_tx_framecount_g; 52*4882a593Smuzhiyun unsigned int mmc_tx_excessdef; 53*4882a593Smuzhiyun unsigned int mmc_tx_pause_frame; 54*4882a593Smuzhiyun unsigned int mmc_tx_vlan_frame_g; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* MMC RX counter registers */ 57*4882a593Smuzhiyun unsigned int mmc_rx_framecount_gb; 58*4882a593Smuzhiyun unsigned int mmc_rx_octetcount_gb; 59*4882a593Smuzhiyun unsigned int mmc_rx_octetcount_g; 60*4882a593Smuzhiyun unsigned int mmc_rx_broadcastframe_g; 61*4882a593Smuzhiyun unsigned int mmc_rx_multicastframe_g; 62*4882a593Smuzhiyun unsigned int mmc_rx_crc_error; 63*4882a593Smuzhiyun unsigned int mmc_rx_align_error; 64*4882a593Smuzhiyun unsigned int mmc_rx_run_error; 65*4882a593Smuzhiyun unsigned int mmc_rx_jabber_error; 66*4882a593Smuzhiyun unsigned int mmc_rx_undersize_g; 67*4882a593Smuzhiyun unsigned int mmc_rx_oversize_g; 68*4882a593Smuzhiyun unsigned int mmc_rx_64_octets_gb; 69*4882a593Smuzhiyun unsigned int mmc_rx_65_to_127_octets_gb; 70*4882a593Smuzhiyun unsigned int mmc_rx_128_to_255_octets_gb; 71*4882a593Smuzhiyun unsigned int mmc_rx_256_to_511_octets_gb; 72*4882a593Smuzhiyun unsigned int mmc_rx_512_to_1023_octets_gb; 73*4882a593Smuzhiyun unsigned int mmc_rx_1024_to_max_octets_gb; 74*4882a593Smuzhiyun unsigned int mmc_rx_unicast_g; 75*4882a593Smuzhiyun unsigned int mmc_rx_length_error; 76*4882a593Smuzhiyun unsigned int mmc_rx_autofrangetype; 77*4882a593Smuzhiyun unsigned int mmc_rx_pause_frames; 78*4882a593Smuzhiyun unsigned int mmc_rx_fifo_overflow; 79*4882a593Smuzhiyun unsigned int mmc_rx_vlan_frames_gb; 80*4882a593Smuzhiyun unsigned int mmc_rx_watchdog_error; 81*4882a593Smuzhiyun /* IPC */ 82*4882a593Smuzhiyun unsigned int mmc_rx_ipc_intr_mask; 83*4882a593Smuzhiyun unsigned int mmc_rx_ipc_intr; 84*4882a593Smuzhiyun /* IPv4 */ 85*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_gd; 86*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_hderr; 87*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_nopay; 88*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_frag; 89*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_udsbl; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_gd_octets; 92*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_hderr_octets; 93*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_nopay_octets; 94*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_frag_octets; 95*4882a593Smuzhiyun unsigned int mmc_rx_ipv4_udsbl_octets; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* IPV6 */ 98*4882a593Smuzhiyun unsigned int mmc_rx_ipv6_gd_octets; 99*4882a593Smuzhiyun unsigned int mmc_rx_ipv6_hderr_octets; 100*4882a593Smuzhiyun unsigned int mmc_rx_ipv6_nopay_octets; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun unsigned int mmc_rx_ipv6_gd; 103*4882a593Smuzhiyun unsigned int mmc_rx_ipv6_hderr; 104*4882a593Smuzhiyun unsigned int mmc_rx_ipv6_nopay; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Protocols */ 107*4882a593Smuzhiyun unsigned int mmc_rx_udp_gd; 108*4882a593Smuzhiyun unsigned int mmc_rx_udp_err; 109*4882a593Smuzhiyun unsigned int mmc_rx_tcp_gd; 110*4882a593Smuzhiyun unsigned int mmc_rx_tcp_err; 111*4882a593Smuzhiyun unsigned int mmc_rx_icmp_gd; 112*4882a593Smuzhiyun unsigned int mmc_rx_icmp_err; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun unsigned int mmc_rx_udp_gd_octets; 115*4882a593Smuzhiyun unsigned int mmc_rx_udp_err_octets; 116*4882a593Smuzhiyun unsigned int mmc_rx_tcp_gd_octets; 117*4882a593Smuzhiyun unsigned int mmc_rx_tcp_err_octets; 118*4882a593Smuzhiyun unsigned int mmc_rx_icmp_gd_octets; 119*4882a593Smuzhiyun unsigned int mmc_rx_icmp_err_octets; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* FPE */ 122*4882a593Smuzhiyun unsigned int mmc_tx_fpe_fragment_cntr; 123*4882a593Smuzhiyun unsigned int mmc_tx_hold_req_cntr; 124*4882a593Smuzhiyun unsigned int mmc_rx_packet_assembly_err_cntr; 125*4882a593Smuzhiyun unsigned int mmc_rx_packet_smd_err_cntr; 126*4882a593Smuzhiyun unsigned int mmc_rx_packet_assembly_ok_cntr; 127*4882a593Smuzhiyun unsigned int mmc_rx_fpe_fragment_cntr; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #endif /* __MMC_H__ */ 131