1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4*4882a593Smuzhiyun * stmmac HW Interface Handling
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include "common.h"
8*4882a593Smuzhiyun #include "stmmac.h"
9*4882a593Smuzhiyun #include "stmmac_ptp.h"
10*4882a593Smuzhiyun
stmmac_get_id(struct stmmac_priv * priv,u32 id_reg)11*4882a593Smuzhiyun static u32 stmmac_get_id(struct stmmac_priv *priv, u32 id_reg)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun u32 reg = readl(priv->ioaddr + id_reg);
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun if (!reg) {
16*4882a593Smuzhiyun dev_info(priv->device, "Version ID not available\n");
17*4882a593Smuzhiyun return 0x0;
18*4882a593Smuzhiyun }
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun dev_info(priv->device, "User ID: 0x%x, Synopsys ID: 0x%x\n",
21*4882a593Smuzhiyun (unsigned int)(reg & GENMASK(15, 8)) >> 8,
22*4882a593Smuzhiyun (unsigned int)(reg & GENMASK(7, 0)));
23*4882a593Smuzhiyun return reg & GENMASK(7, 0);
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun
stmmac_get_dev_id(struct stmmac_priv * priv,u32 id_reg)26*4882a593Smuzhiyun static u32 stmmac_get_dev_id(struct stmmac_priv *priv, u32 id_reg)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun u32 reg = readl(priv->ioaddr + id_reg);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (!reg) {
31*4882a593Smuzhiyun dev_info(priv->device, "Version ID not available\n");
32*4882a593Smuzhiyun return 0x0;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return (reg & GENMASK(15, 8)) >> 8;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #ifdef CONFIG_STMMAC_FULL
stmmac_dwmac_mode_quirk(struct stmmac_priv * priv)39*4882a593Smuzhiyun static void stmmac_dwmac_mode_quirk(struct stmmac_priv *priv)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct mac_device_info *mac = priv->hw;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (priv->chain_mode) {
44*4882a593Smuzhiyun dev_info(priv->device, "Chain mode enabled\n");
45*4882a593Smuzhiyun priv->mode = STMMAC_CHAIN_MODE;
46*4882a593Smuzhiyun mac->mode = &chain_mode_ops;
47*4882a593Smuzhiyun } else {
48*4882a593Smuzhiyun dev_info(priv->device, "Ring mode enabled\n");
49*4882a593Smuzhiyun priv->mode = STMMAC_RING_MODE;
50*4882a593Smuzhiyun mac->mode = &ring_mode_ops;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
stmmac_dwmac1_quirks(struct stmmac_priv * priv)54*4882a593Smuzhiyun static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct mac_device_info *mac = priv->hw;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (priv->plat->enh_desc) {
59*4882a593Smuzhiyun dev_info(priv->device, "Enhanced/Alternate descriptors\n");
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* GMAC older than 3.50 has no extended descriptors */
62*4882a593Smuzhiyun if (priv->synopsys_id >= DWMAC_CORE_3_50) {
63*4882a593Smuzhiyun dev_info(priv->device, "Enabled extended descriptors\n");
64*4882a593Smuzhiyun priv->extend_desc = 1;
65*4882a593Smuzhiyun } else {
66*4882a593Smuzhiyun dev_warn(priv->device, "Extended descriptors not supported\n");
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun mac->desc = &enh_desc_ops;
70*4882a593Smuzhiyun } else {
71*4882a593Smuzhiyun dev_info(priv->device, "Normal descriptors\n");
72*4882a593Smuzhiyun mac->desc = &ndesc_ops;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun stmmac_dwmac_mode_quirk(priv);
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
stmmac_dwmac4_quirks(struct stmmac_priv * priv)79*4882a593Smuzhiyun static int stmmac_dwmac4_quirks(struct stmmac_priv *priv)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun stmmac_dwmac_mode_quirk(priv);
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
stmmac_dwxlgmac_quirks(struct stmmac_priv * priv)85*4882a593Smuzhiyun static int stmmac_dwxlgmac_quirks(struct stmmac_priv *priv)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun priv->hw->xlgmac = true;
88*4882a593Smuzhiyun return 0;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun #endif
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static const struct stmmac_hwif_entry {
93*4882a593Smuzhiyun bool gmac;
94*4882a593Smuzhiyun bool gmac4;
95*4882a593Smuzhiyun bool xgmac;
96*4882a593Smuzhiyun u32 min_id;
97*4882a593Smuzhiyun u32 dev_id;
98*4882a593Smuzhiyun const struct stmmac_regs_off regs;
99*4882a593Smuzhiyun const void *desc;
100*4882a593Smuzhiyun const void *dma;
101*4882a593Smuzhiyun const void *mac;
102*4882a593Smuzhiyun const void *hwtimestamp;
103*4882a593Smuzhiyun const void *mode;
104*4882a593Smuzhiyun const void *tc;
105*4882a593Smuzhiyun const void *mmc;
106*4882a593Smuzhiyun int (*setup)(struct stmmac_priv *priv);
107*4882a593Smuzhiyun int (*quirks)(struct stmmac_priv *priv);
108*4882a593Smuzhiyun } stmmac_hw[] = {
109*4882a593Smuzhiyun /* NOTE: New HW versions shall go to the end of this table */
110*4882a593Smuzhiyun #ifdef CONFIG_STMMAC_FULL
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun .gmac = false,
113*4882a593Smuzhiyun .gmac4 = false,
114*4882a593Smuzhiyun .xgmac = false,
115*4882a593Smuzhiyun .min_id = 0,
116*4882a593Smuzhiyun .regs = {
117*4882a593Smuzhiyun .ptp_off = PTP_GMAC3_X_OFFSET,
118*4882a593Smuzhiyun .mmc_off = MMC_GMAC3_X_OFFSET,
119*4882a593Smuzhiyun },
120*4882a593Smuzhiyun .desc = NULL,
121*4882a593Smuzhiyun .dma = &dwmac100_dma_ops,
122*4882a593Smuzhiyun .mac = &dwmac100_ops,
123*4882a593Smuzhiyun .hwtimestamp = &stmmac_ptp,
124*4882a593Smuzhiyun .mode = NULL,
125*4882a593Smuzhiyun .tc = NULL,
126*4882a593Smuzhiyun .mmc = &dwmac_mmc_ops,
127*4882a593Smuzhiyun .setup = dwmac100_setup,
128*4882a593Smuzhiyun .quirks = stmmac_dwmac1_quirks,
129*4882a593Smuzhiyun }, {
130*4882a593Smuzhiyun .gmac = true,
131*4882a593Smuzhiyun .gmac4 = false,
132*4882a593Smuzhiyun .xgmac = false,
133*4882a593Smuzhiyun .min_id = 0,
134*4882a593Smuzhiyun .regs = {
135*4882a593Smuzhiyun .ptp_off = PTP_GMAC3_X_OFFSET,
136*4882a593Smuzhiyun .mmc_off = MMC_GMAC3_X_OFFSET,
137*4882a593Smuzhiyun },
138*4882a593Smuzhiyun .desc = NULL,
139*4882a593Smuzhiyun .dma = &dwmac1000_dma_ops,
140*4882a593Smuzhiyun .mac = &dwmac1000_ops,
141*4882a593Smuzhiyun .hwtimestamp = &stmmac_ptp,
142*4882a593Smuzhiyun .mode = NULL,
143*4882a593Smuzhiyun .tc = NULL,
144*4882a593Smuzhiyun .mmc = &dwmac_mmc_ops,
145*4882a593Smuzhiyun .setup = dwmac1000_setup,
146*4882a593Smuzhiyun .quirks = stmmac_dwmac1_quirks,
147*4882a593Smuzhiyun }, {
148*4882a593Smuzhiyun .gmac = false,
149*4882a593Smuzhiyun .gmac4 = true,
150*4882a593Smuzhiyun .xgmac = false,
151*4882a593Smuzhiyun .min_id = 0,
152*4882a593Smuzhiyun .regs = {
153*4882a593Smuzhiyun .ptp_off = PTP_GMAC4_OFFSET,
154*4882a593Smuzhiyun .mmc_off = MMC_GMAC4_OFFSET,
155*4882a593Smuzhiyun },
156*4882a593Smuzhiyun .desc = &dwmac4_desc_ops,
157*4882a593Smuzhiyun .dma = &dwmac4_dma_ops,
158*4882a593Smuzhiyun .mac = &dwmac4_ops,
159*4882a593Smuzhiyun .hwtimestamp = &stmmac_ptp,
160*4882a593Smuzhiyun .mode = NULL,
161*4882a593Smuzhiyun .tc = &dwmac510_tc_ops,
162*4882a593Smuzhiyun .mmc = &dwmac_mmc_ops,
163*4882a593Smuzhiyun .setup = dwmac4_setup,
164*4882a593Smuzhiyun .quirks = stmmac_dwmac4_quirks,
165*4882a593Smuzhiyun }, {
166*4882a593Smuzhiyun .gmac = false,
167*4882a593Smuzhiyun .gmac4 = true,
168*4882a593Smuzhiyun .xgmac = false,
169*4882a593Smuzhiyun .min_id = DWMAC_CORE_4_00,
170*4882a593Smuzhiyun .regs = {
171*4882a593Smuzhiyun .ptp_off = PTP_GMAC4_OFFSET,
172*4882a593Smuzhiyun .mmc_off = MMC_GMAC4_OFFSET,
173*4882a593Smuzhiyun },
174*4882a593Smuzhiyun .desc = &dwmac4_desc_ops,
175*4882a593Smuzhiyun .dma = &dwmac4_dma_ops,
176*4882a593Smuzhiyun .mac = &dwmac410_ops,
177*4882a593Smuzhiyun .hwtimestamp = &stmmac_ptp,
178*4882a593Smuzhiyun .mode = &dwmac4_ring_mode_ops,
179*4882a593Smuzhiyun .tc = &dwmac510_tc_ops,
180*4882a593Smuzhiyun .mmc = &dwmac_mmc_ops,
181*4882a593Smuzhiyun .setup = dwmac4_setup,
182*4882a593Smuzhiyun .quirks = NULL,
183*4882a593Smuzhiyun },
184*4882a593Smuzhiyun #endif /* CONFIG_STMMAC_FULL */
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun .gmac = false,
187*4882a593Smuzhiyun .gmac4 = true,
188*4882a593Smuzhiyun .xgmac = false,
189*4882a593Smuzhiyun .min_id = DWMAC_CORE_4_10,
190*4882a593Smuzhiyun .regs = {
191*4882a593Smuzhiyun .ptp_off = PTP_GMAC4_OFFSET,
192*4882a593Smuzhiyun .mmc_off = MMC_GMAC4_OFFSET,
193*4882a593Smuzhiyun },
194*4882a593Smuzhiyun .desc = &dwmac4_desc_ops,
195*4882a593Smuzhiyun .dma = &dwmac410_dma_ops,
196*4882a593Smuzhiyun .mac = &dwmac410_ops,
197*4882a593Smuzhiyun .hwtimestamp = &stmmac_ptp,
198*4882a593Smuzhiyun .mode = &dwmac4_ring_mode_ops,
199*4882a593Smuzhiyun #ifdef CONFIG_STMMAC_FULL
200*4882a593Smuzhiyun .tc = &dwmac510_tc_ops,
201*4882a593Smuzhiyun #endif
202*4882a593Smuzhiyun .mmc = &dwmac_mmc_ops,
203*4882a593Smuzhiyun .setup = dwmac4_setup,
204*4882a593Smuzhiyun .quirks = NULL,
205*4882a593Smuzhiyun },
206*4882a593Smuzhiyun #ifdef CONFIG_STMMAC_FULL
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun .gmac = false,
209*4882a593Smuzhiyun .gmac4 = true,
210*4882a593Smuzhiyun .xgmac = false,
211*4882a593Smuzhiyun .min_id = DWMAC_CORE_5_10,
212*4882a593Smuzhiyun .regs = {
213*4882a593Smuzhiyun .ptp_off = PTP_GMAC4_OFFSET,
214*4882a593Smuzhiyun .mmc_off = MMC_GMAC4_OFFSET,
215*4882a593Smuzhiyun },
216*4882a593Smuzhiyun .desc = &dwmac4_desc_ops,
217*4882a593Smuzhiyun .dma = &dwmac410_dma_ops,
218*4882a593Smuzhiyun .mac = &dwmac510_ops,
219*4882a593Smuzhiyun .hwtimestamp = &stmmac_ptp,
220*4882a593Smuzhiyun .mode = &dwmac4_ring_mode_ops,
221*4882a593Smuzhiyun .tc = &dwmac510_tc_ops,
222*4882a593Smuzhiyun .mmc = &dwmac_mmc_ops,
223*4882a593Smuzhiyun .setup = dwmac4_setup,
224*4882a593Smuzhiyun .quirks = NULL,
225*4882a593Smuzhiyun }, {
226*4882a593Smuzhiyun .gmac = false,
227*4882a593Smuzhiyun .gmac4 = false,
228*4882a593Smuzhiyun .xgmac = true,
229*4882a593Smuzhiyun .min_id = DWXGMAC_CORE_2_10,
230*4882a593Smuzhiyun .dev_id = DWXGMAC_ID,
231*4882a593Smuzhiyun .regs = {
232*4882a593Smuzhiyun .ptp_off = PTP_XGMAC_OFFSET,
233*4882a593Smuzhiyun .mmc_off = MMC_XGMAC_OFFSET,
234*4882a593Smuzhiyun },
235*4882a593Smuzhiyun .desc = &dwxgmac210_desc_ops,
236*4882a593Smuzhiyun .dma = &dwxgmac210_dma_ops,
237*4882a593Smuzhiyun .mac = &dwxgmac210_ops,
238*4882a593Smuzhiyun .hwtimestamp = &stmmac_ptp,
239*4882a593Smuzhiyun .mode = NULL,
240*4882a593Smuzhiyun .tc = &dwmac510_tc_ops,
241*4882a593Smuzhiyun .mmc = &dwxgmac_mmc_ops,
242*4882a593Smuzhiyun .setup = dwxgmac2_setup,
243*4882a593Smuzhiyun .quirks = NULL,
244*4882a593Smuzhiyun }, {
245*4882a593Smuzhiyun .gmac = false,
246*4882a593Smuzhiyun .gmac4 = false,
247*4882a593Smuzhiyun .xgmac = true,
248*4882a593Smuzhiyun .min_id = DWXLGMAC_CORE_2_00,
249*4882a593Smuzhiyun .dev_id = DWXLGMAC_ID,
250*4882a593Smuzhiyun .regs = {
251*4882a593Smuzhiyun .ptp_off = PTP_XGMAC_OFFSET,
252*4882a593Smuzhiyun .mmc_off = MMC_XGMAC_OFFSET,
253*4882a593Smuzhiyun },
254*4882a593Smuzhiyun .desc = &dwxgmac210_desc_ops,
255*4882a593Smuzhiyun .dma = &dwxgmac210_dma_ops,
256*4882a593Smuzhiyun .mac = &dwxlgmac2_ops,
257*4882a593Smuzhiyun .hwtimestamp = &stmmac_ptp,
258*4882a593Smuzhiyun .mode = NULL,
259*4882a593Smuzhiyun .tc = &dwmac510_tc_ops,
260*4882a593Smuzhiyun .mmc = &dwxgmac_mmc_ops,
261*4882a593Smuzhiyun .setup = dwxlgmac2_setup,
262*4882a593Smuzhiyun .quirks = stmmac_dwxlgmac_quirks,
263*4882a593Smuzhiyun },
264*4882a593Smuzhiyun #endif
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun
stmmac_hwif_init(struct stmmac_priv * priv)267*4882a593Smuzhiyun int stmmac_hwif_init(struct stmmac_priv *priv)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun bool needs_xgmac = priv->plat->has_xgmac;
270*4882a593Smuzhiyun bool needs_gmac4 = priv->plat->has_gmac4;
271*4882a593Smuzhiyun bool needs_gmac = priv->plat->has_gmac;
272*4882a593Smuzhiyun const struct stmmac_hwif_entry *entry;
273*4882a593Smuzhiyun struct mac_device_info *mac;
274*4882a593Smuzhiyun bool needs_setup = true;
275*4882a593Smuzhiyun u32 id, dev_id = 0;
276*4882a593Smuzhiyun int i, ret;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun if (needs_gmac) {
279*4882a593Smuzhiyun id = stmmac_get_id(priv, GMAC_VERSION);
280*4882a593Smuzhiyun } else if (needs_gmac4 || needs_xgmac) {
281*4882a593Smuzhiyun id = stmmac_get_id(priv, GMAC4_VERSION);
282*4882a593Smuzhiyun if (needs_xgmac)
283*4882a593Smuzhiyun dev_id = stmmac_get_dev_id(priv, GMAC4_VERSION);
284*4882a593Smuzhiyun } else {
285*4882a593Smuzhiyun id = 0;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* Save ID for later use */
289*4882a593Smuzhiyun priv->synopsys_id = id;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /* Lets assume some safe values first */
292*4882a593Smuzhiyun priv->ptpaddr = priv->ioaddr +
293*4882a593Smuzhiyun (needs_gmac4 ? PTP_GMAC4_OFFSET : PTP_GMAC3_X_OFFSET);
294*4882a593Smuzhiyun priv->mmcaddr = priv->ioaddr +
295*4882a593Smuzhiyun (needs_gmac4 ? MMC_GMAC4_OFFSET : MMC_GMAC3_X_OFFSET);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /* Check for HW specific setup first */
298*4882a593Smuzhiyun if (priv->plat->setup) {
299*4882a593Smuzhiyun mac = priv->plat->setup(priv);
300*4882a593Smuzhiyun needs_setup = false;
301*4882a593Smuzhiyun } else {
302*4882a593Smuzhiyun mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if (!mac)
306*4882a593Smuzhiyun return -ENOMEM;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* Fallback to generic HW */
309*4882a593Smuzhiyun for (i = ARRAY_SIZE(stmmac_hw) - 1; i >= 0; i--) {
310*4882a593Smuzhiyun entry = &stmmac_hw[i];
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun if (needs_gmac ^ entry->gmac)
313*4882a593Smuzhiyun continue;
314*4882a593Smuzhiyun if (needs_gmac4 ^ entry->gmac4)
315*4882a593Smuzhiyun continue;
316*4882a593Smuzhiyun if (needs_xgmac ^ entry->xgmac)
317*4882a593Smuzhiyun continue;
318*4882a593Smuzhiyun /* Use synopsys_id var because some setups can override this */
319*4882a593Smuzhiyun if (priv->synopsys_id < entry->min_id)
320*4882a593Smuzhiyun continue;
321*4882a593Smuzhiyun if (needs_xgmac && (dev_id ^ entry->dev_id))
322*4882a593Smuzhiyun continue;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /* Only use generic HW helpers if needed */
325*4882a593Smuzhiyun mac->desc = mac->desc ? : entry->desc;
326*4882a593Smuzhiyun mac->dma = mac->dma ? : entry->dma;
327*4882a593Smuzhiyun mac->mac = mac->mac ? : entry->mac;
328*4882a593Smuzhiyun mac->ptp = mac->ptp ? : entry->hwtimestamp;
329*4882a593Smuzhiyun mac->mode = mac->mode ? : entry->mode;
330*4882a593Smuzhiyun mac->tc = mac->tc ? : entry->tc;
331*4882a593Smuzhiyun mac->mmc = mac->mmc ? : entry->mmc;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun priv->hw = mac;
334*4882a593Smuzhiyun priv->ptpaddr = priv->ioaddr + entry->regs.ptp_off;
335*4882a593Smuzhiyun priv->mmcaddr = priv->ioaddr + entry->regs.mmc_off;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /* Entry found */
338*4882a593Smuzhiyun if (needs_setup) {
339*4882a593Smuzhiyun ret = entry->setup(priv);
340*4882a593Smuzhiyun if (ret)
341*4882a593Smuzhiyun return ret;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun /* Save quirks, if needed for posterior use */
345*4882a593Smuzhiyun priv->hwif_quirks = entry->quirks;
346*4882a593Smuzhiyun return 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun dev_err(priv->device, "Failed to find HW IF (id=0x%x, gmac=%d/%d)\n",
350*4882a593Smuzhiyun id, needs_gmac, needs_gmac4);
351*4882a593Smuzhiyun return -EINVAL;
352*4882a593Smuzhiyun }
353