1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun // Copyright (c) 2017 Synopsys, Inc. and/or its affiliates. 3*4882a593Smuzhiyun // stmmac Support for 5.xx Ethernet QoS cores 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __DWMAC5_H__ 6*4882a593Smuzhiyun #define __DWMAC5_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define MAC_DPP_FSM_INT_STATUS 0x00000140 9*4882a593Smuzhiyun #define MAC_AXI_SLV_DPE_ADDR_STATUS 0x00000144 10*4882a593Smuzhiyun #define MAC_FSM_CONTROL 0x00000148 11*4882a593Smuzhiyun #define PRTYEN BIT(1) 12*4882a593Smuzhiyun #define TMOUTEN BIT(0) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MAC_FPE_CTRL_STS 0x00000234 15*4882a593Smuzhiyun #define EFPE BIT(0) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define MAC_PPS_CONTROL 0x00000b70 18*4882a593Smuzhiyun #define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1) 19*4882a593Smuzhiyun #define PPS_MINIDX(x) ((x) * 8) 20*4882a593Smuzhiyun #define PPSx_MASK(x) GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x)) 21*4882a593Smuzhiyun #define MCGRENx(x) BIT(PPS_MAXIDX(x)) 22*4882a593Smuzhiyun #define TRGTMODSELx(x, val) \ 23*4882a593Smuzhiyun GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \ 24*4882a593Smuzhiyun ((val) << (PPS_MAXIDX(x) - 2)) 25*4882a593Smuzhiyun #define PPSCMDx(x, val) \ 26*4882a593Smuzhiyun GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \ 27*4882a593Smuzhiyun ((val) << PPS_MINIDX(x)) 28*4882a593Smuzhiyun #define PPSEN0 BIT(4) 29*4882a593Smuzhiyun #define MAC_PPSx_TARGET_TIME_SEC(x) (0x00000b80 + ((x) * 0x10)) 30*4882a593Smuzhiyun #define MAC_PPSx_TARGET_TIME_NSEC(x) (0x00000b84 + ((x) * 0x10)) 31*4882a593Smuzhiyun #define TRGTBUSY0 BIT(31) 32*4882a593Smuzhiyun #define TTSL0 GENMASK(30, 0) 33*4882a593Smuzhiyun #define MAC_PPSx_INTERVAL(x) (0x00000b88 + ((x) * 0x10)) 34*4882a593Smuzhiyun #define MAC_PPSx_WIDTH(x) (0x00000b8c + ((x) * 0x10)) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define MTL_EST_CONTROL 0x00000c50 37*4882a593Smuzhiyun #define PTOV GENMASK(31, 24) 38*4882a593Smuzhiyun #define PTOV_SHIFT 24 39*4882a593Smuzhiyun #define SSWL BIT(1) 40*4882a593Smuzhiyun #define EEST BIT(0) 41*4882a593Smuzhiyun #define MTL_EST_GCL_CONTROL 0x00000c80 42*4882a593Smuzhiyun #define BTR_LOW 0x0 43*4882a593Smuzhiyun #define BTR_HIGH 0x1 44*4882a593Smuzhiyun #define CTR_LOW 0x2 45*4882a593Smuzhiyun #define CTR_HIGH 0x3 46*4882a593Smuzhiyun #define TER 0x4 47*4882a593Smuzhiyun #define LLR 0x5 48*4882a593Smuzhiyun #define ADDR_SHIFT 8 49*4882a593Smuzhiyun #define GCRR BIT(2) 50*4882a593Smuzhiyun #define SRWO BIT(0) 51*4882a593Smuzhiyun #define MTL_EST_GCL_DATA 0x00000c84 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MTL_RXP_CONTROL_STATUS 0x00000ca0 54*4882a593Smuzhiyun #define RXPI BIT(31) 55*4882a593Smuzhiyun #define NPE GENMASK(23, 16) 56*4882a593Smuzhiyun #define NVE GENMASK(7, 0) 57*4882a593Smuzhiyun #define MTL_RXP_IACC_CTRL_STATUS 0x00000cb0 58*4882a593Smuzhiyun #define STARTBUSY BIT(31) 59*4882a593Smuzhiyun #define RXPEIEC GENMASK(22, 21) 60*4882a593Smuzhiyun #define RXPEIEE BIT(20) 61*4882a593Smuzhiyun #define WRRDN BIT(16) 62*4882a593Smuzhiyun #define ADDR GENMASK(15, 0) 63*4882a593Smuzhiyun #define MTL_RXP_IACC_DATA 0x00000cb4 64*4882a593Smuzhiyun #define MTL_ECC_CONTROL 0x00000cc0 65*4882a593Smuzhiyun #define TSOEE BIT(4) 66*4882a593Smuzhiyun #define MRXPEE BIT(3) 67*4882a593Smuzhiyun #define MESTEE BIT(2) 68*4882a593Smuzhiyun #define MRXEE BIT(1) 69*4882a593Smuzhiyun #define MTXEE BIT(0) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define MTL_SAFETY_INT_STATUS 0x00000cc4 72*4882a593Smuzhiyun #define MCSIS BIT(31) 73*4882a593Smuzhiyun #define MEUIS BIT(1) 74*4882a593Smuzhiyun #define MECIS BIT(0) 75*4882a593Smuzhiyun #define MTL_ECC_INT_ENABLE 0x00000cc8 76*4882a593Smuzhiyun #define RPCEIE BIT(12) 77*4882a593Smuzhiyun #define ECEIE BIT(8) 78*4882a593Smuzhiyun #define RXCEIE BIT(4) 79*4882a593Smuzhiyun #define TXCEIE BIT(0) 80*4882a593Smuzhiyun #define MTL_ECC_INT_STATUS 0x00000ccc 81*4882a593Smuzhiyun #define MTL_DPP_CONTROL 0x00000ce0 82*4882a593Smuzhiyun #define EPSI BIT(2) 83*4882a593Smuzhiyun #define OPE BIT(1) 84*4882a593Smuzhiyun #define EDPP BIT(0) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define DMA_SAFETY_INT_STATUS 0x00001080 87*4882a593Smuzhiyun #define MSUIS BIT(29) 88*4882a593Smuzhiyun #define MSCIS BIT(28) 89*4882a593Smuzhiyun #define DEUIS BIT(1) 90*4882a593Smuzhiyun #define DECIS BIT(0) 91*4882a593Smuzhiyun #define DMA_ECC_INT_ENABLE 0x00001084 92*4882a593Smuzhiyun #define TCEIE BIT(0) 93*4882a593Smuzhiyun #define DMA_ECC_INT_STATUS 0x00001088 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* EQoS version 5.xx VLAN Tag Filter Fail Packets Queuing */ 96*4882a593Smuzhiyun #define GMAC_RXQ_CTRL4 0x00000094 97*4882a593Smuzhiyun #define GMAC_RXQCTRL_VFFQ_MASK GENMASK(19, 17) 98*4882a593Smuzhiyun #define GMAC_RXQCTRL_VFFQ_SHIFT 17 99*4882a593Smuzhiyun #define GMAC_RXQCTRL_VFFQE BIT(16) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp); 102*4882a593Smuzhiyun int dwmac5_safety_feat_irq_status(struct net_device *ndev, 103*4882a593Smuzhiyun void __iomem *ioaddr, unsigned int asp, 104*4882a593Smuzhiyun struct stmmac_safety_stats *stats); 105*4882a593Smuzhiyun int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats, 106*4882a593Smuzhiyun int index, unsigned long *count, const char **desc); 107*4882a593Smuzhiyun int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries, 108*4882a593Smuzhiyun unsigned int count); 109*4882a593Smuzhiyun int dwmac5_flex_pps_config(void __iomem *ioaddr, int index, 110*4882a593Smuzhiyun struct stmmac_pps_cfg *cfg, bool enable, 111*4882a593Smuzhiyun u32 sub_second_inc, u32 systime_flags); 112*4882a593Smuzhiyun int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg, 113*4882a593Smuzhiyun unsigned int ptp_rate); 114*4882a593Smuzhiyun void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq, 115*4882a593Smuzhiyun bool enable); 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif /* __DWMAC5_H__ */ 118