1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header File to describe the DMA descriptors and related definitions specific 4*4882a593Smuzhiyun * for DesignWare databook 4.xx. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2015 STMicroelectronics Ltd 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Alexandre Torgue <alexandre.torgue@st.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __DWMAC4_DESCS_H__ 12*4882a593Smuzhiyun #define __DWMAC4_DESCS_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/bitops.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Normal transmit descriptor defines (without split feature) */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* TDES2 (read format) */ 19*4882a593Smuzhiyun #define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0) 20*4882a593Smuzhiyun #define TDES2_VLAN_TAG_MASK GENMASK(15, 14) 21*4882a593Smuzhiyun #define TDES2_VLAN_TAG_SHIFT 14 22*4882a593Smuzhiyun #define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16) 23*4882a593Smuzhiyun #define TDES2_BUFFER2_SIZE_MASK_SHIFT 16 24*4882a593Smuzhiyun #define TDES3_IVTIR_MASK GENMASK(19, 18) 25*4882a593Smuzhiyun #define TDES3_IVTIR_SHIFT 18 26*4882a593Smuzhiyun #define TDES3_IVLTV BIT(17) 27*4882a593Smuzhiyun #define TDES2_TIMESTAMP_ENABLE BIT(30) 28*4882a593Smuzhiyun #define TDES2_IVT_MASK GENMASK(31, 16) 29*4882a593Smuzhiyun #define TDES2_IVT_SHIFT 16 30*4882a593Smuzhiyun #define TDES2_INTERRUPT_ON_COMPLETION BIT(31) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* TDES3 (read format) */ 33*4882a593Smuzhiyun #define TDES3_PACKET_SIZE_MASK GENMASK(14, 0) 34*4882a593Smuzhiyun #define TDES3_VLAN_TAG GENMASK(15, 0) 35*4882a593Smuzhiyun #define TDES3_VLTV BIT(16) 36*4882a593Smuzhiyun #define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16) 37*4882a593Smuzhiyun #define TDES3_CHECKSUM_INSERTION_SHIFT 16 38*4882a593Smuzhiyun #define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0) 39*4882a593Smuzhiyun #define TDES3_TCP_SEGMENTATION_ENABLE BIT(18) 40*4882a593Smuzhiyun #define TDES3_HDR_LEN_SHIFT 19 41*4882a593Smuzhiyun #define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19) 42*4882a593Smuzhiyun #define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23) 43*4882a593Smuzhiyun #define TDES3_SA_INSERT_CTRL_SHIFT 23 44*4882a593Smuzhiyun #define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* TDES3 (write back format) */ 47*4882a593Smuzhiyun #define TDES3_IP_HDR_ERROR BIT(0) 48*4882a593Smuzhiyun #define TDES3_DEFERRED BIT(1) 49*4882a593Smuzhiyun #define TDES3_UNDERFLOW_ERROR BIT(2) 50*4882a593Smuzhiyun #define TDES3_EXCESSIVE_DEFERRAL BIT(3) 51*4882a593Smuzhiyun #define TDES3_COLLISION_COUNT_MASK GENMASK(7, 4) 52*4882a593Smuzhiyun #define TDES3_COLLISION_COUNT_SHIFT 4 53*4882a593Smuzhiyun #define TDES3_EXCESSIVE_COLLISION BIT(8) 54*4882a593Smuzhiyun #define TDES3_LATE_COLLISION BIT(9) 55*4882a593Smuzhiyun #define TDES3_NO_CARRIER BIT(10) 56*4882a593Smuzhiyun #define TDES3_LOSS_CARRIER BIT(11) 57*4882a593Smuzhiyun #define TDES3_PAYLOAD_ERROR BIT(12) 58*4882a593Smuzhiyun #define TDES3_PACKET_FLUSHED BIT(13) 59*4882a593Smuzhiyun #define TDES3_JABBER_TIMEOUT BIT(14) 60*4882a593Smuzhiyun #define TDES3_ERROR_SUMMARY BIT(15) 61*4882a593Smuzhiyun #define TDES3_TIMESTAMP_STATUS BIT(17) 62*4882a593Smuzhiyun #define TDES3_TIMESTAMP_STATUS_SHIFT 17 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* TDES3 context */ 65*4882a593Smuzhiyun #define TDES3_CTXT_TCMSSV BIT(26) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* TDES3 Common */ 68*4882a593Smuzhiyun #define TDES3_RS1V BIT(26) 69*4882a593Smuzhiyun #define TDES3_RS1V_SHIFT 26 70*4882a593Smuzhiyun #define TDES3_LAST_DESCRIPTOR BIT(28) 71*4882a593Smuzhiyun #define TDES3_LAST_DESCRIPTOR_SHIFT 28 72*4882a593Smuzhiyun #define TDES3_FIRST_DESCRIPTOR BIT(29) 73*4882a593Smuzhiyun #define TDES3_CONTEXT_TYPE BIT(30) 74*4882a593Smuzhiyun #define TDES3_CONTEXT_TYPE_SHIFT 30 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* TDES4 */ 77*4882a593Smuzhiyun #define TDES4_LTV BIT(31) 78*4882a593Smuzhiyun #define TDES4_LT GENMASK(7, 0) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* TDES5 */ 81*4882a593Smuzhiyun #define TDES5_LT GENMASK(31, 8) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* TDS3 use for both format (read and write back) */ 84*4882a593Smuzhiyun #define TDES3_OWN BIT(31) 85*4882a593Smuzhiyun #define TDES3_OWN_SHIFT 31 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Normal receive descriptor defines (without split feature) */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* RDES0 (write back format) */ 90*4882a593Smuzhiyun #define RDES0_VLAN_TAG_MASK GENMASK(15, 0) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* RDES1 (write back format) */ 93*4882a593Smuzhiyun #define RDES1_IP_PAYLOAD_TYPE_MASK GENMASK(2, 0) 94*4882a593Smuzhiyun #define RDES1_IP_HDR_ERROR BIT(3) 95*4882a593Smuzhiyun #define RDES1_IPV4_HEADER BIT(4) 96*4882a593Smuzhiyun #define RDES1_IPV6_HEADER BIT(5) 97*4882a593Smuzhiyun #define RDES1_IP_CSUM_BYPASSED BIT(6) 98*4882a593Smuzhiyun #define RDES1_IP_CSUM_ERROR BIT(7) 99*4882a593Smuzhiyun #define RDES1_PTP_MSG_TYPE_MASK GENMASK(11, 8) 100*4882a593Smuzhiyun #define RDES1_PTP_PACKET_TYPE BIT(12) 101*4882a593Smuzhiyun #define RDES1_PTP_VER BIT(13) 102*4882a593Smuzhiyun #define RDES1_TIMESTAMP_AVAILABLE BIT(14) 103*4882a593Smuzhiyun #define RDES1_TIMESTAMP_AVAILABLE_SHIFT 14 104*4882a593Smuzhiyun #define RDES1_TIMESTAMP_DROPPED BIT(15) 105*4882a593Smuzhiyun #define RDES1_IP_TYPE1_CSUM_MASK GENMASK(31, 16) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* RDES2 (write back format) */ 108*4882a593Smuzhiyun #define RDES2_L3_L4_HEADER_SIZE_MASK GENMASK(9, 0) 109*4882a593Smuzhiyun #define RDES2_VLAN_FILTER_STATUS BIT(15) 110*4882a593Smuzhiyun #define RDES2_SA_FILTER_FAIL BIT(16) 111*4882a593Smuzhiyun #define RDES2_DA_FILTER_FAIL BIT(17) 112*4882a593Smuzhiyun #define RDES2_HASH_FILTER_STATUS BIT(18) 113*4882a593Smuzhiyun #define RDES2_MAC_ADDR_MATCH_MASK GENMASK(26, 19) 114*4882a593Smuzhiyun #define RDES2_HASH_VALUE_MATCH_MASK GENMASK(26, 19) 115*4882a593Smuzhiyun #define RDES2_L3_FILTER_MATCH BIT(27) 116*4882a593Smuzhiyun #define RDES2_L4_FILTER_MATCH BIT(28) 117*4882a593Smuzhiyun #define RDES2_L3_L4_FILT_NB_MATCH_MASK GENMASK(27, 26) 118*4882a593Smuzhiyun #define RDES2_L3_L4_FILT_NB_MATCH_SHIFT 26 119*4882a593Smuzhiyun #define RDES2_HL GENMASK(9, 0) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* RDES3 (write back format) */ 122*4882a593Smuzhiyun #define RDES3_PACKET_SIZE_MASK GENMASK(14, 0) 123*4882a593Smuzhiyun #define RDES3_ERROR_SUMMARY BIT(15) 124*4882a593Smuzhiyun #define RDES3_PACKET_LEN_TYPE_MASK GENMASK(18, 16) 125*4882a593Smuzhiyun #define RDES3_DRIBBLE_ERROR BIT(19) 126*4882a593Smuzhiyun #define RDES3_RECEIVE_ERROR BIT(20) 127*4882a593Smuzhiyun #define RDES3_OVERFLOW_ERROR BIT(21) 128*4882a593Smuzhiyun #define RDES3_RECEIVE_WATCHDOG BIT(22) 129*4882a593Smuzhiyun #define RDES3_GIANT_PACKET BIT(23) 130*4882a593Smuzhiyun #define RDES3_CRC_ERROR BIT(24) 131*4882a593Smuzhiyun #define RDES3_RDES0_VALID BIT(25) 132*4882a593Smuzhiyun #define RDES3_RDES1_VALID BIT(26) 133*4882a593Smuzhiyun #define RDES3_RDES2_VALID BIT(27) 134*4882a593Smuzhiyun #define RDES3_LAST_DESCRIPTOR BIT(28) 135*4882a593Smuzhiyun #define RDES3_FIRST_DESCRIPTOR BIT(29) 136*4882a593Smuzhiyun #define RDES3_CONTEXT_DESCRIPTOR BIT(30) 137*4882a593Smuzhiyun #define RDES3_CONTEXT_DESCRIPTOR_SHIFT 30 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* RDES3 (read format) */ 140*4882a593Smuzhiyun #define RDES3_BUFFER1_VALID_ADDR BIT(24) 141*4882a593Smuzhiyun #define RDES3_BUFFER2_VALID_ADDR BIT(25) 142*4882a593Smuzhiyun #define RDES3_INT_ON_COMPLETION_EN BIT(30) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* TDS3 use for both format (read and write back) */ 145*4882a593Smuzhiyun #define RDES3_OWN BIT(31) 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #endif /* __DWMAC4_DESCS_H__ */ 148