1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2020, Intel Corporation 3*4882a593Smuzhiyun * DWMAC Intel header file 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DWMAC_INTEL_H__ 7*4882a593Smuzhiyun #define __DWMAC_INTEL_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define POLL_DELAY_US 8 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* SERDES Register */ 12*4882a593Smuzhiyun #define SERDES_GSR0 0x5 /* Global Status Reg0 */ 13*4882a593Smuzhiyun #define SERDES_GCR0 0xb /* Global Configuration Reg0 */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* SERDES defines */ 16*4882a593Smuzhiyun #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ 17*4882a593Smuzhiyun #define SERDES_RST BIT(2) /* Serdes Reset */ 18*4882a593Smuzhiyun #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ 19*4882a593Smuzhiyun #define SERDES_PWR_ST_SHIFT 4 20*4882a593Smuzhiyun #define SERDES_PWR_ST_P0 0x0 21*4882a593Smuzhiyun #define SERDES_PWR_ST_P3 0x3 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif /* __DWMAC_INTEL_H__ */ 24