xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-intel-plat.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Intel DWMAC platform driver
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright(C) 2020 Intel Corporation
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/ethtool.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/of_device.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/stmmac.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include "dwmac4.h"
15*4882a593Smuzhiyun #include "stmmac.h"
16*4882a593Smuzhiyun #include "stmmac_platform.h"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun struct intel_dwmac {
19*4882a593Smuzhiyun 	struct device *dev;
20*4882a593Smuzhiyun 	struct clk *tx_clk;
21*4882a593Smuzhiyun 	const struct intel_dwmac_data *data;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun struct intel_dwmac_data {
25*4882a593Smuzhiyun 	void (*fix_mac_speed)(void *priv, unsigned int speed);
26*4882a593Smuzhiyun 	unsigned long ptp_ref_clk_rate;
27*4882a593Smuzhiyun 	unsigned long tx_clk_rate;
28*4882a593Smuzhiyun 	bool tx_clk_en;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun 
kmb_eth_fix_mac_speed(void * priv,unsigned int speed)31*4882a593Smuzhiyun static void kmb_eth_fix_mac_speed(void *priv, unsigned int speed)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun 	struct intel_dwmac *dwmac = priv;
34*4882a593Smuzhiyun 	unsigned long rate;
35*4882a593Smuzhiyun 	int ret;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	rate = clk_get_rate(dwmac->tx_clk);
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	switch (speed) {
40*4882a593Smuzhiyun 	case SPEED_1000:
41*4882a593Smuzhiyun 		rate = 125000000;
42*4882a593Smuzhiyun 		break;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	case SPEED_100:
45*4882a593Smuzhiyun 		rate = 25000000;
46*4882a593Smuzhiyun 		break;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	case SPEED_10:
49*4882a593Smuzhiyun 		rate = 2500000;
50*4882a593Smuzhiyun 		break;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	default:
53*4882a593Smuzhiyun 		dev_err(dwmac->dev, "Invalid speed\n");
54*4882a593Smuzhiyun 		break;
55*4882a593Smuzhiyun 	}
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	ret = clk_set_rate(dwmac->tx_clk, rate);
58*4882a593Smuzhiyun 	if (ret)
59*4882a593Smuzhiyun 		dev_err(dwmac->dev, "Failed to configure tx clock rate\n");
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun static const struct intel_dwmac_data kmb_data = {
63*4882a593Smuzhiyun 	.fix_mac_speed = kmb_eth_fix_mac_speed,
64*4882a593Smuzhiyun 	.ptp_ref_clk_rate = 200000000,
65*4882a593Smuzhiyun 	.tx_clk_rate = 125000000,
66*4882a593Smuzhiyun 	.tx_clk_en = true,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun static const struct of_device_id intel_eth_plat_match[] = {
70*4882a593Smuzhiyun 	{ .compatible = "intel,keembay-dwmac", .data = &kmb_data },
71*4882a593Smuzhiyun 	{ }
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, intel_eth_plat_match);
74*4882a593Smuzhiyun 
intel_eth_plat_probe(struct platform_device * pdev)75*4882a593Smuzhiyun static int intel_eth_plat_probe(struct platform_device *pdev)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	struct net_device *ndev = platform_get_drvdata(pdev);
78*4882a593Smuzhiyun 	struct stmmac_priv *priv = netdev_priv(ndev);
79*4882a593Smuzhiyun 	struct plat_stmmacenet_data *plat_dat;
80*4882a593Smuzhiyun 	struct stmmac_resources stmmac_res;
81*4882a593Smuzhiyun 	const struct of_device_id *match;
82*4882a593Smuzhiyun 	struct intel_dwmac *dwmac;
83*4882a593Smuzhiyun 	unsigned long rate;
84*4882a593Smuzhiyun 	int ret;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	plat_dat = priv->plat;
87*4882a593Smuzhiyun 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
88*4882a593Smuzhiyun 	if (ret)
89*4882a593Smuzhiyun 		return ret;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
92*4882a593Smuzhiyun 	if (IS_ERR(plat_dat)) {
93*4882a593Smuzhiyun 		dev_err(&pdev->dev, "dt configuration failed\n");
94*4882a593Smuzhiyun 		return PTR_ERR(plat_dat);
95*4882a593Smuzhiyun 	}
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
98*4882a593Smuzhiyun 	if (!dwmac) {
99*4882a593Smuzhiyun 		ret = -ENOMEM;
100*4882a593Smuzhiyun 		goto err_remove_config_dt;
101*4882a593Smuzhiyun 	}
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	dwmac->dev = &pdev->dev;
104*4882a593Smuzhiyun 	dwmac->tx_clk = NULL;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	match = of_match_device(intel_eth_plat_match, &pdev->dev);
107*4882a593Smuzhiyun 	if (match && match->data) {
108*4882a593Smuzhiyun 		dwmac->data = (const struct intel_dwmac_data *)match->data;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 		if (dwmac->data->fix_mac_speed)
111*4882a593Smuzhiyun 			plat_dat->fix_mac_speed = dwmac->data->fix_mac_speed;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 		/* Enable TX clock */
114*4882a593Smuzhiyun 		if (dwmac->data->tx_clk_en) {
115*4882a593Smuzhiyun 			dwmac->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
116*4882a593Smuzhiyun 			if (IS_ERR(dwmac->tx_clk)) {
117*4882a593Smuzhiyun 				ret = PTR_ERR(dwmac->tx_clk);
118*4882a593Smuzhiyun 				goto err_remove_config_dt;
119*4882a593Smuzhiyun 			}
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 			clk_prepare_enable(dwmac->tx_clk);
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 			/* Check and configure TX clock rate */
124*4882a593Smuzhiyun 			rate = clk_get_rate(dwmac->tx_clk);
125*4882a593Smuzhiyun 			if (dwmac->data->tx_clk_rate &&
126*4882a593Smuzhiyun 			    rate != dwmac->data->tx_clk_rate) {
127*4882a593Smuzhiyun 				rate = dwmac->data->tx_clk_rate;
128*4882a593Smuzhiyun 				ret = clk_set_rate(dwmac->tx_clk, rate);
129*4882a593Smuzhiyun 				if (ret) {
130*4882a593Smuzhiyun 					dev_err(&pdev->dev,
131*4882a593Smuzhiyun 						"Failed to set tx_clk\n");
132*4882a593Smuzhiyun 					goto err_remove_config_dt;
133*4882a593Smuzhiyun 				}
134*4882a593Smuzhiyun 			}
135*4882a593Smuzhiyun 		}
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 		/* Check and configure PTP ref clock rate */
138*4882a593Smuzhiyun 		rate = clk_get_rate(plat_dat->clk_ptp_ref);
139*4882a593Smuzhiyun 		if (dwmac->data->ptp_ref_clk_rate &&
140*4882a593Smuzhiyun 		    rate != dwmac->data->ptp_ref_clk_rate) {
141*4882a593Smuzhiyun 			rate = dwmac->data->ptp_ref_clk_rate;
142*4882a593Smuzhiyun 			ret = clk_set_rate(plat_dat->clk_ptp_ref, rate);
143*4882a593Smuzhiyun 			if (ret) {
144*4882a593Smuzhiyun 				dev_err(&pdev->dev,
145*4882a593Smuzhiyun 					"Failed to set clk_ptp_ref\n");
146*4882a593Smuzhiyun 				goto err_remove_config_dt;
147*4882a593Smuzhiyun 			}
148*4882a593Smuzhiyun 		}
149*4882a593Smuzhiyun 	}
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	plat_dat->bsp_priv = dwmac;
152*4882a593Smuzhiyun 	plat_dat->eee_usecs_rate = plat_dat->clk_ptp_rate;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	if (plat_dat->eee_usecs_rate > 0) {
155*4882a593Smuzhiyun 		u32 tx_lpi_usec;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 		tx_lpi_usec = (plat_dat->eee_usecs_rate / 1000000) - 1;
158*4882a593Smuzhiyun 		writel(tx_lpi_usec, stmmac_res.addr + GMAC_1US_TIC_COUNTER);
159*4882a593Smuzhiyun 	}
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
162*4882a593Smuzhiyun 	if (ret) {
163*4882a593Smuzhiyun 		clk_disable_unprepare(dwmac->tx_clk);
164*4882a593Smuzhiyun 		goto err_remove_config_dt;
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	return 0;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun err_remove_config_dt:
170*4882a593Smuzhiyun 	stmmac_remove_config_dt(pdev, plat_dat);
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	return ret;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
intel_eth_plat_remove(struct platform_device * pdev)175*4882a593Smuzhiyun static int intel_eth_plat_remove(struct platform_device *pdev)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	struct intel_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev);
178*4882a593Smuzhiyun 	int ret;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	ret = stmmac_pltfr_remove(pdev);
181*4882a593Smuzhiyun 	clk_disable_unprepare(dwmac->tx_clk);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	return ret;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun static struct platform_driver intel_eth_plat_driver = {
187*4882a593Smuzhiyun 	.probe  = intel_eth_plat_probe,
188*4882a593Smuzhiyun 	.remove = intel_eth_plat_remove,
189*4882a593Smuzhiyun 	.driver = {
190*4882a593Smuzhiyun 		.name		= "intel-eth-plat",
191*4882a593Smuzhiyun 		.pm		= &stmmac_pltfr_pm_ops,
192*4882a593Smuzhiyun 		.of_match_table = intel_eth_plat_match,
193*4882a593Smuzhiyun 	},
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun module_platform_driver(intel_eth_plat_driver);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
198*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel DWMAC platform driver");
199