1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * smc911x.c
4*4882a593Smuzhiyun * This is a driver for SMSC's LAN911{5,6,7,8} single-chip Ethernet devices.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2005 Sensoria Corp
7*4882a593Smuzhiyun * Derived from the unified SMC91x driver by Nicolas Pitre
8*4882a593Smuzhiyun * and the smsc911x.c reference driver by SMSC
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Arguments:
11*4882a593Smuzhiyun * watchdog = TX watchdog timeout
12*4882a593Smuzhiyun * tx_fifo_kb = Size of TX FIFO in KB
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * History:
15*4882a593Smuzhiyun * 04/16/05 Dustin McIntire Initial version
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun static const char version[] =
18*4882a593Smuzhiyun "smc911x.c: v1.0 04-16-2005 by Dustin McIntire <dustin@sensoria.com>\n";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Debugging options */
21*4882a593Smuzhiyun #define ENABLE_SMC_DEBUG_RX 0
22*4882a593Smuzhiyun #define ENABLE_SMC_DEBUG_TX 0
23*4882a593Smuzhiyun #define ENABLE_SMC_DEBUG_DMA 0
24*4882a593Smuzhiyun #define ENABLE_SMC_DEBUG_PKTS 0
25*4882a593Smuzhiyun #define ENABLE_SMC_DEBUG_MISC 0
26*4882a593Smuzhiyun #define ENABLE_SMC_DEBUG_FUNC 0
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define SMC_DEBUG_RX ((ENABLE_SMC_DEBUG_RX ? 1 : 0) << 0)
29*4882a593Smuzhiyun #define SMC_DEBUG_TX ((ENABLE_SMC_DEBUG_TX ? 1 : 0) << 1)
30*4882a593Smuzhiyun #define SMC_DEBUG_DMA ((ENABLE_SMC_DEBUG_DMA ? 1 : 0) << 2)
31*4882a593Smuzhiyun #define SMC_DEBUG_PKTS ((ENABLE_SMC_DEBUG_PKTS ? 1 : 0) << 3)
32*4882a593Smuzhiyun #define SMC_DEBUG_MISC ((ENABLE_SMC_DEBUG_MISC ? 1 : 0) << 4)
33*4882a593Smuzhiyun #define SMC_DEBUG_FUNC ((ENABLE_SMC_DEBUG_FUNC ? 1 : 0) << 5)
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #ifndef SMC_DEBUG
36*4882a593Smuzhiyun #define SMC_DEBUG ( SMC_DEBUG_RX | \
37*4882a593Smuzhiyun SMC_DEBUG_TX | \
38*4882a593Smuzhiyun SMC_DEBUG_DMA | \
39*4882a593Smuzhiyun SMC_DEBUG_PKTS | \
40*4882a593Smuzhiyun SMC_DEBUG_MISC | \
41*4882a593Smuzhiyun SMC_DEBUG_FUNC \
42*4882a593Smuzhiyun )
43*4882a593Smuzhiyun #endif
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #include <linux/module.h>
46*4882a593Smuzhiyun #include <linux/kernel.h>
47*4882a593Smuzhiyun #include <linux/sched.h>
48*4882a593Smuzhiyun #include <linux/delay.h>
49*4882a593Smuzhiyun #include <linux/interrupt.h>
50*4882a593Smuzhiyun #include <linux/errno.h>
51*4882a593Smuzhiyun #include <linux/ioport.h>
52*4882a593Smuzhiyun #include <linux/crc32.h>
53*4882a593Smuzhiyun #include <linux/device.h>
54*4882a593Smuzhiyun #include <linux/platform_device.h>
55*4882a593Smuzhiyun #include <linux/spinlock.h>
56*4882a593Smuzhiyun #include <linux/ethtool.h>
57*4882a593Smuzhiyun #include <linux/mii.h>
58*4882a593Smuzhiyun #include <linux/workqueue.h>
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #include <linux/netdevice.h>
61*4882a593Smuzhiyun #include <linux/etherdevice.h>
62*4882a593Smuzhiyun #include <linux/skbuff.h>
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #include <linux/dmaengine.h>
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #include <asm/io.h>
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #include "smc911x.h"
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * Transmit timeout, default 5 seconds.
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun static int watchdog = 5000;
74*4882a593Smuzhiyun module_param(watchdog, int, 0400);
75*4882a593Smuzhiyun MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static int tx_fifo_kb=8;
78*4882a593Smuzhiyun module_param(tx_fifo_kb, int, 0400);
79*4882a593Smuzhiyun MODULE_PARM_DESC(tx_fifo_kb,"transmit FIFO size in KB (1<x<15)(default=8)");
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun MODULE_LICENSE("GPL");
82*4882a593Smuzhiyun MODULE_ALIAS("platform:smc911x");
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun * The internal workings of the driver. If you are changing anything
86*4882a593Smuzhiyun * here with the SMC stuff, you should have the datasheet and know
87*4882a593Smuzhiyun * what you are doing.
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun #define CARDNAME "smc911x"
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun * Use power-down feature of the chip
93*4882a593Smuzhiyun */
94*4882a593Smuzhiyun #define POWER_DOWN 1
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #if SMC_DEBUG > 0
97*4882a593Smuzhiyun #define DBG(n, dev, args...) \
98*4882a593Smuzhiyun do { \
99*4882a593Smuzhiyun if (SMC_DEBUG & (n)) \
100*4882a593Smuzhiyun netdev_dbg(dev, args); \
101*4882a593Smuzhiyun } while (0)
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define PRINTK(dev, args...) netdev_info(dev, args)
104*4882a593Smuzhiyun #else
105*4882a593Smuzhiyun #define DBG(n, dev, args...) do { } while (0)
106*4882a593Smuzhiyun #define PRINTK(dev, args...) netdev_dbg(dev, args)
107*4882a593Smuzhiyun #endif
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #if SMC_DEBUG_PKTS > 0
PRINT_PKT(u_char * buf,int length)110*4882a593Smuzhiyun static void PRINT_PKT(u_char *buf, int length)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun int i;
113*4882a593Smuzhiyun int remainder;
114*4882a593Smuzhiyun int lines;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun lines = length / 16;
117*4882a593Smuzhiyun remainder = length % 16;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun for (i = 0; i < lines ; i ++) {
120*4882a593Smuzhiyun int cur;
121*4882a593Smuzhiyun printk(KERN_DEBUG);
122*4882a593Smuzhiyun for (cur = 0; cur < 8; cur++) {
123*4882a593Smuzhiyun u_char a, b;
124*4882a593Smuzhiyun a = *buf++;
125*4882a593Smuzhiyun b = *buf++;
126*4882a593Smuzhiyun pr_cont("%02x%02x ", a, b);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun pr_cont("\n");
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun printk(KERN_DEBUG);
131*4882a593Smuzhiyun for (i = 0; i < remainder/2 ; i++) {
132*4882a593Smuzhiyun u_char a, b;
133*4882a593Smuzhiyun a = *buf++;
134*4882a593Smuzhiyun b = *buf++;
135*4882a593Smuzhiyun pr_cont("%02x%02x ", a, b);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun pr_cont("\n");
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun #else
140*4882a593Smuzhiyun #define PRINT_PKT(x...) do { } while (0)
141*4882a593Smuzhiyun #endif
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /* this enables an interrupt in the interrupt mask register */
145*4882a593Smuzhiyun #define SMC_ENABLE_INT(lp, x) do { \
146*4882a593Smuzhiyun unsigned int __mask; \
147*4882a593Smuzhiyun __mask = SMC_GET_INT_EN((lp)); \
148*4882a593Smuzhiyun __mask |= (x); \
149*4882a593Smuzhiyun SMC_SET_INT_EN((lp), __mask); \
150*4882a593Smuzhiyun } while (0)
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /* this disables an interrupt from the interrupt mask register */
153*4882a593Smuzhiyun #define SMC_DISABLE_INT(lp, x) do { \
154*4882a593Smuzhiyun unsigned int __mask; \
155*4882a593Smuzhiyun __mask = SMC_GET_INT_EN((lp)); \
156*4882a593Smuzhiyun __mask &= ~(x); \
157*4882a593Smuzhiyun SMC_SET_INT_EN((lp), __mask); \
158*4882a593Smuzhiyun } while (0)
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /*
161*4882a593Smuzhiyun * this does a soft reset on the device
162*4882a593Smuzhiyun */
smc911x_reset(struct net_device * dev)163*4882a593Smuzhiyun static void smc911x_reset(struct net_device *dev)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
166*4882a593Smuzhiyun unsigned int reg, timeout=0, resets=1, irq_cfg;
167*4882a593Smuzhiyun unsigned long flags;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* Take out of PM setting first */
172*4882a593Smuzhiyun if ((SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_) == 0) {
173*4882a593Smuzhiyun /* Write to the bytetest will take out of powerdown */
174*4882a593Smuzhiyun SMC_SET_BYTE_TEST(lp, 0);
175*4882a593Smuzhiyun timeout=10;
176*4882a593Smuzhiyun do {
177*4882a593Smuzhiyun udelay(10);
178*4882a593Smuzhiyun reg = SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_;
179*4882a593Smuzhiyun } while (--timeout && !reg);
180*4882a593Smuzhiyun if (timeout == 0) {
181*4882a593Smuzhiyun PRINTK(dev, "smc911x_reset timeout waiting for PM restore\n");
182*4882a593Smuzhiyun return;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* Disable all interrupts */
187*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
188*4882a593Smuzhiyun SMC_SET_INT_EN(lp, 0);
189*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun while (resets--) {
192*4882a593Smuzhiyun SMC_SET_HW_CFG(lp, HW_CFG_SRST_);
193*4882a593Smuzhiyun timeout=10;
194*4882a593Smuzhiyun do {
195*4882a593Smuzhiyun udelay(10);
196*4882a593Smuzhiyun reg = SMC_GET_HW_CFG(lp);
197*4882a593Smuzhiyun /* If chip indicates reset timeout then try again */
198*4882a593Smuzhiyun if (reg & HW_CFG_SRST_TO_) {
199*4882a593Smuzhiyun PRINTK(dev, "chip reset timeout, retrying...\n");
200*4882a593Smuzhiyun resets++;
201*4882a593Smuzhiyun break;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun } while (--timeout && (reg & HW_CFG_SRST_));
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun if (timeout == 0) {
206*4882a593Smuzhiyun PRINTK(dev, "smc911x_reset timeout waiting for reset\n");
207*4882a593Smuzhiyun return;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /* make sure EEPROM has finished loading before setting GPIO_CFG */
211*4882a593Smuzhiyun timeout=1000;
212*4882a593Smuzhiyun while (--timeout && (SMC_GET_E2P_CMD(lp) & E2P_CMD_EPC_BUSY_))
213*4882a593Smuzhiyun udelay(10);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (timeout == 0){
216*4882a593Smuzhiyun PRINTK(dev, "smc911x_reset timeout waiting for EEPROM busy\n");
217*4882a593Smuzhiyun return;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /* Initialize interrupts */
221*4882a593Smuzhiyun SMC_SET_INT_EN(lp, 0);
222*4882a593Smuzhiyun SMC_ACK_INT(lp, -1);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* Reset the FIFO level and flow control settings */
225*4882a593Smuzhiyun SMC_SET_HW_CFG(lp, (lp->tx_fifo_kb & 0xF) << 16);
226*4882a593Smuzhiyun //TODO: Figure out what appropriate pause time is
227*4882a593Smuzhiyun SMC_SET_FLOW(lp, FLOW_FCPT_ | FLOW_FCEN_);
228*4882a593Smuzhiyun SMC_SET_AFC_CFG(lp, lp->afc_cfg);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /* Set to LED outputs */
232*4882a593Smuzhiyun SMC_SET_GPIO_CFG(lp, 0x70070000);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /*
235*4882a593Smuzhiyun * Deassert IRQ for 1*10us for edge type interrupts
236*4882a593Smuzhiyun * and drive IRQ pin push-pull
237*4882a593Smuzhiyun */
238*4882a593Smuzhiyun irq_cfg = (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_;
239*4882a593Smuzhiyun #ifdef SMC_DYNAMIC_BUS_CONFIG
240*4882a593Smuzhiyun if (lp->cfg.irq_polarity)
241*4882a593Smuzhiyun irq_cfg |= INT_CFG_IRQ_POL_;
242*4882a593Smuzhiyun #endif
243*4882a593Smuzhiyun SMC_SET_IRQ_CFG(lp, irq_cfg);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /* clear anything saved */
246*4882a593Smuzhiyun if (lp->pending_tx_skb != NULL) {
247*4882a593Smuzhiyun dev_kfree_skb (lp->pending_tx_skb);
248*4882a593Smuzhiyun lp->pending_tx_skb = NULL;
249*4882a593Smuzhiyun dev->stats.tx_errors++;
250*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /*
255*4882a593Smuzhiyun * Enable Interrupts, Receive, and Transmit
256*4882a593Smuzhiyun */
smc911x_enable(struct net_device * dev)257*4882a593Smuzhiyun static void smc911x_enable(struct net_device *dev)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
260*4882a593Smuzhiyun unsigned mask, cfg, cr;
261*4882a593Smuzhiyun unsigned long flags;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun SMC_SET_MAC_ADDR(lp, dev->dev_addr);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* Enable TX */
270*4882a593Smuzhiyun cfg = SMC_GET_HW_CFG(lp);
271*4882a593Smuzhiyun cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF;
272*4882a593Smuzhiyun cfg |= HW_CFG_SF_;
273*4882a593Smuzhiyun SMC_SET_HW_CFG(lp, cfg);
274*4882a593Smuzhiyun SMC_SET_FIFO_TDA(lp, 0xFF);
275*4882a593Smuzhiyun /* Update TX stats on every 64 packets received or every 1 sec */
276*4882a593Smuzhiyun SMC_SET_FIFO_TSL(lp, 64);
277*4882a593Smuzhiyun SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun SMC_GET_MAC_CR(lp, cr);
280*4882a593Smuzhiyun cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_;
281*4882a593Smuzhiyun SMC_SET_MAC_CR(lp, cr);
282*4882a593Smuzhiyun SMC_SET_TX_CFG(lp, TX_CFG_TX_ON_);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /* Add 2 byte padding to start of packets */
285*4882a593Smuzhiyun SMC_SET_RX_CFG(lp, (2<<8) & RX_CFG_RXDOFF_);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /* Turn on receiver and enable RX */
288*4882a593Smuzhiyun if (cr & MAC_CR_RXEN_)
289*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "Receiver already enabled\n");
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun SMC_SET_MAC_CR(lp, cr | MAC_CR_RXEN_);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /* Interrupt on every received packet */
294*4882a593Smuzhiyun SMC_SET_FIFO_RSA(lp, 0x01);
295*4882a593Smuzhiyun SMC_SET_FIFO_RSL(lp, 0x00);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /* now, enable interrupts */
298*4882a593Smuzhiyun mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ |
299*4882a593Smuzhiyun INT_EN_GPT_INT_EN_ | INT_EN_RXDFH_INT_EN_ | INT_EN_RXE_EN_ |
300*4882a593Smuzhiyun INT_EN_PHY_INT_EN_;
301*4882a593Smuzhiyun if (IS_REV_A(lp->revision))
302*4882a593Smuzhiyun mask|=INT_EN_RDFL_EN_;
303*4882a593Smuzhiyun else {
304*4882a593Smuzhiyun mask|=INT_EN_RDFO_EN_;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun SMC_ENABLE_INT(lp, mask);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /*
312*4882a593Smuzhiyun * this puts the device in an inactive state
313*4882a593Smuzhiyun */
smc911x_shutdown(struct net_device * dev)314*4882a593Smuzhiyun static void smc911x_shutdown(struct net_device *dev)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
317*4882a593Smuzhiyun unsigned cr;
318*4882a593Smuzhiyun unsigned long flags;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "%s: --> %s\n", CARDNAME, __func__);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* Disable IRQ's */
323*4882a593Smuzhiyun SMC_SET_INT_EN(lp, 0);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* Turn of Rx and TX */
326*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
327*4882a593Smuzhiyun SMC_GET_MAC_CR(lp, cr);
328*4882a593Smuzhiyun cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
329*4882a593Smuzhiyun SMC_SET_MAC_CR(lp, cr);
330*4882a593Smuzhiyun SMC_SET_TX_CFG(lp, TX_CFG_STOP_TX_);
331*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
smc911x_drop_pkt(struct net_device * dev)334*4882a593Smuzhiyun static inline void smc911x_drop_pkt(struct net_device *dev)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
337*4882a593Smuzhiyun unsigned int fifo_count, timeout, reg;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, dev, "%s: --> %s\n",
340*4882a593Smuzhiyun CARDNAME, __func__);
341*4882a593Smuzhiyun fifo_count = SMC_GET_RX_FIFO_INF(lp) & 0xFFFF;
342*4882a593Smuzhiyun if (fifo_count <= 4) {
343*4882a593Smuzhiyun /* Manually dump the packet data */
344*4882a593Smuzhiyun while (fifo_count--)
345*4882a593Smuzhiyun SMC_GET_RX_FIFO(lp);
346*4882a593Smuzhiyun } else {
347*4882a593Smuzhiyun /* Fast forward through the bad packet */
348*4882a593Smuzhiyun SMC_SET_RX_DP_CTRL(lp, RX_DP_CTRL_FFWD_BUSY_);
349*4882a593Smuzhiyun timeout=50;
350*4882a593Smuzhiyun do {
351*4882a593Smuzhiyun udelay(10);
352*4882a593Smuzhiyun reg = SMC_GET_RX_DP_CTRL(lp) & RX_DP_CTRL_FFWD_BUSY_;
353*4882a593Smuzhiyun } while (--timeout && reg);
354*4882a593Smuzhiyun if (timeout == 0) {
355*4882a593Smuzhiyun PRINTK(dev, "timeout waiting for RX fast forward\n");
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun /*
361*4882a593Smuzhiyun * This is the procedure to handle the receipt of a packet.
362*4882a593Smuzhiyun * It should be called after checking for packet presence in
363*4882a593Smuzhiyun * the RX status FIFO. It must be called with the spin lock
364*4882a593Smuzhiyun * already held.
365*4882a593Smuzhiyun */
smc911x_rcv(struct net_device * dev)366*4882a593Smuzhiyun static inline void smc911x_rcv(struct net_device *dev)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
369*4882a593Smuzhiyun unsigned int pkt_len, status;
370*4882a593Smuzhiyun struct sk_buff *skb;
371*4882a593Smuzhiyun unsigned char *data;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, dev, "--> %s\n",
374*4882a593Smuzhiyun __func__);
375*4882a593Smuzhiyun status = SMC_GET_RX_STS_FIFO(lp);
376*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "Rx pkt len %d status 0x%08x\n",
377*4882a593Smuzhiyun (status & 0x3fff0000) >> 16, status & 0xc000ffff);
378*4882a593Smuzhiyun pkt_len = (status & RX_STS_PKT_LEN_) >> 16;
379*4882a593Smuzhiyun if (status & RX_STS_ES_) {
380*4882a593Smuzhiyun /* Deal with a bad packet */
381*4882a593Smuzhiyun dev->stats.rx_errors++;
382*4882a593Smuzhiyun if (status & RX_STS_CRC_ERR_)
383*4882a593Smuzhiyun dev->stats.rx_crc_errors++;
384*4882a593Smuzhiyun else {
385*4882a593Smuzhiyun if (status & RX_STS_LEN_ERR_)
386*4882a593Smuzhiyun dev->stats.rx_length_errors++;
387*4882a593Smuzhiyun if (status & RX_STS_MCAST_)
388*4882a593Smuzhiyun dev->stats.multicast++;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun /* Remove the bad packet data from the RX FIFO */
391*4882a593Smuzhiyun smc911x_drop_pkt(dev);
392*4882a593Smuzhiyun } else {
393*4882a593Smuzhiyun /* Receive a valid packet */
394*4882a593Smuzhiyun /* Alloc a buffer with extra room for DMA alignment */
395*4882a593Smuzhiyun skb = netdev_alloc_skb(dev, pkt_len+32);
396*4882a593Smuzhiyun if (unlikely(skb == NULL)) {
397*4882a593Smuzhiyun PRINTK(dev, "Low memory, rcvd packet dropped.\n");
398*4882a593Smuzhiyun dev->stats.rx_dropped++;
399*4882a593Smuzhiyun smc911x_drop_pkt(dev);
400*4882a593Smuzhiyun return;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun /* Align IP header to 32 bits
403*4882a593Smuzhiyun * Note that the device is configured to add a 2
404*4882a593Smuzhiyun * byte padding to the packet start, so we really
405*4882a593Smuzhiyun * want to write to the orignal data pointer */
406*4882a593Smuzhiyun data = skb->data;
407*4882a593Smuzhiyun skb_reserve(skb, 2);
408*4882a593Smuzhiyun skb_put(skb,pkt_len-4);
409*4882a593Smuzhiyun #ifdef SMC_USE_DMA
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun unsigned int fifo;
412*4882a593Smuzhiyun /* Lower the FIFO threshold if possible */
413*4882a593Smuzhiyun fifo = SMC_GET_FIFO_INT(lp);
414*4882a593Smuzhiyun if (fifo & 0xFF) fifo--;
415*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "Setting RX stat FIFO threshold to %d\n",
416*4882a593Smuzhiyun fifo & 0xff);
417*4882a593Smuzhiyun SMC_SET_FIFO_INT(lp, fifo);
418*4882a593Smuzhiyun /* Setup RX DMA */
419*4882a593Smuzhiyun SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_));
420*4882a593Smuzhiyun lp->rxdma_active = 1;
421*4882a593Smuzhiyun lp->current_rx_skb = skb;
422*4882a593Smuzhiyun SMC_PULL_DATA(lp, data, (pkt_len+2+15) & ~15);
423*4882a593Smuzhiyun /* Packet processing deferred to DMA RX interrupt */
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun #else
426*4882a593Smuzhiyun SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_));
427*4882a593Smuzhiyun SMC_PULL_DATA(lp, data, pkt_len+2+3);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun DBG(SMC_DEBUG_PKTS, dev, "Received packet\n");
430*4882a593Smuzhiyun PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64);
431*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
432*4882a593Smuzhiyun netif_rx(skb);
433*4882a593Smuzhiyun dev->stats.rx_packets++;
434*4882a593Smuzhiyun dev->stats.rx_bytes += pkt_len-4;
435*4882a593Smuzhiyun #endif
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun /*
440*4882a593Smuzhiyun * This is called to actually send a packet to the chip.
441*4882a593Smuzhiyun */
smc911x_hardware_send_pkt(struct net_device * dev)442*4882a593Smuzhiyun static void smc911x_hardware_send_pkt(struct net_device *dev)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
445*4882a593Smuzhiyun struct sk_buff *skb;
446*4882a593Smuzhiyun unsigned int cmdA, cmdB, len;
447*4882a593Smuzhiyun unsigned char *buf;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, dev, "--> %s\n", __func__);
450*4882a593Smuzhiyun BUG_ON(lp->pending_tx_skb == NULL);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun skb = lp->pending_tx_skb;
453*4882a593Smuzhiyun lp->pending_tx_skb = NULL;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun /* cmdA {25:24] data alignment [20:16] start offset [10:0] buffer length */
456*4882a593Smuzhiyun /* cmdB {31:16] pkt tag [10:0] length */
457*4882a593Smuzhiyun #ifdef SMC_USE_DMA
458*4882a593Smuzhiyun /* 16 byte buffer alignment mode */
459*4882a593Smuzhiyun buf = (char*)((u32)(skb->data) & ~0xF);
460*4882a593Smuzhiyun len = (skb->len + 0xF + ((u32)skb->data & 0xF)) & ~0xF;
461*4882a593Smuzhiyun cmdA = (1<<24) | (((u32)skb->data & 0xF)<<16) |
462*4882a593Smuzhiyun TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
463*4882a593Smuzhiyun skb->len;
464*4882a593Smuzhiyun #else
465*4882a593Smuzhiyun buf = (char*)((u32)skb->data & ~0x3);
466*4882a593Smuzhiyun len = (skb->len + 3 + ((u32)skb->data & 3)) & ~0x3;
467*4882a593Smuzhiyun cmdA = (((u32)skb->data & 0x3) << 16) |
468*4882a593Smuzhiyun TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
469*4882a593Smuzhiyun skb->len;
470*4882a593Smuzhiyun #endif
471*4882a593Smuzhiyun /* tag is packet length so we can use this in stats update later */
472*4882a593Smuzhiyun cmdB = (skb->len << 16) | (skb->len & 0x7FF);
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun DBG(SMC_DEBUG_TX, dev, "TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n",
475*4882a593Smuzhiyun len, len, buf, cmdA, cmdB);
476*4882a593Smuzhiyun SMC_SET_TX_FIFO(lp, cmdA);
477*4882a593Smuzhiyun SMC_SET_TX_FIFO(lp, cmdB);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun DBG(SMC_DEBUG_PKTS, dev, "Transmitted packet\n");
480*4882a593Smuzhiyun PRINT_PKT(buf, len <= 64 ? len : 64);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun /* Send pkt via PIO or DMA */
483*4882a593Smuzhiyun #ifdef SMC_USE_DMA
484*4882a593Smuzhiyun lp->current_tx_skb = skb;
485*4882a593Smuzhiyun SMC_PUSH_DATA(lp, buf, len);
486*4882a593Smuzhiyun /* DMA complete IRQ will free buffer and set jiffies */
487*4882a593Smuzhiyun #else
488*4882a593Smuzhiyun SMC_PUSH_DATA(lp, buf, len);
489*4882a593Smuzhiyun netif_trans_update(dev);
490*4882a593Smuzhiyun dev_kfree_skb_irq(skb);
491*4882a593Smuzhiyun #endif
492*4882a593Smuzhiyun if (!lp->tx_throttle) {
493*4882a593Smuzhiyun netif_wake_queue(dev);
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun SMC_ENABLE_INT(lp, INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun /*
499*4882a593Smuzhiyun * Since I am not sure if I will have enough room in the chip's ram
500*4882a593Smuzhiyun * to store the packet, I call this routine which either sends it
501*4882a593Smuzhiyun * now, or set the card to generates an interrupt when ready
502*4882a593Smuzhiyun * for the packet.
503*4882a593Smuzhiyun */
504*4882a593Smuzhiyun static netdev_tx_t
smc911x_hard_start_xmit(struct sk_buff * skb,struct net_device * dev)505*4882a593Smuzhiyun smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
508*4882a593Smuzhiyun unsigned int free;
509*4882a593Smuzhiyun unsigned long flags;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, dev, "--> %s\n",
512*4882a593Smuzhiyun __func__);
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun BUG_ON(lp->pending_tx_skb != NULL);
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun free = SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TDFREE_;
519*4882a593Smuzhiyun DBG(SMC_DEBUG_TX, dev, "TX free space %d\n", free);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun /* Turn off the flow when running out of space in FIFO */
522*4882a593Smuzhiyun if (free <= SMC911X_TX_FIFO_LOW_THRESHOLD) {
523*4882a593Smuzhiyun DBG(SMC_DEBUG_TX, dev, "Disabling data flow due to low FIFO space (%d)\n",
524*4882a593Smuzhiyun free);
525*4882a593Smuzhiyun /* Reenable when at least 1 packet of size MTU present */
526*4882a593Smuzhiyun SMC_SET_FIFO_TDA(lp, (SMC911X_TX_FIFO_LOW_THRESHOLD)/64);
527*4882a593Smuzhiyun lp->tx_throttle = 1;
528*4882a593Smuzhiyun netif_stop_queue(dev);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun /* Drop packets when we run out of space in TX FIFO
532*4882a593Smuzhiyun * Account for overhead required for:
533*4882a593Smuzhiyun *
534*4882a593Smuzhiyun * Tx command words 8 bytes
535*4882a593Smuzhiyun * Start offset 15 bytes
536*4882a593Smuzhiyun * End padding 15 bytes
537*4882a593Smuzhiyun */
538*4882a593Smuzhiyun if (unlikely(free < (skb->len + 8 + 15 + 15))) {
539*4882a593Smuzhiyun netdev_warn(dev, "No Tx free space %d < %d\n",
540*4882a593Smuzhiyun free, skb->len);
541*4882a593Smuzhiyun lp->pending_tx_skb = NULL;
542*4882a593Smuzhiyun dev->stats.tx_errors++;
543*4882a593Smuzhiyun dev->stats.tx_dropped++;
544*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
545*4882a593Smuzhiyun dev_kfree_skb_any(skb);
546*4882a593Smuzhiyun return NETDEV_TX_OK;
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun #ifdef SMC_USE_DMA
550*4882a593Smuzhiyun {
551*4882a593Smuzhiyun /* If the DMA is already running then defer this packet Tx until
552*4882a593Smuzhiyun * the DMA IRQ starts it
553*4882a593Smuzhiyun */
554*4882a593Smuzhiyun if (lp->txdma_active) {
555*4882a593Smuzhiyun DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev, "Tx DMA running, deferring packet\n");
556*4882a593Smuzhiyun lp->pending_tx_skb = skb;
557*4882a593Smuzhiyun netif_stop_queue(dev);
558*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
559*4882a593Smuzhiyun return NETDEV_TX_OK;
560*4882a593Smuzhiyun } else {
561*4882a593Smuzhiyun DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev, "Activating Tx DMA\n");
562*4882a593Smuzhiyun lp->txdma_active = 1;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun #endif
566*4882a593Smuzhiyun lp->pending_tx_skb = skb;
567*4882a593Smuzhiyun smc911x_hardware_send_pkt(dev);
568*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun return NETDEV_TX_OK;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun /*
574*4882a593Smuzhiyun * This handles a TX status interrupt, which is only called when:
575*4882a593Smuzhiyun * - a TX error occurred, or
576*4882a593Smuzhiyun * - TX of a packet completed.
577*4882a593Smuzhiyun */
smc911x_tx(struct net_device * dev)578*4882a593Smuzhiyun static void smc911x_tx(struct net_device *dev)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
581*4882a593Smuzhiyun unsigned int tx_status;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, dev, "--> %s\n",
584*4882a593Smuzhiyun __func__);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun /* Collect the TX status */
587*4882a593Smuzhiyun while (((SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16) != 0) {
588*4882a593Smuzhiyun DBG(SMC_DEBUG_TX, dev, "Tx stat FIFO used 0x%04x\n",
589*4882a593Smuzhiyun (SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16);
590*4882a593Smuzhiyun tx_status = SMC_GET_TX_STS_FIFO(lp);
591*4882a593Smuzhiyun dev->stats.tx_packets++;
592*4882a593Smuzhiyun dev->stats.tx_bytes+=tx_status>>16;
593*4882a593Smuzhiyun DBG(SMC_DEBUG_TX, dev, "Tx FIFO tag 0x%04x status 0x%04x\n",
594*4882a593Smuzhiyun (tx_status & 0xffff0000) >> 16,
595*4882a593Smuzhiyun tx_status & 0x0000ffff);
596*4882a593Smuzhiyun /* count Tx errors, but ignore lost carrier errors when in
597*4882a593Smuzhiyun * full-duplex mode */
598*4882a593Smuzhiyun if ((tx_status & TX_STS_ES_) && !(lp->ctl_rfduplx &&
599*4882a593Smuzhiyun !(tx_status & 0x00000306))) {
600*4882a593Smuzhiyun dev->stats.tx_errors++;
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun if (tx_status & TX_STS_MANY_COLL_) {
603*4882a593Smuzhiyun dev->stats.collisions+=16;
604*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
605*4882a593Smuzhiyun } else {
606*4882a593Smuzhiyun dev->stats.collisions+=(tx_status & TX_STS_COLL_CNT_) >> 3;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun /* carrier error only has meaning for half-duplex communication */
609*4882a593Smuzhiyun if ((tx_status & (TX_STS_LOC_ | TX_STS_NO_CARR_)) &&
610*4882a593Smuzhiyun !lp->ctl_rfduplx) {
611*4882a593Smuzhiyun dev->stats.tx_carrier_errors++;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun if (tx_status & TX_STS_LATE_COLL_) {
614*4882a593Smuzhiyun dev->stats.collisions++;
615*4882a593Smuzhiyun dev->stats.tx_aborted_errors++;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
622*4882a593Smuzhiyun /*
623*4882a593Smuzhiyun * Reads a register from the MII Management serial interface
624*4882a593Smuzhiyun */
625*4882a593Smuzhiyun
smc911x_phy_read(struct net_device * dev,int phyaddr,int phyreg)626*4882a593Smuzhiyun static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
629*4882a593Smuzhiyun unsigned int phydata;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun SMC_GET_MII(lp, phyreg, phyaddr, phydata);
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n",
634*4882a593Smuzhiyun __func__, phyaddr, phyreg, phydata);
635*4882a593Smuzhiyun return phydata;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun /*
640*4882a593Smuzhiyun * Writes a register to the MII Management serial interface
641*4882a593Smuzhiyun */
smc911x_phy_write(struct net_device * dev,int phyaddr,int phyreg,int phydata)642*4882a593Smuzhiyun static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
643*4882a593Smuzhiyun int phydata)
644*4882a593Smuzhiyun {
645*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
648*4882a593Smuzhiyun __func__, phyaddr, phyreg, phydata);
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun SMC_SET_MII(lp, phyreg, phyaddr, phydata);
651*4882a593Smuzhiyun }
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun /*
654*4882a593Smuzhiyun * Finds and reports the PHY address (115 and 117 have external
655*4882a593Smuzhiyun * PHY interface 118 has internal only
656*4882a593Smuzhiyun */
smc911x_phy_detect(struct net_device * dev)657*4882a593Smuzhiyun static void smc911x_phy_detect(struct net_device *dev)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
660*4882a593Smuzhiyun int phyaddr;
661*4882a593Smuzhiyun unsigned int cfg, id1, id2;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun lp->phy_type = 0;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun /*
668*4882a593Smuzhiyun * Scan all 32 PHY addresses if necessary, starting at
669*4882a593Smuzhiyun * PHY#1 to PHY#31, and then PHY#0 last.
670*4882a593Smuzhiyun */
671*4882a593Smuzhiyun switch(lp->version) {
672*4882a593Smuzhiyun case CHIP_9115:
673*4882a593Smuzhiyun case CHIP_9117:
674*4882a593Smuzhiyun case CHIP_9215:
675*4882a593Smuzhiyun case CHIP_9217:
676*4882a593Smuzhiyun cfg = SMC_GET_HW_CFG(lp);
677*4882a593Smuzhiyun if (cfg & HW_CFG_EXT_PHY_DET_) {
678*4882a593Smuzhiyun cfg &= ~HW_CFG_PHY_CLK_SEL_;
679*4882a593Smuzhiyun cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
680*4882a593Smuzhiyun SMC_SET_HW_CFG(lp, cfg);
681*4882a593Smuzhiyun udelay(10); /* Wait for clocks to stop */
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun cfg |= HW_CFG_EXT_PHY_EN_;
684*4882a593Smuzhiyun SMC_SET_HW_CFG(lp, cfg);
685*4882a593Smuzhiyun udelay(10); /* Wait for clocks to stop */
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun cfg &= ~HW_CFG_PHY_CLK_SEL_;
688*4882a593Smuzhiyun cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
689*4882a593Smuzhiyun SMC_SET_HW_CFG(lp, cfg);
690*4882a593Smuzhiyun udelay(10); /* Wait for clocks to stop */
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun cfg |= HW_CFG_SMI_SEL_;
693*4882a593Smuzhiyun SMC_SET_HW_CFG(lp, cfg);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun for (phyaddr = 1; phyaddr < 32; ++phyaddr) {
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun /* Read the PHY identifiers */
698*4882a593Smuzhiyun SMC_GET_PHY_ID1(lp, phyaddr & 31, id1);
699*4882a593Smuzhiyun SMC_GET_PHY_ID2(lp, phyaddr & 31, id2);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun /* Make sure it is a valid identifier */
702*4882a593Smuzhiyun if (id1 != 0x0000 && id1 != 0xffff &&
703*4882a593Smuzhiyun id1 != 0x8000 && id2 != 0x0000 &&
704*4882a593Smuzhiyun id2 != 0xffff && id2 != 0x8000) {
705*4882a593Smuzhiyun /* Save the PHY's address */
706*4882a593Smuzhiyun lp->mii.phy_id = phyaddr & 31;
707*4882a593Smuzhiyun lp->phy_type = id1 << 16 | id2;
708*4882a593Smuzhiyun break;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun if (phyaddr < 32)
712*4882a593Smuzhiyun /* Found an external PHY */
713*4882a593Smuzhiyun break;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun fallthrough;
716*4882a593Smuzhiyun default:
717*4882a593Smuzhiyun /* Internal media only */
718*4882a593Smuzhiyun SMC_GET_PHY_ID1(lp, 1, id1);
719*4882a593Smuzhiyun SMC_GET_PHY_ID2(lp, 1, id2);
720*4882a593Smuzhiyun /* Save the PHY's address */
721*4882a593Smuzhiyun lp->mii.phy_id = 1;
722*4882a593Smuzhiyun lp->phy_type = id1 << 16 | id2;
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "phy_id1=0x%x, phy_id2=0x%x phyaddr=0x%x\n",
726*4882a593Smuzhiyun id1, id2, lp->mii.phy_id);
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun /*
730*4882a593Smuzhiyun * Sets the PHY to a configuration as determined by the user.
731*4882a593Smuzhiyun * Called with spin_lock held.
732*4882a593Smuzhiyun */
smc911x_phy_fixed(struct net_device * dev)733*4882a593Smuzhiyun static int smc911x_phy_fixed(struct net_device *dev)
734*4882a593Smuzhiyun {
735*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
736*4882a593Smuzhiyun int phyaddr = lp->mii.phy_id;
737*4882a593Smuzhiyun int bmcr;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun /* Enter Link Disable state */
742*4882a593Smuzhiyun SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
743*4882a593Smuzhiyun bmcr |= BMCR_PDOWN;
744*4882a593Smuzhiyun SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun /*
747*4882a593Smuzhiyun * Set our fixed capabilities
748*4882a593Smuzhiyun * Disable auto-negotiation
749*4882a593Smuzhiyun */
750*4882a593Smuzhiyun bmcr &= ~BMCR_ANENABLE;
751*4882a593Smuzhiyun if (lp->ctl_rfduplx)
752*4882a593Smuzhiyun bmcr |= BMCR_FULLDPLX;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun if (lp->ctl_rspeed == 100)
755*4882a593Smuzhiyun bmcr |= BMCR_SPEED100;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun /* Write our capabilities to the phy control register */
758*4882a593Smuzhiyun SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun /* Re-Configure the Receive/Phy Control register */
761*4882a593Smuzhiyun bmcr &= ~BMCR_PDOWN;
762*4882a593Smuzhiyun SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun return 1;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun /**
768*4882a593Smuzhiyun * smc911x_phy_reset - reset the phy
769*4882a593Smuzhiyun * @dev: net device
770*4882a593Smuzhiyun * @phy: phy address
771*4882a593Smuzhiyun *
772*4882a593Smuzhiyun * Issue a software reset for the specified PHY and
773*4882a593Smuzhiyun * wait up to 100ms for the reset to complete. We should
774*4882a593Smuzhiyun * not access the PHY for 50ms after issuing the reset.
775*4882a593Smuzhiyun *
776*4882a593Smuzhiyun * The time to wait appears to be dependent on the PHY.
777*4882a593Smuzhiyun *
778*4882a593Smuzhiyun */
smc911x_phy_reset(struct net_device * dev,int phy)779*4882a593Smuzhiyun static int smc911x_phy_reset(struct net_device *dev, int phy)
780*4882a593Smuzhiyun {
781*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
782*4882a593Smuzhiyun int timeout;
783*4882a593Smuzhiyun unsigned long flags;
784*4882a593Smuzhiyun unsigned int reg;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s()\n", __func__);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
789*4882a593Smuzhiyun reg = SMC_GET_PMT_CTRL(lp);
790*4882a593Smuzhiyun reg &= ~0xfffff030;
791*4882a593Smuzhiyun reg |= PMT_CTRL_PHY_RST_;
792*4882a593Smuzhiyun SMC_SET_PMT_CTRL(lp, reg);
793*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
794*4882a593Smuzhiyun for (timeout = 2; timeout; timeout--) {
795*4882a593Smuzhiyun msleep(50);
796*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
797*4882a593Smuzhiyun reg = SMC_GET_PMT_CTRL(lp);
798*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
799*4882a593Smuzhiyun if (!(reg & PMT_CTRL_PHY_RST_)) {
800*4882a593Smuzhiyun /* extra delay required because the phy may
801*4882a593Smuzhiyun * not be completed with its reset
802*4882a593Smuzhiyun * when PHY_BCR_RESET_ is cleared. 256us
803*4882a593Smuzhiyun * should suffice, but use 500us to be safe
804*4882a593Smuzhiyun */
805*4882a593Smuzhiyun udelay(500);
806*4882a593Smuzhiyun break;
807*4882a593Smuzhiyun }
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun return reg & PMT_CTRL_PHY_RST_;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun /**
814*4882a593Smuzhiyun * smc911x_phy_powerdown - powerdown phy
815*4882a593Smuzhiyun * @dev: net device
816*4882a593Smuzhiyun * @phy: phy address
817*4882a593Smuzhiyun *
818*4882a593Smuzhiyun * Power down the specified PHY
819*4882a593Smuzhiyun */
smc911x_phy_powerdown(struct net_device * dev,int phy)820*4882a593Smuzhiyun static void smc911x_phy_powerdown(struct net_device *dev, int phy)
821*4882a593Smuzhiyun {
822*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
823*4882a593Smuzhiyun unsigned int bmcr;
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun /* Enter Link Disable state */
826*4882a593Smuzhiyun SMC_GET_PHY_BMCR(lp, phy, bmcr);
827*4882a593Smuzhiyun bmcr |= BMCR_PDOWN;
828*4882a593Smuzhiyun SMC_SET_PHY_BMCR(lp, phy, bmcr);
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun /**
832*4882a593Smuzhiyun * smc911x_phy_check_media - check the media status and adjust BMCR
833*4882a593Smuzhiyun * @dev: net device
834*4882a593Smuzhiyun * @init: set true for initialisation
835*4882a593Smuzhiyun *
836*4882a593Smuzhiyun * Select duplex mode depending on negotiation state. This
837*4882a593Smuzhiyun * also updates our carrier state.
838*4882a593Smuzhiyun */
smc911x_phy_check_media(struct net_device * dev,int init)839*4882a593Smuzhiyun static void smc911x_phy_check_media(struct net_device *dev, int init)
840*4882a593Smuzhiyun {
841*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
842*4882a593Smuzhiyun int phyaddr = lp->mii.phy_id;
843*4882a593Smuzhiyun unsigned int bmcr, cr;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
848*4882a593Smuzhiyun /* duplex state has changed */
849*4882a593Smuzhiyun SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
850*4882a593Smuzhiyun SMC_GET_MAC_CR(lp, cr);
851*4882a593Smuzhiyun if (lp->mii.full_duplex) {
852*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "Configuring for full-duplex mode\n");
853*4882a593Smuzhiyun bmcr |= BMCR_FULLDPLX;
854*4882a593Smuzhiyun cr |= MAC_CR_RCVOWN_;
855*4882a593Smuzhiyun } else {
856*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "Configuring for half-duplex mode\n");
857*4882a593Smuzhiyun bmcr &= ~BMCR_FULLDPLX;
858*4882a593Smuzhiyun cr &= ~MAC_CR_RCVOWN_;
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
861*4882a593Smuzhiyun SMC_SET_MAC_CR(lp, cr);
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun }
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun /*
866*4882a593Smuzhiyun * Configures the specified PHY through the MII management interface
867*4882a593Smuzhiyun * using Autonegotiation.
868*4882a593Smuzhiyun * Calls smc911x_phy_fixed() if the user has requested a certain config.
869*4882a593Smuzhiyun * If RPC ANEG bit is set, the media selection is dependent purely on
870*4882a593Smuzhiyun * the selection by the MII (either in the MII BMCR reg or the result
871*4882a593Smuzhiyun * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
872*4882a593Smuzhiyun * is controlled by the RPC SPEED and RPC DPLX bits.
873*4882a593Smuzhiyun */
smc911x_phy_configure(struct work_struct * work)874*4882a593Smuzhiyun static void smc911x_phy_configure(struct work_struct *work)
875*4882a593Smuzhiyun {
876*4882a593Smuzhiyun struct smc911x_local *lp = container_of(work, struct smc911x_local,
877*4882a593Smuzhiyun phy_configure);
878*4882a593Smuzhiyun struct net_device *dev = lp->netdev;
879*4882a593Smuzhiyun int phyaddr = lp->mii.phy_id;
880*4882a593Smuzhiyun int my_phy_caps; /* My PHY capabilities */
881*4882a593Smuzhiyun int my_ad_caps; /* My Advertised capabilities */
882*4882a593Smuzhiyun int status;
883*4882a593Smuzhiyun unsigned long flags;
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s()\n", __func__);
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun /*
888*4882a593Smuzhiyun * We should not be called if phy_type is zero.
889*4882a593Smuzhiyun */
890*4882a593Smuzhiyun if (lp->phy_type == 0)
891*4882a593Smuzhiyun return;
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun if (smc911x_phy_reset(dev, phyaddr)) {
894*4882a593Smuzhiyun netdev_info(dev, "PHY reset timed out\n");
895*4882a593Smuzhiyun return;
896*4882a593Smuzhiyun }
897*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun /*
900*4882a593Smuzhiyun * Enable PHY Interrupts (for register 18)
901*4882a593Smuzhiyun * Interrupts listed here are enabled
902*4882a593Smuzhiyun */
903*4882a593Smuzhiyun SMC_SET_PHY_INT_MASK(lp, phyaddr, PHY_INT_MASK_ENERGY_ON_ |
904*4882a593Smuzhiyun PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ |
905*4882a593Smuzhiyun PHY_INT_MASK_LINK_DOWN_);
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun /* If the user requested no auto neg, then go set his request */
908*4882a593Smuzhiyun if (lp->mii.force_media) {
909*4882a593Smuzhiyun smc911x_phy_fixed(dev);
910*4882a593Smuzhiyun goto smc911x_phy_configure_exit;
911*4882a593Smuzhiyun }
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
914*4882a593Smuzhiyun SMC_GET_PHY_BMSR(lp, phyaddr, my_phy_caps);
915*4882a593Smuzhiyun if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
916*4882a593Smuzhiyun netdev_info(dev, "Auto negotiation NOT supported\n");
917*4882a593Smuzhiyun smc911x_phy_fixed(dev);
918*4882a593Smuzhiyun goto smc911x_phy_configure_exit;
919*4882a593Smuzhiyun }
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun /* CSMA capable w/ both pauses */
922*4882a593Smuzhiyun my_ad_caps = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun if (my_phy_caps & BMSR_100BASE4)
925*4882a593Smuzhiyun my_ad_caps |= ADVERTISE_100BASE4;
926*4882a593Smuzhiyun if (my_phy_caps & BMSR_100FULL)
927*4882a593Smuzhiyun my_ad_caps |= ADVERTISE_100FULL;
928*4882a593Smuzhiyun if (my_phy_caps & BMSR_100HALF)
929*4882a593Smuzhiyun my_ad_caps |= ADVERTISE_100HALF;
930*4882a593Smuzhiyun if (my_phy_caps & BMSR_10FULL)
931*4882a593Smuzhiyun my_ad_caps |= ADVERTISE_10FULL;
932*4882a593Smuzhiyun if (my_phy_caps & BMSR_10HALF)
933*4882a593Smuzhiyun my_ad_caps |= ADVERTISE_10HALF;
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun /* Disable capabilities not selected by our user */
936*4882a593Smuzhiyun if (lp->ctl_rspeed != 100)
937*4882a593Smuzhiyun my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun if (!lp->ctl_rfduplx)
940*4882a593Smuzhiyun my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun /* Update our Auto-Neg Advertisement Register */
943*4882a593Smuzhiyun SMC_SET_PHY_MII_ADV(lp, phyaddr, my_ad_caps);
944*4882a593Smuzhiyun lp->mii.advertising = my_ad_caps;
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun /*
947*4882a593Smuzhiyun * Read the register back. Without this, it appears that when
948*4882a593Smuzhiyun * auto-negotiation is restarted, sometimes it isn't ready and
949*4882a593Smuzhiyun * the link does not come up.
950*4882a593Smuzhiyun */
951*4882a593Smuzhiyun udelay(10);
952*4882a593Smuzhiyun SMC_GET_PHY_MII_ADV(lp, phyaddr, status);
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "phy caps=0x%04x\n", my_phy_caps);
955*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "phy advertised caps=0x%04x\n", my_ad_caps);
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun /* Restart auto-negotiation process in order to advertise my caps */
958*4882a593Smuzhiyun SMC_SET_PHY_BMCR(lp, phyaddr, BMCR_ANENABLE | BMCR_ANRESTART);
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun smc911x_phy_check_media(dev, 1);
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun smc911x_phy_configure_exit:
963*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun /*
967*4882a593Smuzhiyun * smc911x_phy_interrupt
968*4882a593Smuzhiyun *
969*4882a593Smuzhiyun * Purpose: Handle interrupts relating to PHY register 18. This is
970*4882a593Smuzhiyun * called from the "hard" interrupt handler under our private spinlock.
971*4882a593Smuzhiyun */
smc911x_phy_interrupt(struct net_device * dev)972*4882a593Smuzhiyun static void smc911x_phy_interrupt(struct net_device *dev)
973*4882a593Smuzhiyun {
974*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
975*4882a593Smuzhiyun int phyaddr = lp->mii.phy_id;
976*4882a593Smuzhiyun int status;
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun if (lp->phy_type == 0)
981*4882a593Smuzhiyun return;
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun smc911x_phy_check_media(dev, 0);
984*4882a593Smuzhiyun /* read to clear status bits */
985*4882a593Smuzhiyun SMC_GET_PHY_INT_SRC(lp, phyaddr,status);
986*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "PHY interrupt status 0x%04x\n",
987*4882a593Smuzhiyun status & 0xffff);
988*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "AFC_CFG 0x%08x\n",
989*4882a593Smuzhiyun SMC_GET_AFC_CFG(lp));
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun /*
995*4882a593Smuzhiyun * This is the main routine of the driver, to handle the device when
996*4882a593Smuzhiyun * it needs some attention.
997*4882a593Smuzhiyun */
smc911x_interrupt(int irq,void * dev_id)998*4882a593Smuzhiyun static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun struct net_device *dev = dev_id;
1001*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1002*4882a593Smuzhiyun unsigned int status, mask, timeout;
1003*4882a593Smuzhiyun unsigned int rx_overrun=0, cr, pkts;
1004*4882a593Smuzhiyun unsigned long flags;
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun /* Spurious interrupt check */
1011*4882a593Smuzhiyun if ((SMC_GET_IRQ_CFG(lp) & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
1012*4882a593Smuzhiyun (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
1013*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1014*4882a593Smuzhiyun return IRQ_NONE;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun mask = SMC_GET_INT_EN(lp);
1018*4882a593Smuzhiyun SMC_SET_INT_EN(lp, 0);
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun /* set a timeout value, so I don't stay here forever */
1021*4882a593Smuzhiyun timeout = 8;
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun do {
1025*4882a593Smuzhiyun status = SMC_GET_INT(lp);
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n",
1028*4882a593Smuzhiyun status, mask, status & ~mask);
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun status &= mask;
1031*4882a593Smuzhiyun if (!status)
1032*4882a593Smuzhiyun break;
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun /* Handle SW interrupt condition */
1035*4882a593Smuzhiyun if (status & INT_STS_SW_INT_) {
1036*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_SW_INT_);
1037*4882a593Smuzhiyun mask &= ~INT_EN_SW_INT_EN_;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun /* Handle various error conditions */
1040*4882a593Smuzhiyun if (status & INT_STS_RXE_) {
1041*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_RXE_);
1042*4882a593Smuzhiyun dev->stats.rx_errors++;
1043*4882a593Smuzhiyun }
1044*4882a593Smuzhiyun if (status & INT_STS_RXDFH_INT_) {
1045*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_RXDFH_INT_);
1046*4882a593Smuzhiyun dev->stats.rx_dropped+=SMC_GET_RX_DROP(lp);
1047*4882a593Smuzhiyun }
1048*4882a593Smuzhiyun /* Undocumented interrupt-what is the right thing to do here? */
1049*4882a593Smuzhiyun if (status & INT_STS_RXDF_INT_) {
1050*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_RXDF_INT_);
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun /* Rx Data FIFO exceeds set level */
1054*4882a593Smuzhiyun if (status & INT_STS_RDFL_) {
1055*4882a593Smuzhiyun if (IS_REV_A(lp->revision)) {
1056*4882a593Smuzhiyun rx_overrun=1;
1057*4882a593Smuzhiyun SMC_GET_MAC_CR(lp, cr);
1058*4882a593Smuzhiyun cr &= ~MAC_CR_RXEN_;
1059*4882a593Smuzhiyun SMC_SET_MAC_CR(lp, cr);
1060*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "RX overrun\n");
1061*4882a593Smuzhiyun dev->stats.rx_errors++;
1062*4882a593Smuzhiyun dev->stats.rx_fifo_errors++;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_RDFL_);
1065*4882a593Smuzhiyun }
1066*4882a593Smuzhiyun if (status & INT_STS_RDFO_) {
1067*4882a593Smuzhiyun if (!IS_REV_A(lp->revision)) {
1068*4882a593Smuzhiyun SMC_GET_MAC_CR(lp, cr);
1069*4882a593Smuzhiyun cr &= ~MAC_CR_RXEN_;
1070*4882a593Smuzhiyun SMC_SET_MAC_CR(lp, cr);
1071*4882a593Smuzhiyun rx_overrun=1;
1072*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "RX overrun\n");
1073*4882a593Smuzhiyun dev->stats.rx_errors++;
1074*4882a593Smuzhiyun dev->stats.rx_fifo_errors++;
1075*4882a593Smuzhiyun }
1076*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_RDFO_);
1077*4882a593Smuzhiyun }
1078*4882a593Smuzhiyun /* Handle receive condition */
1079*4882a593Smuzhiyun if ((status & INT_STS_RSFL_) || rx_overrun) {
1080*4882a593Smuzhiyun unsigned int fifo;
1081*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "RX irq\n");
1082*4882a593Smuzhiyun fifo = SMC_GET_RX_FIFO_INF(lp);
1083*4882a593Smuzhiyun pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16;
1084*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "Rx FIFO pkts %d, bytes %d\n",
1085*4882a593Smuzhiyun pkts, fifo & 0xFFFF);
1086*4882a593Smuzhiyun if (pkts != 0) {
1087*4882a593Smuzhiyun #ifdef SMC_USE_DMA
1088*4882a593Smuzhiyun unsigned int fifo;
1089*4882a593Smuzhiyun if (lp->rxdma_active){
1090*4882a593Smuzhiyun DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, dev,
1091*4882a593Smuzhiyun "RX DMA active\n");
1092*4882a593Smuzhiyun /* The DMA is already running so up the IRQ threshold */
1093*4882a593Smuzhiyun fifo = SMC_GET_FIFO_INT(lp) & ~0xFF;
1094*4882a593Smuzhiyun fifo |= pkts & 0xFF;
1095*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev,
1096*4882a593Smuzhiyun "Setting RX stat FIFO threshold to %d\n",
1097*4882a593Smuzhiyun fifo & 0xff);
1098*4882a593Smuzhiyun SMC_SET_FIFO_INT(lp, fifo);
1099*4882a593Smuzhiyun } else
1100*4882a593Smuzhiyun #endif
1101*4882a593Smuzhiyun smc911x_rcv(dev);
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_RSFL_);
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun /* Handle transmit FIFO available */
1106*4882a593Smuzhiyun if (status & INT_STS_TDFA_) {
1107*4882a593Smuzhiyun DBG(SMC_DEBUG_TX, dev, "TX data FIFO space available irq\n");
1108*4882a593Smuzhiyun SMC_SET_FIFO_TDA(lp, 0xFF);
1109*4882a593Smuzhiyun lp->tx_throttle = 0;
1110*4882a593Smuzhiyun #ifdef SMC_USE_DMA
1111*4882a593Smuzhiyun if (!lp->txdma_active)
1112*4882a593Smuzhiyun #endif
1113*4882a593Smuzhiyun netif_wake_queue(dev);
1114*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_TDFA_);
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun /* Handle transmit done condition */
1117*4882a593Smuzhiyun #if 1
1118*4882a593Smuzhiyun if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) {
1119*4882a593Smuzhiyun DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC, dev,
1120*4882a593Smuzhiyun "Tx stat FIFO limit (%d) /GPT irq\n",
1121*4882a593Smuzhiyun (SMC_GET_FIFO_INT(lp) & 0x00ff0000) >> 16);
1122*4882a593Smuzhiyun smc911x_tx(dev);
1123*4882a593Smuzhiyun SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1124*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_TSFL_);
1125*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_TSFL_ | INT_STS_GPT_INT_);
1126*4882a593Smuzhiyun }
1127*4882a593Smuzhiyun #else
1128*4882a593Smuzhiyun if (status & INT_STS_TSFL_) {
1129*4882a593Smuzhiyun DBG(SMC_DEBUG_TX, dev, "TX status FIFO limit (%d) irq\n", ?);
1130*4882a593Smuzhiyun smc911x_tx(dev);
1131*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_TSFL_);
1132*4882a593Smuzhiyun }
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun if (status & INT_STS_GPT_INT_) {
1135*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n",
1136*4882a593Smuzhiyun SMC_GET_IRQ_CFG(lp),
1137*4882a593Smuzhiyun SMC_GET_FIFO_INT(lp),
1138*4882a593Smuzhiyun SMC_GET_RX_CFG(lp));
1139*4882a593Smuzhiyun DBG(SMC_DEBUG_RX, dev, "Rx Stat FIFO Used 0x%02x Data FIFO Used 0x%04x Stat FIFO 0x%08x\n",
1140*4882a593Smuzhiyun (SMC_GET_RX_FIFO_INF(lp) & 0x00ff0000) >> 16,
1141*4882a593Smuzhiyun SMC_GET_RX_FIFO_INF(lp) & 0xffff,
1142*4882a593Smuzhiyun SMC_GET_RX_STS_FIFO_PEEK(lp));
1143*4882a593Smuzhiyun SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1144*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_GPT_INT_);
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun #endif
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun /* Handle PHY interrupt condition */
1149*4882a593Smuzhiyun if (status & INT_STS_PHY_INT_) {
1150*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "PHY irq\n");
1151*4882a593Smuzhiyun smc911x_phy_interrupt(dev);
1152*4882a593Smuzhiyun SMC_ACK_INT(lp, INT_STS_PHY_INT_);
1153*4882a593Smuzhiyun }
1154*4882a593Smuzhiyun } while (--timeout);
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun /* restore mask state */
1157*4882a593Smuzhiyun SMC_SET_INT_EN(lp, mask);
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "Interrupt done (%d loops)\n",
1160*4882a593Smuzhiyun 8-timeout);
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun return IRQ_HANDLED;
1165*4882a593Smuzhiyun }
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun #ifdef SMC_USE_DMA
1168*4882a593Smuzhiyun static void
smc911x_tx_dma_irq(void * data)1169*4882a593Smuzhiyun smc911x_tx_dma_irq(void *data)
1170*4882a593Smuzhiyun {
1171*4882a593Smuzhiyun struct smc911x_local *lp = data;
1172*4882a593Smuzhiyun struct net_device *dev = lp->netdev;
1173*4882a593Smuzhiyun struct sk_buff *skb = lp->current_tx_skb;
1174*4882a593Smuzhiyun unsigned long flags;
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev, "TX DMA irq handler\n");
1179*4882a593Smuzhiyun BUG_ON(skb == NULL);
1180*4882a593Smuzhiyun dma_unmap_single(lp->dev, tx_dmabuf, tx_dmalen, DMA_TO_DEVICE);
1181*4882a593Smuzhiyun netif_trans_update(dev);
1182*4882a593Smuzhiyun dev_kfree_skb_irq(skb);
1183*4882a593Smuzhiyun lp->current_tx_skb = NULL;
1184*4882a593Smuzhiyun if (lp->pending_tx_skb != NULL)
1185*4882a593Smuzhiyun smc911x_hardware_send_pkt(dev);
1186*4882a593Smuzhiyun else {
1187*4882a593Smuzhiyun DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev,
1188*4882a593Smuzhiyun "No pending Tx packets. DMA disabled\n");
1189*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1190*4882a593Smuzhiyun lp->txdma_active = 0;
1191*4882a593Smuzhiyun if (!lp->tx_throttle) {
1192*4882a593Smuzhiyun netif_wake_queue(dev);
1193*4882a593Smuzhiyun }
1194*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev,
1198*4882a593Smuzhiyun "TX DMA irq completed\n");
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun static void
smc911x_rx_dma_irq(void * data)1201*4882a593Smuzhiyun smc911x_rx_dma_irq(void *data)
1202*4882a593Smuzhiyun {
1203*4882a593Smuzhiyun struct smc911x_local *lp = data;
1204*4882a593Smuzhiyun struct net_device *dev = lp->netdev;
1205*4882a593Smuzhiyun struct sk_buff *skb = lp->current_rx_skb;
1206*4882a593Smuzhiyun unsigned long flags;
1207*4882a593Smuzhiyun unsigned int pkts;
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1210*4882a593Smuzhiyun DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, dev, "RX DMA irq handler\n");
1211*4882a593Smuzhiyun dma_unmap_single(lp->dev, rx_dmabuf, rx_dmalen, DMA_FROM_DEVICE);
1212*4882a593Smuzhiyun BUG_ON(skb == NULL);
1213*4882a593Smuzhiyun lp->current_rx_skb = NULL;
1214*4882a593Smuzhiyun PRINT_PKT(skb->data, skb->len);
1215*4882a593Smuzhiyun skb->protocol = eth_type_trans(skb, dev);
1216*4882a593Smuzhiyun dev->stats.rx_packets++;
1217*4882a593Smuzhiyun dev->stats.rx_bytes += skb->len;
1218*4882a593Smuzhiyun netif_rx(skb);
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1221*4882a593Smuzhiyun pkts = (SMC_GET_RX_FIFO_INF(lp) & RX_FIFO_INF_RXSUSED_) >> 16;
1222*4882a593Smuzhiyun if (pkts != 0) {
1223*4882a593Smuzhiyun smc911x_rcv(dev);
1224*4882a593Smuzhiyun }else {
1225*4882a593Smuzhiyun lp->rxdma_active = 0;
1226*4882a593Smuzhiyun }
1227*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1228*4882a593Smuzhiyun DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, dev,
1229*4882a593Smuzhiyun "RX DMA irq completed. DMA RX FIFO PKTS %d\n",
1230*4882a593Smuzhiyun pkts);
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun #endif /* SMC_USE_DMA */
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun #ifdef CONFIG_NET_POLL_CONTROLLER
1235*4882a593Smuzhiyun /*
1236*4882a593Smuzhiyun * Polling receive - used by netconsole and other diagnostic tools
1237*4882a593Smuzhiyun * to allow network i/o with interrupts disabled.
1238*4882a593Smuzhiyun */
smc911x_poll_controller(struct net_device * dev)1239*4882a593Smuzhiyun static void smc911x_poll_controller(struct net_device *dev)
1240*4882a593Smuzhiyun {
1241*4882a593Smuzhiyun disable_irq(dev->irq);
1242*4882a593Smuzhiyun smc911x_interrupt(dev->irq, dev);
1243*4882a593Smuzhiyun enable_irq(dev->irq);
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun #endif
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun /* Our watchdog timed out. Called by the networking layer */
smc911x_timeout(struct net_device * dev,unsigned int txqueue)1248*4882a593Smuzhiyun static void smc911x_timeout(struct net_device *dev, unsigned int txqueue)
1249*4882a593Smuzhiyun {
1250*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1251*4882a593Smuzhiyun int status, mask;
1252*4882a593Smuzhiyun unsigned long flags;
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1255*4882a593Smuzhiyun
1256*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1257*4882a593Smuzhiyun status = SMC_GET_INT(lp);
1258*4882a593Smuzhiyun mask = SMC_GET_INT_EN(lp);
1259*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1260*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "INT 0x%02x MASK 0x%02x\n",
1261*4882a593Smuzhiyun status, mask);
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun /* Dump the current TX FIFO contents and restart */
1264*4882a593Smuzhiyun mask = SMC_GET_TX_CFG(lp);
1265*4882a593Smuzhiyun SMC_SET_TX_CFG(lp, mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_);
1266*4882a593Smuzhiyun /*
1267*4882a593Smuzhiyun * Reconfiguring the PHY doesn't seem like a bad idea here, but
1268*4882a593Smuzhiyun * smc911x_phy_configure() calls msleep() which calls schedule_timeout()
1269*4882a593Smuzhiyun * which calls schedule(). Hence we use a work queue.
1270*4882a593Smuzhiyun */
1271*4882a593Smuzhiyun if (lp->phy_type != 0)
1272*4882a593Smuzhiyun schedule_work(&lp->phy_configure);
1273*4882a593Smuzhiyun
1274*4882a593Smuzhiyun /* We can accept TX packets again */
1275*4882a593Smuzhiyun netif_trans_update(dev); /* prevent tx timeout */
1276*4882a593Smuzhiyun netif_wake_queue(dev);
1277*4882a593Smuzhiyun }
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun /*
1280*4882a593Smuzhiyun * This routine will, depending on the values passed to it,
1281*4882a593Smuzhiyun * either make it accept multicast packets, go into
1282*4882a593Smuzhiyun * promiscuous mode (for TCPDUMP and cousins) or accept
1283*4882a593Smuzhiyun * a select set of multicast packets
1284*4882a593Smuzhiyun */
smc911x_set_multicast_list(struct net_device * dev)1285*4882a593Smuzhiyun static void smc911x_set_multicast_list(struct net_device *dev)
1286*4882a593Smuzhiyun {
1287*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1288*4882a593Smuzhiyun unsigned int multicast_table[2];
1289*4882a593Smuzhiyun unsigned int mcr, update_multicast = 0;
1290*4882a593Smuzhiyun unsigned long flags;
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1293*4882a593Smuzhiyun
1294*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1295*4882a593Smuzhiyun SMC_GET_MAC_CR(lp, mcr);
1296*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun if (dev->flags & IFF_PROMISC) {
1299*4882a593Smuzhiyun
1300*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "RCR_PRMS\n");
1301*4882a593Smuzhiyun mcr |= MAC_CR_PRMS_;
1302*4882a593Smuzhiyun }
1303*4882a593Smuzhiyun /*
1304*4882a593Smuzhiyun * Here, I am setting this to accept all multicast packets.
1305*4882a593Smuzhiyun * I don't need to zero the multicast table, because the flag is
1306*4882a593Smuzhiyun * checked before the table is
1307*4882a593Smuzhiyun */
1308*4882a593Smuzhiyun else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
1309*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "RCR_ALMUL\n");
1310*4882a593Smuzhiyun mcr |= MAC_CR_MCPAS_;
1311*4882a593Smuzhiyun }
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun /*
1314*4882a593Smuzhiyun * This sets the internal hardware table to filter out unwanted
1315*4882a593Smuzhiyun * multicast packets before they take up memory.
1316*4882a593Smuzhiyun *
1317*4882a593Smuzhiyun * The SMC chip uses a hash table where the high 6 bits of the CRC of
1318*4882a593Smuzhiyun * address are the offset into the table. If that bit is 1, then the
1319*4882a593Smuzhiyun * multicast packet is accepted. Otherwise, it's dropped silently.
1320*4882a593Smuzhiyun *
1321*4882a593Smuzhiyun * To use the 6 bits as an offset into the table, the high 1 bit is
1322*4882a593Smuzhiyun * the number of the 32 bit register, while the low 5 bits are the bit
1323*4882a593Smuzhiyun * within that register.
1324*4882a593Smuzhiyun */
1325*4882a593Smuzhiyun else if (!netdev_mc_empty(dev)) {
1326*4882a593Smuzhiyun struct netdev_hw_addr *ha;
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun /* Set the Hash perfec mode */
1329*4882a593Smuzhiyun mcr |= MAC_CR_HPFILT_;
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun /* start with a table of all zeros: reject all */
1332*4882a593Smuzhiyun memset(multicast_table, 0, sizeof(multicast_table));
1333*4882a593Smuzhiyun
1334*4882a593Smuzhiyun netdev_for_each_mc_addr(ha, dev) {
1335*4882a593Smuzhiyun u32 position;
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun /* upper 6 bits are used as hash index */
1338*4882a593Smuzhiyun position = ether_crc(ETH_ALEN, ha->addr)>>26;
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun multicast_table[position>>5] |= 1 << (position&0x1f);
1341*4882a593Smuzhiyun }
1342*4882a593Smuzhiyun
1343*4882a593Smuzhiyun /* be sure I get rid of flags I might have set */
1344*4882a593Smuzhiyun mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun /* now, the table can be loaded into the chipset */
1347*4882a593Smuzhiyun update_multicast = 1;
1348*4882a593Smuzhiyun } else {
1349*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "~(MAC_CR_PRMS_|MAC_CR_MCPAS_)\n");
1350*4882a593Smuzhiyun mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun /*
1353*4882a593Smuzhiyun * since I'm disabling all multicast entirely, I need to
1354*4882a593Smuzhiyun * clear the multicast list
1355*4882a593Smuzhiyun */
1356*4882a593Smuzhiyun memset(multicast_table, 0, sizeof(multicast_table));
1357*4882a593Smuzhiyun update_multicast = 1;
1358*4882a593Smuzhiyun }
1359*4882a593Smuzhiyun
1360*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1361*4882a593Smuzhiyun SMC_SET_MAC_CR(lp, mcr);
1362*4882a593Smuzhiyun if (update_multicast) {
1363*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev,
1364*4882a593Smuzhiyun "update mcast hash table 0x%08x 0x%08x\n",
1365*4882a593Smuzhiyun multicast_table[0], multicast_table[1]);
1366*4882a593Smuzhiyun SMC_SET_HASHL(lp, multicast_table[0]);
1367*4882a593Smuzhiyun SMC_SET_HASHH(lp, multicast_table[1]);
1368*4882a593Smuzhiyun }
1369*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1370*4882a593Smuzhiyun }
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun
1373*4882a593Smuzhiyun /*
1374*4882a593Smuzhiyun * Open and Initialize the board
1375*4882a593Smuzhiyun *
1376*4882a593Smuzhiyun * Set up everything, reset the card, etc..
1377*4882a593Smuzhiyun */
1378*4882a593Smuzhiyun static int
smc911x_open(struct net_device * dev)1379*4882a593Smuzhiyun smc911x_open(struct net_device *dev)
1380*4882a593Smuzhiyun {
1381*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1384*4882a593Smuzhiyun
1385*4882a593Smuzhiyun /* reset the hardware */
1386*4882a593Smuzhiyun smc911x_reset(dev);
1387*4882a593Smuzhiyun
1388*4882a593Smuzhiyun /* Configure the PHY, initialize the link state */
1389*4882a593Smuzhiyun smc911x_phy_configure(&lp->phy_configure);
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun /* Turn on Tx + Rx */
1392*4882a593Smuzhiyun smc911x_enable(dev);
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun netif_start_queue(dev);
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun return 0;
1397*4882a593Smuzhiyun }
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun /*
1400*4882a593Smuzhiyun * smc911x_close
1401*4882a593Smuzhiyun *
1402*4882a593Smuzhiyun * this makes the board clean up everything that it can
1403*4882a593Smuzhiyun * and not talk to the outside world. Caused by
1404*4882a593Smuzhiyun * an 'ifconfig ethX down'
1405*4882a593Smuzhiyun */
smc911x_close(struct net_device * dev)1406*4882a593Smuzhiyun static int smc911x_close(struct net_device *dev)
1407*4882a593Smuzhiyun {
1408*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun netif_stop_queue(dev);
1413*4882a593Smuzhiyun netif_carrier_off(dev);
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun /* clear everything */
1416*4882a593Smuzhiyun smc911x_shutdown(dev);
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun if (lp->phy_type != 0) {
1419*4882a593Smuzhiyun /* We need to ensure that no calls to
1420*4882a593Smuzhiyun * smc911x_phy_configure are pending.
1421*4882a593Smuzhiyun */
1422*4882a593Smuzhiyun cancel_work_sync(&lp->phy_configure);
1423*4882a593Smuzhiyun smc911x_phy_powerdown(dev, lp->mii.phy_id);
1424*4882a593Smuzhiyun }
1425*4882a593Smuzhiyun
1426*4882a593Smuzhiyun if (lp->pending_tx_skb) {
1427*4882a593Smuzhiyun dev_kfree_skb(lp->pending_tx_skb);
1428*4882a593Smuzhiyun lp->pending_tx_skb = NULL;
1429*4882a593Smuzhiyun }
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun return 0;
1432*4882a593Smuzhiyun }
1433*4882a593Smuzhiyun
1434*4882a593Smuzhiyun /*
1435*4882a593Smuzhiyun * Ethtool support
1436*4882a593Smuzhiyun */
1437*4882a593Smuzhiyun static int
smc911x_ethtool_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)1438*4882a593Smuzhiyun smc911x_ethtool_get_link_ksettings(struct net_device *dev,
1439*4882a593Smuzhiyun struct ethtool_link_ksettings *cmd)
1440*4882a593Smuzhiyun {
1441*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1442*4882a593Smuzhiyun int status;
1443*4882a593Smuzhiyun unsigned long flags;
1444*4882a593Smuzhiyun u32 supported;
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1447*4882a593Smuzhiyun
1448*4882a593Smuzhiyun if (lp->phy_type != 0) {
1449*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1450*4882a593Smuzhiyun mii_ethtool_get_link_ksettings(&lp->mii, cmd);
1451*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1452*4882a593Smuzhiyun } else {
1453*4882a593Smuzhiyun supported = SUPPORTED_10baseT_Half |
1454*4882a593Smuzhiyun SUPPORTED_10baseT_Full |
1455*4882a593Smuzhiyun SUPPORTED_TP | SUPPORTED_AUI;
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun if (lp->ctl_rspeed == 10)
1458*4882a593Smuzhiyun cmd->base.speed = SPEED_10;
1459*4882a593Smuzhiyun else if (lp->ctl_rspeed == 100)
1460*4882a593Smuzhiyun cmd->base.speed = SPEED_100;
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun cmd->base.autoneg = AUTONEG_DISABLE;
1463*4882a593Smuzhiyun cmd->base.port = 0;
1464*4882a593Smuzhiyun SMC_GET_PHY_SPECIAL(lp, lp->mii.phy_id, status);
1465*4882a593Smuzhiyun cmd->base.duplex =
1466*4882a593Smuzhiyun (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ?
1467*4882a593Smuzhiyun DUPLEX_FULL : DUPLEX_HALF;
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun ethtool_convert_legacy_u32_to_link_mode(
1470*4882a593Smuzhiyun cmd->link_modes.supported, supported);
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun }
1473*4882a593Smuzhiyun
1474*4882a593Smuzhiyun return 0;
1475*4882a593Smuzhiyun }
1476*4882a593Smuzhiyun
1477*4882a593Smuzhiyun static int
smc911x_ethtool_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)1478*4882a593Smuzhiyun smc911x_ethtool_set_link_ksettings(struct net_device *dev,
1479*4882a593Smuzhiyun const struct ethtool_link_ksettings *cmd)
1480*4882a593Smuzhiyun {
1481*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1482*4882a593Smuzhiyun int ret;
1483*4882a593Smuzhiyun unsigned long flags;
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun if (lp->phy_type != 0) {
1486*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1487*4882a593Smuzhiyun ret = mii_ethtool_set_link_ksettings(&lp->mii, cmd);
1488*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1489*4882a593Smuzhiyun } else {
1490*4882a593Smuzhiyun if (cmd->base.autoneg != AUTONEG_DISABLE ||
1491*4882a593Smuzhiyun cmd->base.speed != SPEED_10 ||
1492*4882a593Smuzhiyun (cmd->base.duplex != DUPLEX_HALF &&
1493*4882a593Smuzhiyun cmd->base.duplex != DUPLEX_FULL) ||
1494*4882a593Smuzhiyun (cmd->base.port != PORT_TP &&
1495*4882a593Smuzhiyun cmd->base.port != PORT_AUI))
1496*4882a593Smuzhiyun return -EINVAL;
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL;
1499*4882a593Smuzhiyun
1500*4882a593Smuzhiyun ret = 0;
1501*4882a593Smuzhiyun }
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun return ret;
1504*4882a593Smuzhiyun }
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun static void
smc911x_ethtool_getdrvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1507*4882a593Smuzhiyun smc911x_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1508*4882a593Smuzhiyun {
1509*4882a593Smuzhiyun strlcpy(info->driver, CARDNAME, sizeof(info->driver));
1510*4882a593Smuzhiyun strlcpy(info->version, version, sizeof(info->version));
1511*4882a593Smuzhiyun strlcpy(info->bus_info, dev_name(dev->dev.parent),
1512*4882a593Smuzhiyun sizeof(info->bus_info));
1513*4882a593Smuzhiyun }
1514*4882a593Smuzhiyun
smc911x_ethtool_nwayreset(struct net_device * dev)1515*4882a593Smuzhiyun static int smc911x_ethtool_nwayreset(struct net_device *dev)
1516*4882a593Smuzhiyun {
1517*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1518*4882a593Smuzhiyun int ret = -EINVAL;
1519*4882a593Smuzhiyun unsigned long flags;
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun if (lp->phy_type != 0) {
1522*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1523*4882a593Smuzhiyun ret = mii_nway_restart(&lp->mii);
1524*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1525*4882a593Smuzhiyun }
1526*4882a593Smuzhiyun
1527*4882a593Smuzhiyun return ret;
1528*4882a593Smuzhiyun }
1529*4882a593Smuzhiyun
smc911x_ethtool_getmsglevel(struct net_device * dev)1530*4882a593Smuzhiyun static u32 smc911x_ethtool_getmsglevel(struct net_device *dev)
1531*4882a593Smuzhiyun {
1532*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1533*4882a593Smuzhiyun return lp->msg_enable;
1534*4882a593Smuzhiyun }
1535*4882a593Smuzhiyun
smc911x_ethtool_setmsglevel(struct net_device * dev,u32 level)1536*4882a593Smuzhiyun static void smc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1537*4882a593Smuzhiyun {
1538*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1539*4882a593Smuzhiyun lp->msg_enable = level;
1540*4882a593Smuzhiyun }
1541*4882a593Smuzhiyun
smc911x_ethtool_getregslen(struct net_device * dev)1542*4882a593Smuzhiyun static int smc911x_ethtool_getregslen(struct net_device *dev)
1543*4882a593Smuzhiyun {
1544*4882a593Smuzhiyun /* System regs + MAC regs + PHY regs */
1545*4882a593Smuzhiyun return (((E2P_CMD - ID_REV)/4 + 1) +
1546*4882a593Smuzhiyun (WUCSR - MAC_CR)+1 + 32) * sizeof(u32);
1547*4882a593Smuzhiyun }
1548*4882a593Smuzhiyun
smc911x_ethtool_getregs(struct net_device * dev,struct ethtool_regs * regs,void * buf)1549*4882a593Smuzhiyun static void smc911x_ethtool_getregs(struct net_device *dev,
1550*4882a593Smuzhiyun struct ethtool_regs* regs, void *buf)
1551*4882a593Smuzhiyun {
1552*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1553*4882a593Smuzhiyun unsigned long flags;
1554*4882a593Smuzhiyun u32 reg,i,j=0;
1555*4882a593Smuzhiyun u32 *data = (u32*)buf;
1556*4882a593Smuzhiyun
1557*4882a593Smuzhiyun regs->version = lp->version;
1558*4882a593Smuzhiyun for(i=ID_REV;i<=E2P_CMD;i+=4) {
1559*4882a593Smuzhiyun data[j++] = SMC_inl(lp, i);
1560*4882a593Smuzhiyun }
1561*4882a593Smuzhiyun for(i=MAC_CR;i<=WUCSR;i++) {
1562*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1563*4882a593Smuzhiyun SMC_GET_MAC_CSR(lp, i, reg);
1564*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1565*4882a593Smuzhiyun data[j++] = reg;
1566*4882a593Smuzhiyun }
1567*4882a593Smuzhiyun for(i=0;i<=31;i++) {
1568*4882a593Smuzhiyun spin_lock_irqsave(&lp->lock, flags);
1569*4882a593Smuzhiyun SMC_GET_MII(lp, i, lp->mii.phy_id, reg);
1570*4882a593Smuzhiyun spin_unlock_irqrestore(&lp->lock, flags);
1571*4882a593Smuzhiyun data[j++] = reg & 0xFFFF;
1572*4882a593Smuzhiyun }
1573*4882a593Smuzhiyun }
1574*4882a593Smuzhiyun
smc911x_ethtool_wait_eeprom_ready(struct net_device * dev)1575*4882a593Smuzhiyun static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1576*4882a593Smuzhiyun {
1577*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1578*4882a593Smuzhiyun unsigned int timeout;
1579*4882a593Smuzhiyun int e2p_cmd;
1580*4882a593Smuzhiyun
1581*4882a593Smuzhiyun e2p_cmd = SMC_GET_E2P_CMD(lp);
1582*4882a593Smuzhiyun for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) {
1583*4882a593Smuzhiyun if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) {
1584*4882a593Smuzhiyun PRINTK(dev, "%s timeout waiting for EEPROM to respond\n",
1585*4882a593Smuzhiyun __func__);
1586*4882a593Smuzhiyun return -EFAULT;
1587*4882a593Smuzhiyun }
1588*4882a593Smuzhiyun mdelay(1);
1589*4882a593Smuzhiyun e2p_cmd = SMC_GET_E2P_CMD(lp);
1590*4882a593Smuzhiyun }
1591*4882a593Smuzhiyun if (timeout == 0) {
1592*4882a593Smuzhiyun PRINTK(dev, "%s timeout waiting for EEPROM CMD not busy\n",
1593*4882a593Smuzhiyun __func__);
1594*4882a593Smuzhiyun return -ETIMEDOUT;
1595*4882a593Smuzhiyun }
1596*4882a593Smuzhiyun return 0;
1597*4882a593Smuzhiyun }
1598*4882a593Smuzhiyun
smc911x_ethtool_write_eeprom_cmd(struct net_device * dev,int cmd,int addr)1599*4882a593Smuzhiyun static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
1600*4882a593Smuzhiyun int cmd, int addr)
1601*4882a593Smuzhiyun {
1602*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1603*4882a593Smuzhiyun int ret;
1604*4882a593Smuzhiyun
1605*4882a593Smuzhiyun if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1606*4882a593Smuzhiyun return ret;
1607*4882a593Smuzhiyun SMC_SET_E2P_CMD(lp, E2P_CMD_EPC_BUSY_ |
1608*4882a593Smuzhiyun ((cmd) & (0x7<<28)) |
1609*4882a593Smuzhiyun ((addr) & 0xFF));
1610*4882a593Smuzhiyun return 0;
1611*4882a593Smuzhiyun }
1612*4882a593Smuzhiyun
smc911x_ethtool_read_eeprom_byte(struct net_device * dev,u8 * data)1613*4882a593Smuzhiyun static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev,
1614*4882a593Smuzhiyun u8 *data)
1615*4882a593Smuzhiyun {
1616*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1617*4882a593Smuzhiyun int ret;
1618*4882a593Smuzhiyun
1619*4882a593Smuzhiyun if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1620*4882a593Smuzhiyun return ret;
1621*4882a593Smuzhiyun *data = SMC_GET_E2P_DATA(lp);
1622*4882a593Smuzhiyun return 0;
1623*4882a593Smuzhiyun }
1624*4882a593Smuzhiyun
smc911x_ethtool_write_eeprom_byte(struct net_device * dev,u8 data)1625*4882a593Smuzhiyun static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev,
1626*4882a593Smuzhiyun u8 data)
1627*4882a593Smuzhiyun {
1628*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1629*4882a593Smuzhiyun int ret;
1630*4882a593Smuzhiyun
1631*4882a593Smuzhiyun if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1632*4882a593Smuzhiyun return ret;
1633*4882a593Smuzhiyun SMC_SET_E2P_DATA(lp, data);
1634*4882a593Smuzhiyun return 0;
1635*4882a593Smuzhiyun }
1636*4882a593Smuzhiyun
smc911x_ethtool_geteeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)1637*4882a593Smuzhiyun static int smc911x_ethtool_geteeprom(struct net_device *dev,
1638*4882a593Smuzhiyun struct ethtool_eeprom *eeprom, u8 *data)
1639*4882a593Smuzhiyun {
1640*4882a593Smuzhiyun u8 eebuf[SMC911X_EEPROM_LEN];
1641*4882a593Smuzhiyun int i, ret;
1642*4882a593Smuzhiyun
1643*4882a593Smuzhiyun for(i=0;i<SMC911X_EEPROM_LEN;i++) {
1644*4882a593Smuzhiyun if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ_, i ))!=0)
1645*4882a593Smuzhiyun return ret;
1646*4882a593Smuzhiyun if ((ret=smc911x_ethtool_read_eeprom_byte(dev, &eebuf[i]))!=0)
1647*4882a593Smuzhiyun return ret;
1648*4882a593Smuzhiyun }
1649*4882a593Smuzhiyun memcpy(data, eebuf+eeprom->offset, eeprom->len);
1650*4882a593Smuzhiyun return 0;
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun
smc911x_ethtool_seteeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)1653*4882a593Smuzhiyun static int smc911x_ethtool_seteeprom(struct net_device *dev,
1654*4882a593Smuzhiyun struct ethtool_eeprom *eeprom, u8 *data)
1655*4882a593Smuzhiyun {
1656*4882a593Smuzhiyun int i, ret;
1657*4882a593Smuzhiyun
1658*4882a593Smuzhiyun /* Enable erase */
1659*4882a593Smuzhiyun if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN_, 0 ))!=0)
1660*4882a593Smuzhiyun return ret;
1661*4882a593Smuzhiyun for(i=eeprom->offset;i<(eeprom->offset+eeprom->len);i++) {
1662*4882a593Smuzhiyun /* erase byte */
1663*4882a593Smuzhiyun if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE_, i ))!=0)
1664*4882a593Smuzhiyun return ret;
1665*4882a593Smuzhiyun /* write byte */
1666*4882a593Smuzhiyun if ((ret=smc911x_ethtool_write_eeprom_byte(dev, *data))!=0)
1667*4882a593Smuzhiyun return ret;
1668*4882a593Smuzhiyun if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE_, i ))!=0)
1669*4882a593Smuzhiyun return ret;
1670*4882a593Smuzhiyun }
1671*4882a593Smuzhiyun return 0;
1672*4882a593Smuzhiyun }
1673*4882a593Smuzhiyun
smc911x_ethtool_geteeprom_len(struct net_device * dev)1674*4882a593Smuzhiyun static int smc911x_ethtool_geteeprom_len(struct net_device *dev)
1675*4882a593Smuzhiyun {
1676*4882a593Smuzhiyun return SMC911X_EEPROM_LEN;
1677*4882a593Smuzhiyun }
1678*4882a593Smuzhiyun
1679*4882a593Smuzhiyun static const struct ethtool_ops smc911x_ethtool_ops = {
1680*4882a593Smuzhiyun .get_drvinfo = smc911x_ethtool_getdrvinfo,
1681*4882a593Smuzhiyun .get_msglevel = smc911x_ethtool_getmsglevel,
1682*4882a593Smuzhiyun .set_msglevel = smc911x_ethtool_setmsglevel,
1683*4882a593Smuzhiyun .nway_reset = smc911x_ethtool_nwayreset,
1684*4882a593Smuzhiyun .get_link = ethtool_op_get_link,
1685*4882a593Smuzhiyun .get_regs_len = smc911x_ethtool_getregslen,
1686*4882a593Smuzhiyun .get_regs = smc911x_ethtool_getregs,
1687*4882a593Smuzhiyun .get_eeprom_len = smc911x_ethtool_geteeprom_len,
1688*4882a593Smuzhiyun .get_eeprom = smc911x_ethtool_geteeprom,
1689*4882a593Smuzhiyun .set_eeprom = smc911x_ethtool_seteeprom,
1690*4882a593Smuzhiyun .get_link_ksettings = smc911x_ethtool_get_link_ksettings,
1691*4882a593Smuzhiyun .set_link_ksettings = smc911x_ethtool_set_link_ksettings,
1692*4882a593Smuzhiyun };
1693*4882a593Smuzhiyun
1694*4882a593Smuzhiyun /*
1695*4882a593Smuzhiyun * smc911x_findirq
1696*4882a593Smuzhiyun *
1697*4882a593Smuzhiyun * This routine has a simple purpose -- make the SMC chip generate an
1698*4882a593Smuzhiyun * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1699*4882a593Smuzhiyun */
smc911x_findirq(struct net_device * dev)1700*4882a593Smuzhiyun static int smc911x_findirq(struct net_device *dev)
1701*4882a593Smuzhiyun {
1702*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1703*4882a593Smuzhiyun int timeout = 20;
1704*4882a593Smuzhiyun unsigned long cookie;
1705*4882a593Smuzhiyun
1706*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1707*4882a593Smuzhiyun
1708*4882a593Smuzhiyun cookie = probe_irq_on();
1709*4882a593Smuzhiyun
1710*4882a593Smuzhiyun /*
1711*4882a593Smuzhiyun * Force a SW interrupt
1712*4882a593Smuzhiyun */
1713*4882a593Smuzhiyun
1714*4882a593Smuzhiyun SMC_SET_INT_EN(lp, INT_EN_SW_INT_EN_);
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun /*
1717*4882a593Smuzhiyun * Wait until positive that the interrupt has been generated
1718*4882a593Smuzhiyun */
1719*4882a593Smuzhiyun do {
1720*4882a593Smuzhiyun int int_status;
1721*4882a593Smuzhiyun udelay(10);
1722*4882a593Smuzhiyun int_status = SMC_GET_INT_EN(lp);
1723*4882a593Smuzhiyun if (int_status & INT_EN_SW_INT_EN_)
1724*4882a593Smuzhiyun break; /* got the interrupt */
1725*4882a593Smuzhiyun } while (--timeout);
1726*4882a593Smuzhiyun
1727*4882a593Smuzhiyun /*
1728*4882a593Smuzhiyun * there is really nothing that I can do here if timeout fails,
1729*4882a593Smuzhiyun * as autoirq_report will return a 0 anyway, which is what I
1730*4882a593Smuzhiyun * want in this case. Plus, the clean up is needed in both
1731*4882a593Smuzhiyun * cases.
1732*4882a593Smuzhiyun */
1733*4882a593Smuzhiyun
1734*4882a593Smuzhiyun /* and disable all interrupts again */
1735*4882a593Smuzhiyun SMC_SET_INT_EN(lp, 0);
1736*4882a593Smuzhiyun
1737*4882a593Smuzhiyun /* and return what I found */
1738*4882a593Smuzhiyun return probe_irq_off(cookie);
1739*4882a593Smuzhiyun }
1740*4882a593Smuzhiyun
1741*4882a593Smuzhiyun static const struct net_device_ops smc911x_netdev_ops = {
1742*4882a593Smuzhiyun .ndo_open = smc911x_open,
1743*4882a593Smuzhiyun .ndo_stop = smc911x_close,
1744*4882a593Smuzhiyun .ndo_start_xmit = smc911x_hard_start_xmit,
1745*4882a593Smuzhiyun .ndo_tx_timeout = smc911x_timeout,
1746*4882a593Smuzhiyun .ndo_set_rx_mode = smc911x_set_multicast_list,
1747*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
1748*4882a593Smuzhiyun .ndo_set_mac_address = eth_mac_addr,
1749*4882a593Smuzhiyun #ifdef CONFIG_NET_POLL_CONTROLLER
1750*4882a593Smuzhiyun .ndo_poll_controller = smc911x_poll_controller,
1751*4882a593Smuzhiyun #endif
1752*4882a593Smuzhiyun };
1753*4882a593Smuzhiyun
1754*4882a593Smuzhiyun /*
1755*4882a593Smuzhiyun * Function: smc911x_probe(unsigned long ioaddr)
1756*4882a593Smuzhiyun *
1757*4882a593Smuzhiyun * Purpose:
1758*4882a593Smuzhiyun * Tests to see if a given ioaddr points to an SMC911x chip.
1759*4882a593Smuzhiyun * Returns a 0 on success
1760*4882a593Smuzhiyun *
1761*4882a593Smuzhiyun * Algorithm:
1762*4882a593Smuzhiyun * (1) see if the endian word is OK
1763*4882a593Smuzhiyun * (1) see if I recognize the chip ID in the appropriate register
1764*4882a593Smuzhiyun *
1765*4882a593Smuzhiyun * Here I do typical initialization tasks.
1766*4882a593Smuzhiyun *
1767*4882a593Smuzhiyun * o Initialize the structure if needed
1768*4882a593Smuzhiyun * o print out my vanity message if not done so already
1769*4882a593Smuzhiyun * o print out what type of hardware is detected
1770*4882a593Smuzhiyun * o print out the ethernet address
1771*4882a593Smuzhiyun * o find the IRQ
1772*4882a593Smuzhiyun * o set up my private data
1773*4882a593Smuzhiyun * o configure the dev structure with my subroutines
1774*4882a593Smuzhiyun * o actually GRAB the irq.
1775*4882a593Smuzhiyun * o GRAB the region
1776*4882a593Smuzhiyun */
smc911x_probe(struct net_device * dev)1777*4882a593Smuzhiyun static int smc911x_probe(struct net_device *dev)
1778*4882a593Smuzhiyun {
1779*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(dev);
1780*4882a593Smuzhiyun int i, retval;
1781*4882a593Smuzhiyun unsigned int val, chip_id, revision;
1782*4882a593Smuzhiyun const char *version_string;
1783*4882a593Smuzhiyun unsigned long irq_flags;
1784*4882a593Smuzhiyun #ifdef SMC_USE_DMA
1785*4882a593Smuzhiyun struct dma_slave_config config;
1786*4882a593Smuzhiyun dma_cap_mask_t mask;
1787*4882a593Smuzhiyun #endif
1788*4882a593Smuzhiyun
1789*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1790*4882a593Smuzhiyun
1791*4882a593Smuzhiyun /* First, see if the endian word is recognized */
1792*4882a593Smuzhiyun val = SMC_GET_BYTE_TEST(lp);
1793*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "%s: endian probe returned 0x%04x\n",
1794*4882a593Smuzhiyun CARDNAME, val);
1795*4882a593Smuzhiyun if (val != 0x87654321) {
1796*4882a593Smuzhiyun netdev_err(dev, "Invalid chip endian 0x%08x\n", val);
1797*4882a593Smuzhiyun retval = -ENODEV;
1798*4882a593Smuzhiyun goto err_out;
1799*4882a593Smuzhiyun }
1800*4882a593Smuzhiyun
1801*4882a593Smuzhiyun /*
1802*4882a593Smuzhiyun * check if the revision register is something that I
1803*4882a593Smuzhiyun * recognize. These might need to be added to later,
1804*4882a593Smuzhiyun * as future revisions could be added.
1805*4882a593Smuzhiyun */
1806*4882a593Smuzhiyun chip_id = SMC_GET_PN(lp);
1807*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "%s: id probe returned 0x%04x\n",
1808*4882a593Smuzhiyun CARDNAME, chip_id);
1809*4882a593Smuzhiyun for(i=0;chip_ids[i].id != 0; i++) {
1810*4882a593Smuzhiyun if (chip_ids[i].id == chip_id) break;
1811*4882a593Smuzhiyun }
1812*4882a593Smuzhiyun if (!chip_ids[i].id) {
1813*4882a593Smuzhiyun netdev_err(dev, "Unknown chip ID %04x\n", chip_id);
1814*4882a593Smuzhiyun retval = -ENODEV;
1815*4882a593Smuzhiyun goto err_out;
1816*4882a593Smuzhiyun }
1817*4882a593Smuzhiyun version_string = chip_ids[i].name;
1818*4882a593Smuzhiyun
1819*4882a593Smuzhiyun revision = SMC_GET_REV(lp);
1820*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "%s: revision = 0x%04x\n", CARDNAME, revision);
1821*4882a593Smuzhiyun
1822*4882a593Smuzhiyun /* At this point I'll assume that the chip is an SMC911x. */
1823*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC, dev, "%s: Found a %s\n",
1824*4882a593Smuzhiyun CARDNAME, chip_ids[i].name);
1825*4882a593Smuzhiyun
1826*4882a593Smuzhiyun /* Validate the TX FIFO size requested */
1827*4882a593Smuzhiyun if ((tx_fifo_kb < 2) || (tx_fifo_kb > 14)) {
1828*4882a593Smuzhiyun netdev_err(dev, "Invalid TX FIFO size requested %d\n",
1829*4882a593Smuzhiyun tx_fifo_kb);
1830*4882a593Smuzhiyun retval = -EINVAL;
1831*4882a593Smuzhiyun goto err_out;
1832*4882a593Smuzhiyun }
1833*4882a593Smuzhiyun
1834*4882a593Smuzhiyun /* fill in some of the fields */
1835*4882a593Smuzhiyun lp->version = chip_ids[i].id;
1836*4882a593Smuzhiyun lp->revision = revision;
1837*4882a593Smuzhiyun lp->tx_fifo_kb = tx_fifo_kb;
1838*4882a593Smuzhiyun /* Reverse calculate the RX FIFO size from the TX */
1839*4882a593Smuzhiyun lp->tx_fifo_size=(lp->tx_fifo_kb<<10) - 512;
1840*4882a593Smuzhiyun lp->rx_fifo_size= ((0x4000 - 512 - lp->tx_fifo_size) / 16) * 15;
1841*4882a593Smuzhiyun
1842*4882a593Smuzhiyun /* Set the automatic flow control values */
1843*4882a593Smuzhiyun switch(lp->tx_fifo_kb) {
1844*4882a593Smuzhiyun /*
1845*4882a593Smuzhiyun * AFC_HI is about ((Rx Data Fifo Size)*2/3)/64
1846*4882a593Smuzhiyun * AFC_LO is AFC_HI/2
1847*4882a593Smuzhiyun * BACK_DUR is about 5uS*(AFC_LO) rounded down
1848*4882a593Smuzhiyun */
1849*4882a593Smuzhiyun case 2:/* 13440 Rx Data Fifo Size */
1850*4882a593Smuzhiyun lp->afc_cfg=0x008C46AF;break;
1851*4882a593Smuzhiyun case 3:/* 12480 Rx Data Fifo Size */
1852*4882a593Smuzhiyun lp->afc_cfg=0x0082419F;break;
1853*4882a593Smuzhiyun case 4:/* 11520 Rx Data Fifo Size */
1854*4882a593Smuzhiyun lp->afc_cfg=0x00783C9F;break;
1855*4882a593Smuzhiyun case 5:/* 10560 Rx Data Fifo Size */
1856*4882a593Smuzhiyun lp->afc_cfg=0x006E374F;break;
1857*4882a593Smuzhiyun case 6:/* 9600 Rx Data Fifo Size */
1858*4882a593Smuzhiyun lp->afc_cfg=0x0064328F;break;
1859*4882a593Smuzhiyun case 7:/* 8640 Rx Data Fifo Size */
1860*4882a593Smuzhiyun lp->afc_cfg=0x005A2D7F;break;
1861*4882a593Smuzhiyun case 8:/* 7680 Rx Data Fifo Size */
1862*4882a593Smuzhiyun lp->afc_cfg=0x0050287F;break;
1863*4882a593Smuzhiyun case 9:/* 6720 Rx Data Fifo Size */
1864*4882a593Smuzhiyun lp->afc_cfg=0x0046236F;break;
1865*4882a593Smuzhiyun case 10:/* 5760 Rx Data Fifo Size */
1866*4882a593Smuzhiyun lp->afc_cfg=0x003C1E6F;break;
1867*4882a593Smuzhiyun case 11:/* 4800 Rx Data Fifo Size */
1868*4882a593Smuzhiyun lp->afc_cfg=0x0032195F;break;
1869*4882a593Smuzhiyun /*
1870*4882a593Smuzhiyun * AFC_HI is ~1520 bytes less than RX Data Fifo Size
1871*4882a593Smuzhiyun * AFC_LO is AFC_HI/2
1872*4882a593Smuzhiyun * BACK_DUR is about 5uS*(AFC_LO) rounded down
1873*4882a593Smuzhiyun */
1874*4882a593Smuzhiyun case 12:/* 3840 Rx Data Fifo Size */
1875*4882a593Smuzhiyun lp->afc_cfg=0x0024124F;break;
1876*4882a593Smuzhiyun case 13:/* 2880 Rx Data Fifo Size */
1877*4882a593Smuzhiyun lp->afc_cfg=0x0015073F;break;
1878*4882a593Smuzhiyun case 14:/* 1920 Rx Data Fifo Size */
1879*4882a593Smuzhiyun lp->afc_cfg=0x0006032F;break;
1880*4882a593Smuzhiyun default:
1881*4882a593Smuzhiyun PRINTK(dev, "ERROR -- no AFC_CFG setting found");
1882*4882a593Smuzhiyun break;
1883*4882a593Smuzhiyun }
1884*4882a593Smuzhiyun
1885*4882a593Smuzhiyun DBG(SMC_DEBUG_MISC | SMC_DEBUG_TX | SMC_DEBUG_RX, dev,
1886*4882a593Smuzhiyun "%s: tx_fifo %d rx_fifo %d afc_cfg 0x%08x\n", CARDNAME,
1887*4882a593Smuzhiyun lp->tx_fifo_size, lp->rx_fifo_size, lp->afc_cfg);
1888*4882a593Smuzhiyun
1889*4882a593Smuzhiyun spin_lock_init(&lp->lock);
1890*4882a593Smuzhiyun
1891*4882a593Smuzhiyun /* Get the MAC address */
1892*4882a593Smuzhiyun SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun /* now, reset the chip, and put it into a known state */
1895*4882a593Smuzhiyun smc911x_reset(dev);
1896*4882a593Smuzhiyun
1897*4882a593Smuzhiyun /*
1898*4882a593Smuzhiyun * If dev->irq is 0, then the device has to be banged on to see
1899*4882a593Smuzhiyun * what the IRQ is.
1900*4882a593Smuzhiyun *
1901*4882a593Smuzhiyun * Specifying an IRQ is done with the assumption that the user knows
1902*4882a593Smuzhiyun * what (s)he is doing. No checking is done!!!!
1903*4882a593Smuzhiyun */
1904*4882a593Smuzhiyun if (dev->irq < 1) {
1905*4882a593Smuzhiyun int trials;
1906*4882a593Smuzhiyun
1907*4882a593Smuzhiyun trials = 3;
1908*4882a593Smuzhiyun while (trials--) {
1909*4882a593Smuzhiyun dev->irq = smc911x_findirq(dev);
1910*4882a593Smuzhiyun if (dev->irq)
1911*4882a593Smuzhiyun break;
1912*4882a593Smuzhiyun /* kick the card and try again */
1913*4882a593Smuzhiyun smc911x_reset(dev);
1914*4882a593Smuzhiyun }
1915*4882a593Smuzhiyun }
1916*4882a593Smuzhiyun if (dev->irq == 0) {
1917*4882a593Smuzhiyun netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n");
1918*4882a593Smuzhiyun retval = -ENODEV;
1919*4882a593Smuzhiyun goto err_out;
1920*4882a593Smuzhiyun }
1921*4882a593Smuzhiyun dev->irq = irq_canonicalize(dev->irq);
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun dev->netdev_ops = &smc911x_netdev_ops;
1924*4882a593Smuzhiyun dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1925*4882a593Smuzhiyun dev->ethtool_ops = &smc911x_ethtool_ops;
1926*4882a593Smuzhiyun
1927*4882a593Smuzhiyun INIT_WORK(&lp->phy_configure, smc911x_phy_configure);
1928*4882a593Smuzhiyun lp->mii.phy_id_mask = 0x1f;
1929*4882a593Smuzhiyun lp->mii.reg_num_mask = 0x1f;
1930*4882a593Smuzhiyun lp->mii.force_media = 0;
1931*4882a593Smuzhiyun lp->mii.full_duplex = 0;
1932*4882a593Smuzhiyun lp->mii.dev = dev;
1933*4882a593Smuzhiyun lp->mii.mdio_read = smc911x_phy_read;
1934*4882a593Smuzhiyun lp->mii.mdio_write = smc911x_phy_write;
1935*4882a593Smuzhiyun
1936*4882a593Smuzhiyun /*
1937*4882a593Smuzhiyun * Locate the phy, if any.
1938*4882a593Smuzhiyun */
1939*4882a593Smuzhiyun smc911x_phy_detect(dev);
1940*4882a593Smuzhiyun
1941*4882a593Smuzhiyun /* Set default parameters */
1942*4882a593Smuzhiyun lp->msg_enable = NETIF_MSG_LINK;
1943*4882a593Smuzhiyun lp->ctl_rfduplx = 1;
1944*4882a593Smuzhiyun lp->ctl_rspeed = 100;
1945*4882a593Smuzhiyun
1946*4882a593Smuzhiyun #ifdef SMC_DYNAMIC_BUS_CONFIG
1947*4882a593Smuzhiyun irq_flags = lp->cfg.irq_flags;
1948*4882a593Smuzhiyun #else
1949*4882a593Smuzhiyun irq_flags = IRQF_SHARED | SMC_IRQ_SENSE;
1950*4882a593Smuzhiyun #endif
1951*4882a593Smuzhiyun
1952*4882a593Smuzhiyun /* Grab the IRQ */
1953*4882a593Smuzhiyun retval = request_irq(dev->irq, smc911x_interrupt,
1954*4882a593Smuzhiyun irq_flags, dev->name, dev);
1955*4882a593Smuzhiyun if (retval)
1956*4882a593Smuzhiyun goto err_out;
1957*4882a593Smuzhiyun
1958*4882a593Smuzhiyun #ifdef SMC_USE_DMA
1959*4882a593Smuzhiyun
1960*4882a593Smuzhiyun dma_cap_zero(mask);
1961*4882a593Smuzhiyun dma_cap_set(DMA_SLAVE, mask);
1962*4882a593Smuzhiyun lp->rxdma = dma_request_channel(mask, NULL, NULL);
1963*4882a593Smuzhiyun lp->txdma = dma_request_channel(mask, NULL, NULL);
1964*4882a593Smuzhiyun lp->rxdma_active = 0;
1965*4882a593Smuzhiyun lp->txdma_active = 0;
1966*4882a593Smuzhiyun
1967*4882a593Smuzhiyun memset(&config, 0, sizeof(config));
1968*4882a593Smuzhiyun config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1969*4882a593Smuzhiyun config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1970*4882a593Smuzhiyun config.src_addr = lp->physaddr + RX_DATA_FIFO;
1971*4882a593Smuzhiyun config.dst_addr = lp->physaddr + TX_DATA_FIFO;
1972*4882a593Smuzhiyun config.src_maxburst = 32;
1973*4882a593Smuzhiyun config.dst_maxburst = 32;
1974*4882a593Smuzhiyun retval = dmaengine_slave_config(lp->rxdma, &config);
1975*4882a593Smuzhiyun if (retval) {
1976*4882a593Smuzhiyun dev_err(lp->dev, "dma rx channel configuration failed: %d\n",
1977*4882a593Smuzhiyun retval);
1978*4882a593Smuzhiyun goto err_out;
1979*4882a593Smuzhiyun }
1980*4882a593Smuzhiyun retval = dmaengine_slave_config(lp->txdma, &config);
1981*4882a593Smuzhiyun if (retval) {
1982*4882a593Smuzhiyun dev_err(lp->dev, "dma tx channel configuration failed: %d\n",
1983*4882a593Smuzhiyun retval);
1984*4882a593Smuzhiyun goto err_out;
1985*4882a593Smuzhiyun }
1986*4882a593Smuzhiyun #endif
1987*4882a593Smuzhiyun
1988*4882a593Smuzhiyun retval = register_netdev(dev);
1989*4882a593Smuzhiyun if (retval == 0) {
1990*4882a593Smuzhiyun /* now, print out the card info, in a short format.. */
1991*4882a593Smuzhiyun netdev_info(dev, "%s (rev %d) at %#lx IRQ %d",
1992*4882a593Smuzhiyun version_string, lp->revision,
1993*4882a593Smuzhiyun dev->base_addr, dev->irq);
1994*4882a593Smuzhiyun
1995*4882a593Smuzhiyun #ifdef SMC_USE_DMA
1996*4882a593Smuzhiyun if (lp->rxdma)
1997*4882a593Smuzhiyun pr_cont(" RXDMA %p", lp->rxdma);
1998*4882a593Smuzhiyun
1999*4882a593Smuzhiyun if (lp->txdma)
2000*4882a593Smuzhiyun pr_cont(" TXDMA %p", lp->txdma);
2001*4882a593Smuzhiyun #endif
2002*4882a593Smuzhiyun pr_cont("\n");
2003*4882a593Smuzhiyun if (!is_valid_ether_addr(dev->dev_addr)) {
2004*4882a593Smuzhiyun netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n");
2005*4882a593Smuzhiyun } else {
2006*4882a593Smuzhiyun /* Print the Ethernet address */
2007*4882a593Smuzhiyun netdev_info(dev, "Ethernet addr: %pM\n",
2008*4882a593Smuzhiyun dev->dev_addr);
2009*4882a593Smuzhiyun }
2010*4882a593Smuzhiyun
2011*4882a593Smuzhiyun if (lp->phy_type == 0) {
2012*4882a593Smuzhiyun PRINTK(dev, "No PHY found\n");
2013*4882a593Smuzhiyun } else if ((lp->phy_type & ~0xff) == LAN911X_INTERNAL_PHY_ID) {
2014*4882a593Smuzhiyun PRINTK(dev, "LAN911x Internal PHY\n");
2015*4882a593Smuzhiyun } else {
2016*4882a593Smuzhiyun PRINTK(dev, "External PHY 0x%08x\n", lp->phy_type);
2017*4882a593Smuzhiyun }
2018*4882a593Smuzhiyun }
2019*4882a593Smuzhiyun
2020*4882a593Smuzhiyun err_out:
2021*4882a593Smuzhiyun #ifdef SMC_USE_DMA
2022*4882a593Smuzhiyun if (retval) {
2023*4882a593Smuzhiyun if (lp->rxdma)
2024*4882a593Smuzhiyun dma_release_channel(lp->rxdma);
2025*4882a593Smuzhiyun if (lp->txdma)
2026*4882a593Smuzhiyun dma_release_channel(lp->txdma);
2027*4882a593Smuzhiyun }
2028*4882a593Smuzhiyun #endif
2029*4882a593Smuzhiyun return retval;
2030*4882a593Smuzhiyun }
2031*4882a593Smuzhiyun
2032*4882a593Smuzhiyun /*
2033*4882a593Smuzhiyun * smc911x_drv_probe(void)
2034*4882a593Smuzhiyun *
2035*4882a593Smuzhiyun * Output:
2036*4882a593Smuzhiyun * 0 --> there is a device
2037*4882a593Smuzhiyun * anything else, error
2038*4882a593Smuzhiyun */
smc911x_drv_probe(struct platform_device * pdev)2039*4882a593Smuzhiyun static int smc911x_drv_probe(struct platform_device *pdev)
2040*4882a593Smuzhiyun {
2041*4882a593Smuzhiyun struct net_device *ndev;
2042*4882a593Smuzhiyun struct resource *res;
2043*4882a593Smuzhiyun struct smc911x_local *lp;
2044*4882a593Smuzhiyun void __iomem *addr;
2045*4882a593Smuzhiyun int ret;
2046*4882a593Smuzhiyun
2047*4882a593Smuzhiyun /* ndev is not valid yet, so avoid passing it in. */
2048*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
2049*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2050*4882a593Smuzhiyun if (!res) {
2051*4882a593Smuzhiyun ret = -ENODEV;
2052*4882a593Smuzhiyun goto out;
2053*4882a593Smuzhiyun }
2054*4882a593Smuzhiyun
2055*4882a593Smuzhiyun /*
2056*4882a593Smuzhiyun * Request the regions.
2057*4882a593Smuzhiyun */
2058*4882a593Smuzhiyun if (!request_mem_region(res->start, SMC911X_IO_EXTENT, CARDNAME)) {
2059*4882a593Smuzhiyun ret = -EBUSY;
2060*4882a593Smuzhiyun goto out;
2061*4882a593Smuzhiyun }
2062*4882a593Smuzhiyun
2063*4882a593Smuzhiyun ndev = alloc_etherdev(sizeof(struct smc911x_local));
2064*4882a593Smuzhiyun if (!ndev) {
2065*4882a593Smuzhiyun ret = -ENOMEM;
2066*4882a593Smuzhiyun goto release_1;
2067*4882a593Smuzhiyun }
2068*4882a593Smuzhiyun SET_NETDEV_DEV(ndev, &pdev->dev);
2069*4882a593Smuzhiyun
2070*4882a593Smuzhiyun ndev->dma = (unsigned char)-1;
2071*4882a593Smuzhiyun ndev->irq = platform_get_irq(pdev, 0);
2072*4882a593Smuzhiyun if (ndev->irq < 0) {
2073*4882a593Smuzhiyun ret = ndev->irq;
2074*4882a593Smuzhiyun goto release_both;
2075*4882a593Smuzhiyun }
2076*4882a593Smuzhiyun
2077*4882a593Smuzhiyun lp = netdev_priv(ndev);
2078*4882a593Smuzhiyun lp->netdev = ndev;
2079*4882a593Smuzhiyun #ifdef SMC_DYNAMIC_BUS_CONFIG
2080*4882a593Smuzhiyun {
2081*4882a593Smuzhiyun struct smc911x_platdata *pd = dev_get_platdata(&pdev->dev);
2082*4882a593Smuzhiyun if (!pd) {
2083*4882a593Smuzhiyun ret = -EINVAL;
2084*4882a593Smuzhiyun goto release_both;
2085*4882a593Smuzhiyun }
2086*4882a593Smuzhiyun memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2087*4882a593Smuzhiyun }
2088*4882a593Smuzhiyun #endif
2089*4882a593Smuzhiyun
2090*4882a593Smuzhiyun addr = ioremap(res->start, SMC911X_IO_EXTENT);
2091*4882a593Smuzhiyun if (!addr) {
2092*4882a593Smuzhiyun ret = -ENOMEM;
2093*4882a593Smuzhiyun goto release_both;
2094*4882a593Smuzhiyun }
2095*4882a593Smuzhiyun
2096*4882a593Smuzhiyun platform_set_drvdata(pdev, ndev);
2097*4882a593Smuzhiyun lp->base = addr;
2098*4882a593Smuzhiyun ndev->base_addr = res->start;
2099*4882a593Smuzhiyun ret = smc911x_probe(ndev);
2100*4882a593Smuzhiyun if (ret != 0) {
2101*4882a593Smuzhiyun iounmap(addr);
2102*4882a593Smuzhiyun release_both:
2103*4882a593Smuzhiyun free_netdev(ndev);
2104*4882a593Smuzhiyun release_1:
2105*4882a593Smuzhiyun release_mem_region(res->start, SMC911X_IO_EXTENT);
2106*4882a593Smuzhiyun out:
2107*4882a593Smuzhiyun pr_info("%s: not found (%d).\n", CARDNAME, ret);
2108*4882a593Smuzhiyun }
2109*4882a593Smuzhiyun #ifdef SMC_USE_DMA
2110*4882a593Smuzhiyun else {
2111*4882a593Smuzhiyun lp->physaddr = res->start;
2112*4882a593Smuzhiyun lp->dev = &pdev->dev;
2113*4882a593Smuzhiyun }
2114*4882a593Smuzhiyun #endif
2115*4882a593Smuzhiyun
2116*4882a593Smuzhiyun return ret;
2117*4882a593Smuzhiyun }
2118*4882a593Smuzhiyun
smc911x_drv_remove(struct platform_device * pdev)2119*4882a593Smuzhiyun static int smc911x_drv_remove(struct platform_device *pdev)
2120*4882a593Smuzhiyun {
2121*4882a593Smuzhiyun struct net_device *ndev = platform_get_drvdata(pdev);
2122*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(ndev);
2123*4882a593Smuzhiyun struct resource *res;
2124*4882a593Smuzhiyun
2125*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, ndev, "--> %s\n", __func__);
2126*4882a593Smuzhiyun
2127*4882a593Smuzhiyun unregister_netdev(ndev);
2128*4882a593Smuzhiyun
2129*4882a593Smuzhiyun free_irq(ndev->irq, ndev);
2130*4882a593Smuzhiyun
2131*4882a593Smuzhiyun #ifdef SMC_USE_DMA
2132*4882a593Smuzhiyun {
2133*4882a593Smuzhiyun if (lp->rxdma)
2134*4882a593Smuzhiyun dma_release_channel(lp->rxdma);
2135*4882a593Smuzhiyun if (lp->txdma)
2136*4882a593Smuzhiyun dma_release_channel(lp->txdma);
2137*4882a593Smuzhiyun }
2138*4882a593Smuzhiyun #endif
2139*4882a593Smuzhiyun iounmap(lp->base);
2140*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2141*4882a593Smuzhiyun release_mem_region(res->start, SMC911X_IO_EXTENT);
2142*4882a593Smuzhiyun
2143*4882a593Smuzhiyun free_netdev(ndev);
2144*4882a593Smuzhiyun return 0;
2145*4882a593Smuzhiyun }
2146*4882a593Smuzhiyun
smc911x_drv_suspend(struct platform_device * dev,pm_message_t state)2147*4882a593Smuzhiyun static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
2148*4882a593Smuzhiyun {
2149*4882a593Smuzhiyun struct net_device *ndev = platform_get_drvdata(dev);
2150*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(ndev);
2151*4882a593Smuzhiyun
2152*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, ndev, "--> %s\n", __func__);
2153*4882a593Smuzhiyun if (ndev) {
2154*4882a593Smuzhiyun if (netif_running(ndev)) {
2155*4882a593Smuzhiyun netif_device_detach(ndev);
2156*4882a593Smuzhiyun smc911x_shutdown(ndev);
2157*4882a593Smuzhiyun #if POWER_DOWN
2158*4882a593Smuzhiyun /* Set D2 - Energy detect only setting */
2159*4882a593Smuzhiyun SMC_SET_PMT_CTRL(lp, 2<<12);
2160*4882a593Smuzhiyun #endif
2161*4882a593Smuzhiyun }
2162*4882a593Smuzhiyun }
2163*4882a593Smuzhiyun return 0;
2164*4882a593Smuzhiyun }
2165*4882a593Smuzhiyun
smc911x_drv_resume(struct platform_device * dev)2166*4882a593Smuzhiyun static int smc911x_drv_resume(struct platform_device *dev)
2167*4882a593Smuzhiyun {
2168*4882a593Smuzhiyun struct net_device *ndev = platform_get_drvdata(dev);
2169*4882a593Smuzhiyun
2170*4882a593Smuzhiyun DBG(SMC_DEBUG_FUNC, ndev, "--> %s\n", __func__);
2171*4882a593Smuzhiyun if (ndev) {
2172*4882a593Smuzhiyun struct smc911x_local *lp = netdev_priv(ndev);
2173*4882a593Smuzhiyun
2174*4882a593Smuzhiyun if (netif_running(ndev)) {
2175*4882a593Smuzhiyun smc911x_reset(ndev);
2176*4882a593Smuzhiyun if (lp->phy_type != 0)
2177*4882a593Smuzhiyun smc911x_phy_configure(&lp->phy_configure);
2178*4882a593Smuzhiyun smc911x_enable(ndev);
2179*4882a593Smuzhiyun netif_device_attach(ndev);
2180*4882a593Smuzhiyun }
2181*4882a593Smuzhiyun }
2182*4882a593Smuzhiyun return 0;
2183*4882a593Smuzhiyun }
2184*4882a593Smuzhiyun
2185*4882a593Smuzhiyun static struct platform_driver smc911x_driver = {
2186*4882a593Smuzhiyun .probe = smc911x_drv_probe,
2187*4882a593Smuzhiyun .remove = smc911x_drv_remove,
2188*4882a593Smuzhiyun .suspend = smc911x_drv_suspend,
2189*4882a593Smuzhiyun .resume = smc911x_drv_resume,
2190*4882a593Smuzhiyun .driver = {
2191*4882a593Smuzhiyun .name = CARDNAME,
2192*4882a593Smuzhiyun },
2193*4882a593Smuzhiyun };
2194*4882a593Smuzhiyun
2195*4882a593Smuzhiyun module_platform_driver(smc911x_driver);
2196