1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /****************************************************************************
3*4882a593Smuzhiyun * Driver for Solarflare network controllers and boards
4*4882a593Smuzhiyun * Copyright 2015 Solarflare Communications Inc.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef SIENA_SRIOV_H
8*4882a593Smuzhiyun #define SIENA_SRIOV_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "net_driver.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /* On the SFC9000 family each port is associated with 1 PCI physical
13*4882a593Smuzhiyun * function (PF) handled by sfc and a configurable number of virtual
14*4882a593Smuzhiyun * functions (VFs) that may be handled by some other driver, often in
15*4882a593Smuzhiyun * a VM guest. The queue pointer registers are mapped in both PF and
16*4882a593Smuzhiyun * VF BARs such that an 8K region provides access to a single RX, TX
17*4882a593Smuzhiyun * and event queue (collectively a Virtual Interface, VI or VNIC).
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * The PF has access to all 1024 VIs while VFs are mapped to VIs
20*4882a593Smuzhiyun * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered
21*4882a593Smuzhiyun * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE).
22*4882a593Smuzhiyun * The number of VIs and the VI_SCALE value are configurable but must
23*4882a593Smuzhiyun * be established at boot time by firmware.
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Maximum VI_SCALE parameter supported by Siena */
27*4882a593Smuzhiyun #define EFX_VI_SCALE_MAX 6
28*4882a593Smuzhiyun /* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
29*4882a593Smuzhiyun * so this is the smallest allowed value.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #define EFX_VI_BASE 128U
32*4882a593Smuzhiyun /* Maximum number of VFs allowed */
33*4882a593Smuzhiyun #define EFX_VF_COUNT_MAX 127
34*4882a593Smuzhiyun /* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */
35*4882a593Smuzhiyun #define EFX_MAX_VF_EVQ_SIZE 8192UL
36*4882a593Smuzhiyun /* The number of buffer table entries reserved for each VI on a VF */
37*4882a593Smuzhiyun #define EFX_VF_BUFTBL_PER_VI \
38*4882a593Smuzhiyun ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \
39*4882a593Smuzhiyun sizeof(efx_qword_t) / EFX_BUF_SIZE)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun int efx_siena_sriov_configure(struct efx_nic *efx, int num_vfs);
42*4882a593Smuzhiyun int efx_siena_sriov_init(struct efx_nic *efx);
43*4882a593Smuzhiyun void efx_siena_sriov_fini(struct efx_nic *efx);
44*4882a593Smuzhiyun int efx_siena_sriov_mac_address_changed(struct efx_nic *efx);
45*4882a593Smuzhiyun bool efx_siena_sriov_wanted(struct efx_nic *efx);
46*4882a593Smuzhiyun void efx_siena_sriov_reset(struct efx_nic *efx);
47*4882a593Smuzhiyun void efx_siena_sriov_flr(struct efx_nic *efx, unsigned flr);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun int efx_siena_sriov_set_vf_mac(struct efx_nic *efx, int vf, u8 *mac);
50*4882a593Smuzhiyun int efx_siena_sriov_set_vf_vlan(struct efx_nic *efx, int vf,
51*4882a593Smuzhiyun u16 vlan, u8 qos);
52*4882a593Smuzhiyun int efx_siena_sriov_set_vf_spoofchk(struct efx_nic *efx, int vf,
53*4882a593Smuzhiyun bool spoofchk);
54*4882a593Smuzhiyun int efx_siena_sriov_get_vf_config(struct efx_nic *efx, int vf,
55*4882a593Smuzhiyun struct ifla_vf_info *ivf);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #ifdef CONFIG_SFC_SRIOV
58*4882a593Smuzhiyun
efx_siena_sriov_enabled(struct efx_nic * efx)59*4882a593Smuzhiyun static inline bool efx_siena_sriov_enabled(struct efx_nic *efx)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun return efx->vf_init_count != 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun #else /* !CONFIG_SFC_SRIOV */
efx_siena_sriov_enabled(struct efx_nic * efx)64*4882a593Smuzhiyun static inline bool efx_siena_sriov_enabled(struct efx_nic *efx)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun return false;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun #endif /* CONFIG_SFC_SRIOV */
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun void efx_siena_sriov_probe(struct efx_nic *efx);
71*4882a593Smuzhiyun void efx_siena_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event);
72*4882a593Smuzhiyun void efx_siena_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event);
73*4882a593Smuzhiyun void efx_siena_sriov_event(struct efx_channel *channel, efx_qword_t *event);
74*4882a593Smuzhiyun void efx_siena_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #endif /* SIENA_SRIOV_H */
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