1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /**************************************************************************** 3*4882a593Smuzhiyun * Driver for Solarflare network controllers and boards 4*4882a593Smuzhiyun * Copyright 2007-2010 Solarflare Communications Inc. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef EF4_PHY_H 8*4882a593Smuzhiyun #define EF4_PHY_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /**************************************************************************** 11*4882a593Smuzhiyun * 10Xpress (SFX7101) PHY 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun extern const struct ef4_phy_operations falcon_sfx7101_phy_ops; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun void tenxpress_set_id_led(struct ef4_nic *efx, enum ef4_led_mode mode); 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /**************************************************************************** 18*4882a593Smuzhiyun * AMCC/Quake QT202x PHYs 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun extern const struct ef4_phy_operations falcon_qt202x_phy_ops; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* These PHYs provide various H/W control states for LEDs */ 23*4882a593Smuzhiyun #define QUAKE_LED_LINK_INVAL (0) 24*4882a593Smuzhiyun #define QUAKE_LED_LINK_STAT (1) 25*4882a593Smuzhiyun #define QUAKE_LED_LINK_ACT (2) 26*4882a593Smuzhiyun #define QUAKE_LED_LINK_ACTSTAT (3) 27*4882a593Smuzhiyun #define QUAKE_LED_OFF (4) 28*4882a593Smuzhiyun #define QUAKE_LED_ON (5) 29*4882a593Smuzhiyun #define QUAKE_LED_LINK_INPUT (6) /* Pin is an input. */ 30*4882a593Smuzhiyun /* What link the LED tracks */ 31*4882a593Smuzhiyun #define QUAKE_LED_TXLINK (0) 32*4882a593Smuzhiyun #define QUAKE_LED_RXLINK (8) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun void falcon_qt202x_set_led(struct ef4_nic *p, int led, int state); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /**************************************************************************** 37*4882a593Smuzhiyun * Transwitch CX4 retimer 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun extern const struct ef4_phy_operations falcon_txc_phy_ops; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define TXC_GPIO_DIR_INPUT 0 42*4882a593Smuzhiyun #define TXC_GPIO_DIR_OUTPUT 1 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun void falcon_txc_set_gpio_dir(struct ef4_nic *efx, int pin, int dir); 45*4882a593Smuzhiyun void falcon_txc_set_gpio_val(struct ef4_nic *efx, int pin, int val); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif 48