1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /****************************************************************************
3*4882a593Smuzhiyun * Driver for Solarflare network controllers and boards
4*4882a593Smuzhiyun * Copyright 2006-2011 Solarflare Communications Inc.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef EF4_MDIO_10G_H
8*4882a593Smuzhiyun #define EF4_MDIO_10G_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/mdio.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun * Helper functions for doing 10G MDIO as specified in IEEE 802.3 clause 45.
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "efx.h"
17*4882a593Smuzhiyun
ef4_mdio_id_rev(u32 id)18*4882a593Smuzhiyun static inline unsigned ef4_mdio_id_rev(u32 id) { return id & 0xf; }
ef4_mdio_id_model(u32 id)19*4882a593Smuzhiyun static inline unsigned ef4_mdio_id_model(u32 id) { return (id >> 4) & 0x3f; }
20*4882a593Smuzhiyun unsigned ef4_mdio_id_oui(u32 id);
21*4882a593Smuzhiyun
ef4_mdio_read(struct ef4_nic * efx,int devad,int addr)22*4882a593Smuzhiyun static inline int ef4_mdio_read(struct ef4_nic *efx, int devad, int addr)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun return efx->mdio.mdio_read(efx->net_dev, efx->mdio.prtad, devad, addr);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static inline void
ef4_mdio_write(struct ef4_nic * efx,int devad,int addr,int value)28*4882a593Smuzhiyun ef4_mdio_write(struct ef4_nic *efx, int devad, int addr, int value)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun efx->mdio.mdio_write(efx->net_dev, efx->mdio.prtad, devad, addr, value);
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
ef4_mdio_read_id(struct ef4_nic * efx,int mmd)33*4882a593Smuzhiyun static inline u32 ef4_mdio_read_id(struct ef4_nic *efx, int mmd)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun u16 id_low = ef4_mdio_read(efx, mmd, MDIO_DEVID2);
36*4882a593Smuzhiyun u16 id_hi = ef4_mdio_read(efx, mmd, MDIO_DEVID1);
37*4882a593Smuzhiyun return (id_hi << 16) | (id_low);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
ef4_mdio_phyxgxs_lane_sync(struct ef4_nic * efx)40*4882a593Smuzhiyun static inline bool ef4_mdio_phyxgxs_lane_sync(struct ef4_nic *efx)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun int i, lane_status;
43*4882a593Smuzhiyun bool sync;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun for (i = 0; i < 2; ++i)
46*4882a593Smuzhiyun lane_status = ef4_mdio_read(efx, MDIO_MMD_PHYXS,
47*4882a593Smuzhiyun MDIO_PHYXS_LNSTAT);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun sync = !!(lane_status & MDIO_PHYXS_LNSTAT_ALIGN);
50*4882a593Smuzhiyun if (!sync)
51*4882a593Smuzhiyun netif_dbg(efx, hw, efx->net_dev, "XGXS lane status: %x\n",
52*4882a593Smuzhiyun lane_status);
53*4882a593Smuzhiyun return sync;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun const char *ef4_mdio_mmd_name(int mmd);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * Reset a specific MMD and wait for reset to clear.
60*4882a593Smuzhiyun * Return number of spins left (>0) on success, -%ETIMEDOUT on failure.
61*4882a593Smuzhiyun *
62*4882a593Smuzhiyun * This function will sleep
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun int ef4_mdio_reset_mmd(struct ef4_nic *efx, int mmd, int spins, int spintime);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* As ef4_mdio_check_mmd but for multiple MMDs */
67*4882a593Smuzhiyun int ef4_mdio_check_mmds(struct ef4_nic *efx, unsigned int mmd_mask);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Check the link status of specified mmds in bit mask */
70*4882a593Smuzhiyun bool ef4_mdio_links_ok(struct ef4_nic *efx, unsigned int mmd_mask);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Generic transmit disable support though PMAPMD */
73*4882a593Smuzhiyun void ef4_mdio_transmit_disable(struct ef4_nic *efx);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Generic part of reconfigure: set/clear loopback bits */
76*4882a593Smuzhiyun void ef4_mdio_phy_reconfigure(struct ef4_nic *efx);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Set the power state of the specified MMDs */
79*4882a593Smuzhiyun void ef4_mdio_set_mmds_lpower(struct ef4_nic *efx, int low_power,
80*4882a593Smuzhiyun unsigned int mmd_mask);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Set (some of) the PHY settings over MDIO */
83*4882a593Smuzhiyun int ef4_mdio_set_link_ksettings(struct ef4_nic *efx,
84*4882a593Smuzhiyun const struct ethtool_link_ksettings *cmd);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* Push advertising flags and restart autonegotiation */
87*4882a593Smuzhiyun void ef4_mdio_an_reconfigure(struct ef4_nic *efx);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Get pause parameters from AN if available (otherwise return
90*4882a593Smuzhiyun * requested pause parameters)
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun u8 ef4_mdio_get_pause(struct ef4_nic *efx);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Wait for specified MMDs to exit reset within a timeout */
95*4882a593Smuzhiyun int ef4_mdio_wait_reset_mmds(struct ef4_nic *efx, unsigned int mmd_mask);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Set or clear flag, debouncing */
98*4882a593Smuzhiyun static inline void
ef4_mdio_set_flag(struct ef4_nic * efx,int devad,int addr,int mask,bool state)99*4882a593Smuzhiyun ef4_mdio_set_flag(struct ef4_nic *efx, int devad, int addr,
100*4882a593Smuzhiyun int mask, bool state)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun mdio_set_flag(&efx->mdio, efx->mdio.prtad, devad, addr, mask, state);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Liveness self-test for MDIO PHYs */
106*4882a593Smuzhiyun int ef4_mdio_test_alive(struct ef4_nic *efx);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #endif /* EF4_MDIO_10G_H */
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