1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 10G controller driver for Samsung SoCs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5*4882a593Smuzhiyun * http://www.samsung.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Siva Reddy Kallam <siva.kallam@samsung.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __SXGBE_MTL_H__ 10*4882a593Smuzhiyun #define __SXGBE_MTL_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define SXGBE_MTL_OPMODE_ESTMASK 0x3 13*4882a593Smuzhiyun #define SXGBE_MTL_OPMODE_RAAMASK 0x1 14*4882a593Smuzhiyun #define SXGBE_MTL_FCMASK 0x7 15*4882a593Smuzhiyun #define SXGBE_MTL_TX_FIFO_DIV 256 16*4882a593Smuzhiyun #define SXGBE_MTL_RX_FIFO_DIV 256 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define SXGBE_MTL_RXQ_OP_FEP BIT(4) 19*4882a593Smuzhiyun #define SXGBE_MTL_RXQ_OP_FUP BIT(3) 20*4882a593Smuzhiyun #define SXGBE_MTL_ENABLE_FC 0x80 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define ETS_WRR 0xFFFFFF9F 23*4882a593Smuzhiyun #define ETS_RST 0xFFFFFF9F 24*4882a593Smuzhiyun #define ETS_WFQ 0x00000020 25*4882a593Smuzhiyun #define ETS_DWRR 0x00000040 26*4882a593Smuzhiyun #define RAA_SP 0xFFFFFFFB 27*4882a593Smuzhiyun #define RAA_WSP 0x00000004 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define RX_QUEUE_DYNAMIC 0x80808080 30*4882a593Smuzhiyun #define RX_FC_ACTIVE 8 31*4882a593Smuzhiyun #define RX_FC_DEACTIVE 13 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun enum ttc_control { 34*4882a593Smuzhiyun MTL_CONTROL_TTC_64 = 0x00000000, 35*4882a593Smuzhiyun MTL_CONTROL_TTC_96 = 0x00000020, 36*4882a593Smuzhiyun MTL_CONTROL_TTC_128 = 0x00000030, 37*4882a593Smuzhiyun MTL_CONTROL_TTC_192 = 0x00000040, 38*4882a593Smuzhiyun MTL_CONTROL_TTC_256 = 0x00000050, 39*4882a593Smuzhiyun MTL_CONTROL_TTC_384 = 0x00000060, 40*4882a593Smuzhiyun MTL_CONTROL_TTC_512 = 0x00000070, 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun enum rtc_control { 44*4882a593Smuzhiyun MTL_CONTROL_RTC_64 = 0x00000000, 45*4882a593Smuzhiyun MTL_CONTROL_RTC_96 = 0x00000002, 46*4882a593Smuzhiyun MTL_CONTROL_RTC_128 = 0x00000003, 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun enum flow_control_th { 50*4882a593Smuzhiyun MTL_FC_FULL_1K = 0x00000000, 51*4882a593Smuzhiyun MTL_FC_FULL_2K = 0x00000001, 52*4882a593Smuzhiyun MTL_FC_FULL_4K = 0x00000002, 53*4882a593Smuzhiyun MTL_FC_FULL_5K = 0x00000003, 54*4882a593Smuzhiyun MTL_FC_FULL_6K = 0x00000004, 55*4882a593Smuzhiyun MTL_FC_FULL_8K = 0x00000005, 56*4882a593Smuzhiyun MTL_FC_FULL_16K = 0x00000006, 57*4882a593Smuzhiyun MTL_FC_FULL_24K = 0x00000007, 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct sxgbe_mtl_ops { 61*4882a593Smuzhiyun void (*mtl_init)(void __iomem *ioaddr, unsigned int etsalg, 62*4882a593Smuzhiyun unsigned int raa); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun void (*mtl_set_txfifosize)(void __iomem *ioaddr, int queue_num, 65*4882a593Smuzhiyun int mtl_fifo); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun void (*mtl_set_rxfifosize)(void __iomem *ioaddr, int queue_num, 68*4882a593Smuzhiyun int queue_fifo); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun void (*mtl_enable_txqueue)(void __iomem *ioaddr, int queue_num); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun void (*mtl_disable_txqueue)(void __iomem *ioaddr, int queue_num); 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun void (*set_tx_mtl_mode)(void __iomem *ioaddr, int queue_num, 75*4882a593Smuzhiyun int tx_mode); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun void (*set_rx_mtl_mode)(void __iomem *ioaddr, int queue_num, 78*4882a593Smuzhiyun int rx_mode); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun void (*mtl_dynamic_dma_rxqueue)(void __iomem *ioaddr); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun void (*mtl_fc_active)(void __iomem *ioaddr, int queue_num, 83*4882a593Smuzhiyun int threshold); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun void (*mtl_fc_deactive)(void __iomem *ioaddr, int queue_num, 86*4882a593Smuzhiyun int threshold); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun void (*mtl_fc_enable)(void __iomem *ioaddr, int queue_num); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun void (*mtl_fep_enable)(void __iomem *ioaddr, int queue_num); 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun void (*mtl_fep_disable)(void __iomem *ioaddr, int queue_num); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun void (*mtl_fup_enable)(void __iomem *ioaddr, int queue_num); 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun void (*mtl_fup_disable)(void __iomem *ioaddr, int queue_num); 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif /* __SXGBE_MTL_H__ */ 102