1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 10G controller driver for Samsung SoCs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5*4882a593Smuzhiyun * http://www.samsung.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Siva Reddy Kallam <siva.kallam@samsung.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __SXGBE_DMA_H__ 10*4882a593Smuzhiyun #define __SXGBE_DMA_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* forward declaration */ 13*4882a593Smuzhiyun struct sxgbe_extra_stats; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SXGBE_DMA_BLENMAP_LSHIFT 1 16*4882a593Smuzhiyun #define SXGBE_DMA_TXPBL_LSHIFT 16 17*4882a593Smuzhiyun #define SXGBE_DMA_RXPBL_LSHIFT 16 18*4882a593Smuzhiyun #define DEFAULT_DMA_PBL 8 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct sxgbe_dma_ops { 21*4882a593Smuzhiyun /* DMA core initialization */ 22*4882a593Smuzhiyun int (*init)(void __iomem *ioaddr, int fix_burst, int burst_map); 23*4882a593Smuzhiyun void (*cha_init)(void __iomem *ioaddr, int cha_num, int fix_burst, 24*4882a593Smuzhiyun int pbl, dma_addr_t dma_tx, dma_addr_t dma_rx, 25*4882a593Smuzhiyun int t_rzie, int r_rsize); 26*4882a593Smuzhiyun void (*enable_dma_transmission)(void __iomem *ioaddr, int dma_cnum); 27*4882a593Smuzhiyun void (*enable_dma_irq)(void __iomem *ioaddr, int dma_cnum); 28*4882a593Smuzhiyun void (*disable_dma_irq)(void __iomem *ioaddr, int dma_cnum); 29*4882a593Smuzhiyun void (*start_tx)(void __iomem *ioaddr, int tchannels); 30*4882a593Smuzhiyun void (*start_tx_queue)(void __iomem *ioaddr, int dma_cnum); 31*4882a593Smuzhiyun void (*stop_tx)(void __iomem *ioaddr, int tchannels); 32*4882a593Smuzhiyun void (*stop_tx_queue)(void __iomem *ioaddr, int dma_cnum); 33*4882a593Smuzhiyun void (*start_rx)(void __iomem *ioaddr, int rchannels); 34*4882a593Smuzhiyun void (*stop_rx)(void __iomem *ioaddr, int rchannels); 35*4882a593Smuzhiyun int (*tx_dma_int_status)(void __iomem *ioaddr, int channel_no, 36*4882a593Smuzhiyun struct sxgbe_extra_stats *x); 37*4882a593Smuzhiyun int (*rx_dma_int_status)(void __iomem *ioaddr, int channel_no, 38*4882a593Smuzhiyun struct sxgbe_extra_stats *x); 39*4882a593Smuzhiyun /* Program the HW RX Watchdog */ 40*4882a593Smuzhiyun void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt); 41*4882a593Smuzhiyun /* Enable TSO for each DMA channel */ 42*4882a593Smuzhiyun void (*enable_tso)(void __iomem *ioaddr, u8 chan_num); 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun const struct sxgbe_dma_ops *sxgbe_get_dma_ops(void); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif /* __SXGBE_CORE_H__ */ 48