1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* r8169_firmware.c: RealTek 8169/8168/8101 ethernet driver.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5*4882a593Smuzhiyun * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6*4882a593Smuzhiyun * Copyright (c) a lot of people too. Please respect their work.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * See MAINTAINERS file for support contact information.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/firmware.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "r8169_firmware.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun enum rtl_fw_opcode {
17*4882a593Smuzhiyun PHY_READ = 0x0,
18*4882a593Smuzhiyun PHY_DATA_OR = 0x1,
19*4882a593Smuzhiyun PHY_DATA_AND = 0x2,
20*4882a593Smuzhiyun PHY_BJMPN = 0x3,
21*4882a593Smuzhiyun PHY_MDIO_CHG = 0x4,
22*4882a593Smuzhiyun PHY_CLEAR_READCOUNT = 0x7,
23*4882a593Smuzhiyun PHY_WRITE = 0x8,
24*4882a593Smuzhiyun PHY_READCOUNT_EQ_SKIP = 0x9,
25*4882a593Smuzhiyun PHY_COMP_EQ_SKIPN = 0xa,
26*4882a593Smuzhiyun PHY_COMP_NEQ_SKIPN = 0xb,
27*4882a593Smuzhiyun PHY_WRITE_PREVIOUS = 0xc,
28*4882a593Smuzhiyun PHY_SKIPN = 0xd,
29*4882a593Smuzhiyun PHY_DELAY_MS = 0xe,
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun struct fw_info {
33*4882a593Smuzhiyun u32 magic;
34*4882a593Smuzhiyun char version[RTL_VER_SIZE];
35*4882a593Smuzhiyun __le32 fw_start;
36*4882a593Smuzhiyun __le32 fw_len;
37*4882a593Smuzhiyun u8 chksum;
38*4882a593Smuzhiyun } __packed;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define FW_OPCODE_SIZE sizeof_field(struct rtl_fw_phy_action, code[0])
41*4882a593Smuzhiyun
rtl_fw_format_ok(struct rtl_fw * rtl_fw)42*4882a593Smuzhiyun static bool rtl_fw_format_ok(struct rtl_fw *rtl_fw)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun const struct firmware *fw = rtl_fw->fw;
45*4882a593Smuzhiyun struct fw_info *fw_info = (struct fw_info *)fw->data;
46*4882a593Smuzhiyun struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (fw->size < FW_OPCODE_SIZE)
49*4882a593Smuzhiyun return false;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun if (!fw_info->magic) {
52*4882a593Smuzhiyun size_t i, size, start;
53*4882a593Smuzhiyun u8 checksum = 0;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (fw->size < sizeof(*fw_info))
56*4882a593Smuzhiyun return false;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun for (i = 0; i < fw->size; i++)
59*4882a593Smuzhiyun checksum += fw->data[i];
60*4882a593Smuzhiyun if (checksum != 0)
61*4882a593Smuzhiyun return false;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun start = le32_to_cpu(fw_info->fw_start);
64*4882a593Smuzhiyun if (start > fw->size)
65*4882a593Smuzhiyun return false;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun size = le32_to_cpu(fw_info->fw_len);
68*4882a593Smuzhiyun if (size > (fw->size - start) / FW_OPCODE_SIZE)
69*4882a593Smuzhiyun return false;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun strscpy(rtl_fw->version, fw_info->version, RTL_VER_SIZE);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun pa->code = (__le32 *)(fw->data + start);
74*4882a593Smuzhiyun pa->size = size;
75*4882a593Smuzhiyun } else {
76*4882a593Smuzhiyun if (fw->size % FW_OPCODE_SIZE)
77*4882a593Smuzhiyun return false;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun strscpy(rtl_fw->version, rtl_fw->fw_name, RTL_VER_SIZE);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun pa->code = (__le32 *)fw->data;
82*4882a593Smuzhiyun pa->size = fw->size / FW_OPCODE_SIZE;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return true;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
rtl_fw_data_ok(struct rtl_fw * rtl_fw)88*4882a593Smuzhiyun static bool rtl_fw_data_ok(struct rtl_fw *rtl_fw)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
91*4882a593Smuzhiyun size_t index;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun for (index = 0; index < pa->size; index++) {
94*4882a593Smuzhiyun u32 action = le32_to_cpu(pa->code[index]);
95*4882a593Smuzhiyun u32 val = action & 0x0000ffff;
96*4882a593Smuzhiyun u32 regno = (action & 0x0fff0000) >> 16;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun switch (action >> 28) {
99*4882a593Smuzhiyun case PHY_READ:
100*4882a593Smuzhiyun case PHY_DATA_OR:
101*4882a593Smuzhiyun case PHY_DATA_AND:
102*4882a593Smuzhiyun case PHY_CLEAR_READCOUNT:
103*4882a593Smuzhiyun case PHY_WRITE:
104*4882a593Smuzhiyun case PHY_WRITE_PREVIOUS:
105*4882a593Smuzhiyun case PHY_DELAY_MS:
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun case PHY_MDIO_CHG:
109*4882a593Smuzhiyun if (val > 1)
110*4882a593Smuzhiyun goto out;
111*4882a593Smuzhiyun break;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun case PHY_BJMPN:
114*4882a593Smuzhiyun if (regno > index)
115*4882a593Smuzhiyun goto out;
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun case PHY_READCOUNT_EQ_SKIP:
118*4882a593Smuzhiyun if (index + 2 >= pa->size)
119*4882a593Smuzhiyun goto out;
120*4882a593Smuzhiyun break;
121*4882a593Smuzhiyun case PHY_COMP_EQ_SKIPN:
122*4882a593Smuzhiyun case PHY_COMP_NEQ_SKIPN:
123*4882a593Smuzhiyun case PHY_SKIPN:
124*4882a593Smuzhiyun if (index + 1 + regno >= pa->size)
125*4882a593Smuzhiyun goto out;
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun default:
129*4882a593Smuzhiyun dev_err(rtl_fw->dev, "Invalid action 0x%08x\n", action);
130*4882a593Smuzhiyun return false;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun return true;
135*4882a593Smuzhiyun out:
136*4882a593Smuzhiyun dev_err(rtl_fw->dev, "Out of range of firmware\n");
137*4882a593Smuzhiyun return false;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
rtl_fw_write_firmware(struct rtl8169_private * tp,struct rtl_fw * rtl_fw)140*4882a593Smuzhiyun void rtl_fw_write_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
143*4882a593Smuzhiyun rtl_fw_write_t fw_write = rtl_fw->phy_write;
144*4882a593Smuzhiyun rtl_fw_read_t fw_read = rtl_fw->phy_read;
145*4882a593Smuzhiyun int predata = 0, count = 0;
146*4882a593Smuzhiyun size_t index;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun for (index = 0; index < pa->size; index++) {
149*4882a593Smuzhiyun u32 action = le32_to_cpu(pa->code[index]);
150*4882a593Smuzhiyun u32 data = action & 0x0000ffff;
151*4882a593Smuzhiyun u32 regno = (action & 0x0fff0000) >> 16;
152*4882a593Smuzhiyun enum rtl_fw_opcode opcode = action >> 28;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (!action)
155*4882a593Smuzhiyun break;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun switch (opcode) {
158*4882a593Smuzhiyun case PHY_READ:
159*4882a593Smuzhiyun predata = fw_read(tp, regno);
160*4882a593Smuzhiyun count++;
161*4882a593Smuzhiyun break;
162*4882a593Smuzhiyun case PHY_DATA_OR:
163*4882a593Smuzhiyun predata |= data;
164*4882a593Smuzhiyun break;
165*4882a593Smuzhiyun case PHY_DATA_AND:
166*4882a593Smuzhiyun predata &= data;
167*4882a593Smuzhiyun break;
168*4882a593Smuzhiyun case PHY_BJMPN:
169*4882a593Smuzhiyun index -= (regno + 1);
170*4882a593Smuzhiyun break;
171*4882a593Smuzhiyun case PHY_MDIO_CHG:
172*4882a593Smuzhiyun if (data) {
173*4882a593Smuzhiyun fw_write = rtl_fw->mac_mcu_write;
174*4882a593Smuzhiyun fw_read = rtl_fw->mac_mcu_read;
175*4882a593Smuzhiyun } else {
176*4882a593Smuzhiyun fw_write = rtl_fw->phy_write;
177*4882a593Smuzhiyun fw_read = rtl_fw->phy_read;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun break;
181*4882a593Smuzhiyun case PHY_CLEAR_READCOUNT:
182*4882a593Smuzhiyun count = 0;
183*4882a593Smuzhiyun break;
184*4882a593Smuzhiyun case PHY_WRITE:
185*4882a593Smuzhiyun fw_write(tp, regno, data);
186*4882a593Smuzhiyun break;
187*4882a593Smuzhiyun case PHY_READCOUNT_EQ_SKIP:
188*4882a593Smuzhiyun if (count == data)
189*4882a593Smuzhiyun index++;
190*4882a593Smuzhiyun break;
191*4882a593Smuzhiyun case PHY_COMP_EQ_SKIPN:
192*4882a593Smuzhiyun if (predata == data)
193*4882a593Smuzhiyun index += regno;
194*4882a593Smuzhiyun break;
195*4882a593Smuzhiyun case PHY_COMP_NEQ_SKIPN:
196*4882a593Smuzhiyun if (predata != data)
197*4882a593Smuzhiyun index += regno;
198*4882a593Smuzhiyun break;
199*4882a593Smuzhiyun case PHY_WRITE_PREVIOUS:
200*4882a593Smuzhiyun fw_write(tp, regno, predata);
201*4882a593Smuzhiyun break;
202*4882a593Smuzhiyun case PHY_SKIPN:
203*4882a593Smuzhiyun index += regno;
204*4882a593Smuzhiyun break;
205*4882a593Smuzhiyun case PHY_DELAY_MS:
206*4882a593Smuzhiyun msleep(data);
207*4882a593Smuzhiyun break;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
rtl_fw_release_firmware(struct rtl_fw * rtl_fw)212*4882a593Smuzhiyun void rtl_fw_release_firmware(struct rtl_fw *rtl_fw)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun release_firmware(rtl_fw->fw);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
rtl_fw_request_firmware(struct rtl_fw * rtl_fw)217*4882a593Smuzhiyun int rtl_fw_request_firmware(struct rtl_fw *rtl_fw)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun int rc;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, rtl_fw->dev);
222*4882a593Smuzhiyun if (rc < 0)
223*4882a593Smuzhiyun goto out;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun if (!rtl_fw_format_ok(rtl_fw) || !rtl_fw_data_ok(rtl_fw)) {
226*4882a593Smuzhiyun release_firmware(rtl_fw->fw);
227*4882a593Smuzhiyun rc = -EINVAL;
228*4882a593Smuzhiyun goto out;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun return 0;
232*4882a593Smuzhiyun out:
233*4882a593Smuzhiyun dev_err(rtl_fw->dev, "Unable to load firmware %s (%d)\n",
234*4882a593Smuzhiyun rtl_fw->fw_name, rc);
235*4882a593Smuzhiyun return rc;
236*4882a593Smuzhiyun }
237