1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc. 3*4882a593Smuzhiyun * Copyright (c) 2014, I2SE GmbH 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software 6*4882a593Smuzhiyun * for any purpose with or without fee is hereby granted, provided 7*4882a593Smuzhiyun * that the above copyright notice and this permission notice appear 8*4882a593Smuzhiyun * in all copies. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*4882a593Smuzhiyun * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL 13*4882a593Smuzhiyun * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR 14*4882a593Smuzhiyun * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 15*4882a593Smuzhiyun * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, 16*4882a593Smuzhiyun * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 17*4882a593Smuzhiyun * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Qualcomm Atheros SPI register definition. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * This module is designed to define the Qualcomm Atheros SPI 24*4882a593Smuzhiyun * register placeholders. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifndef _QCA_7K_H 28*4882a593Smuzhiyun #define _QCA_7K_H 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #include <linux/types.h> 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #include "qca_spi.h" 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define QCA7K_SPI_READ (1 << 15) 35*4882a593Smuzhiyun #define QCA7K_SPI_WRITE (0 << 15) 36*4882a593Smuzhiyun #define QCA7K_SPI_INTERNAL (1 << 14) 37*4882a593Smuzhiyun #define QCA7K_SPI_EXTERNAL (0 << 14) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define QCASPI_CMD_LEN 2 40*4882a593Smuzhiyun #define QCASPI_HW_PKT_LEN 4 41*4882a593Smuzhiyun #define QCASPI_HW_BUF_LEN 0xC5B 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* SPI registers; */ 44*4882a593Smuzhiyun #define SPI_REG_BFR_SIZE 0x0100 45*4882a593Smuzhiyun #define SPI_REG_WRBUF_SPC_AVA 0x0200 46*4882a593Smuzhiyun #define SPI_REG_RDBUF_BYTE_AVA 0x0300 47*4882a593Smuzhiyun #define SPI_REG_SPI_CONFIG 0x0400 48*4882a593Smuzhiyun #define SPI_REG_SPI_STATUS 0x0500 49*4882a593Smuzhiyun #define SPI_REG_INTR_CAUSE 0x0C00 50*4882a593Smuzhiyun #define SPI_REG_INTR_ENABLE 0x0D00 51*4882a593Smuzhiyun #define SPI_REG_RDBUF_WATERMARK 0x1200 52*4882a593Smuzhiyun #define SPI_REG_WRBUF_WATERMARK 0x1300 53*4882a593Smuzhiyun #define SPI_REG_SIGNATURE 0x1A00 54*4882a593Smuzhiyun #define SPI_REG_ACTION_CTRL 0x1B00 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* SPI_CONFIG register definition; */ 57*4882a593Smuzhiyun #define QCASPI_SLAVE_RESET_BIT BIT(6) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* INTR_CAUSE/ENABLE register definition. */ 60*4882a593Smuzhiyun #define SPI_INT_WRBUF_BELOW_WM BIT(10) 61*4882a593Smuzhiyun #define SPI_INT_CPU_ON BIT(6) 62*4882a593Smuzhiyun #define SPI_INT_ADDR_ERR BIT(3) 63*4882a593Smuzhiyun #define SPI_INT_WRBUF_ERR BIT(2) 64*4882a593Smuzhiyun #define SPI_INT_RDBUF_ERR BIT(1) 65*4882a593Smuzhiyun #define SPI_INT_PKT_AVLBL BIT(0) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun void qcaspi_spi_error(struct qcaspi *qca); 68*4882a593Smuzhiyun int qcaspi_read_register(struct qcaspi *qca, u16 reg, u16 *result); 69*4882a593Smuzhiyun int qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value, int retry); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif /* _QCA_7K_H */ 72