1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
4*4882a593Smuzhiyun * Copyright (c) 2014, I2SE GmbH
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software
7*4882a593Smuzhiyun * for any purpose with or without fee is hereby granted, provided
8*4882a593Smuzhiyun * that the above copyright notice and this permission notice appear
9*4882a593Smuzhiyun * in all copies.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
12*4882a593Smuzhiyun * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
13*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
14*4882a593Smuzhiyun * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
15*4882a593Smuzhiyun * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
16*4882a593Smuzhiyun * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
17*4882a593Smuzhiyun * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
18*4882a593Smuzhiyun * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* This module implements the Qualcomm Atheros SPI protocol for
23*4882a593Smuzhiyun * kernel-based SPI device.
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <linux/kernel.h>
27*4882a593Smuzhiyun #include <linux/netdevice.h>
28*4882a593Smuzhiyun #include <linux/spi/spi.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "qca_7k.h"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun void
qcaspi_spi_error(struct qcaspi * qca)33*4882a593Smuzhiyun qcaspi_spi_error(struct qcaspi *qca)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun if (qca->sync != QCASPI_SYNC_READY)
36*4882a593Smuzhiyun return;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun netdev_err(qca->net_dev, "spi error\n");
39*4882a593Smuzhiyun qca->sync = QCASPI_SYNC_UNKNOWN;
40*4882a593Smuzhiyun qca->stats.spi_err++;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun int
qcaspi_read_register(struct qcaspi * qca,u16 reg,u16 * result)44*4882a593Smuzhiyun qcaspi_read_register(struct qcaspi *qca, u16 reg, u16 *result)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun __be16 rx_data;
47*4882a593Smuzhiyun __be16 tx_data;
48*4882a593Smuzhiyun struct spi_transfer transfer[2];
49*4882a593Smuzhiyun struct spi_message msg;
50*4882a593Smuzhiyun int ret;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun memset(transfer, 0, sizeof(transfer));
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun spi_message_init(&msg);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun tx_data = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_INTERNAL | reg);
57*4882a593Smuzhiyun *result = 0;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun transfer[0].tx_buf = &tx_data;
60*4882a593Smuzhiyun transfer[0].len = QCASPI_CMD_LEN;
61*4882a593Smuzhiyun transfer[1].rx_buf = &rx_data;
62*4882a593Smuzhiyun transfer[1].len = QCASPI_CMD_LEN;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun spi_message_add_tail(&transfer[0], &msg);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (qca->legacy_mode) {
67*4882a593Smuzhiyun spi_sync(qca->spi_dev, &msg);
68*4882a593Smuzhiyun spi_message_init(&msg);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun spi_message_add_tail(&transfer[1], &msg);
71*4882a593Smuzhiyun ret = spi_sync(qca->spi_dev, &msg);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (!ret)
74*4882a593Smuzhiyun ret = msg.status;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (ret)
77*4882a593Smuzhiyun qcaspi_spi_error(qca);
78*4882a593Smuzhiyun else
79*4882a593Smuzhiyun *result = be16_to_cpu(rx_data);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return ret;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static int
__qcaspi_write_register(struct qcaspi * qca,u16 reg,u16 value)85*4882a593Smuzhiyun __qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun __be16 tx_data[2];
88*4882a593Smuzhiyun struct spi_transfer transfer[2];
89*4882a593Smuzhiyun struct spi_message msg;
90*4882a593Smuzhiyun int ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun memset(&transfer, 0, sizeof(transfer));
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun spi_message_init(&msg);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun tx_data[0] = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_INTERNAL | reg);
97*4882a593Smuzhiyun tx_data[1] = cpu_to_be16(value);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun transfer[0].tx_buf = &tx_data[0];
100*4882a593Smuzhiyun transfer[0].len = QCASPI_CMD_LEN;
101*4882a593Smuzhiyun transfer[1].tx_buf = &tx_data[1];
102*4882a593Smuzhiyun transfer[1].len = QCASPI_CMD_LEN;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun spi_message_add_tail(&transfer[0], &msg);
105*4882a593Smuzhiyun if (qca->legacy_mode) {
106*4882a593Smuzhiyun spi_sync(qca->spi_dev, &msg);
107*4882a593Smuzhiyun spi_message_init(&msg);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun spi_message_add_tail(&transfer[1], &msg);
110*4882a593Smuzhiyun ret = spi_sync(qca->spi_dev, &msg);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (!ret)
113*4882a593Smuzhiyun ret = msg.status;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun if (ret)
116*4882a593Smuzhiyun qcaspi_spi_error(qca);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun int
qcaspi_write_register(struct qcaspi * qca,u16 reg,u16 value,int retry)122*4882a593Smuzhiyun qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value, int retry)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun int ret, i = 0;
125*4882a593Smuzhiyun u16 confirmed;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun do {
128*4882a593Smuzhiyun ret = __qcaspi_write_register(qca, reg, value);
129*4882a593Smuzhiyun if (ret)
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if (!retry)
133*4882a593Smuzhiyun return 0;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun ret = qcaspi_read_register(qca, reg, &confirmed);
136*4882a593Smuzhiyun if (ret)
137*4882a593Smuzhiyun return ret;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun ret = confirmed != value;
140*4882a593Smuzhiyun if (!ret)
141*4882a593Smuzhiyun return 0;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun i++;
144*4882a593Smuzhiyun qca->stats.write_verify_failed++;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun } while (i <= retry);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return ret;
149*4882a593Smuzhiyun }
150