1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /* Qualcomm Technologies, Inc. EMAC Gigabit Ethernet Driver */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/if_ether.h>
8*4882a593Smuzhiyun #include <linux/if_vlan.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_net.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/phy.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/acpi.h>
18*4882a593Smuzhiyun #include "emac.h"
19*4882a593Smuzhiyun #include "emac-mac.h"
20*4882a593Smuzhiyun #include "emac-phy.h"
21*4882a593Smuzhiyun #include "emac-sgmii.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define EMAC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
24*4882a593Smuzhiyun NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define EMAC_RRD_SIZE 4
27*4882a593Smuzhiyun /* The RRD size if timestamping is enabled: */
28*4882a593Smuzhiyun #define EMAC_TS_RRD_SIZE 6
29*4882a593Smuzhiyun #define EMAC_TPD_SIZE 4
30*4882a593Smuzhiyun #define EMAC_RFD_SIZE 2
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define REG_MAC_RX_STATUS_BIN EMAC_RXMAC_STATC_REG0
33*4882a593Smuzhiyun #define REG_MAC_RX_STATUS_END EMAC_RXMAC_STATC_REG22
34*4882a593Smuzhiyun #define REG_MAC_TX_STATUS_BIN EMAC_TXMAC_STATC_REG0
35*4882a593Smuzhiyun #define REG_MAC_TX_STATUS_END EMAC_TXMAC_STATC_REG24
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define RXQ0_NUM_RFD_PREF_DEF 8
38*4882a593Smuzhiyun #define TXQ0_NUM_TPD_PREF_DEF 5
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define EMAC_PREAMBLE_DEF 7
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define DMAR_DLY_CNT_DEF 15
43*4882a593Smuzhiyun #define DMAW_DLY_CNT_DEF 4
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define IMR_NORMAL_MASK (ISR_ERROR | ISR_OVER | ISR_TX_PKT)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define ISR_TX_PKT (\
48*4882a593Smuzhiyun TX_PKT_INT |\
49*4882a593Smuzhiyun TX_PKT_INT1 |\
50*4882a593Smuzhiyun TX_PKT_INT2 |\
51*4882a593Smuzhiyun TX_PKT_INT3)
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define ISR_OVER (\
54*4882a593Smuzhiyun RFD0_UR_INT |\
55*4882a593Smuzhiyun RFD1_UR_INT |\
56*4882a593Smuzhiyun RFD2_UR_INT |\
57*4882a593Smuzhiyun RFD3_UR_INT |\
58*4882a593Smuzhiyun RFD4_UR_INT |\
59*4882a593Smuzhiyun RXF_OF_INT |\
60*4882a593Smuzhiyun TXF_UR_INT)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define ISR_ERROR (\
63*4882a593Smuzhiyun DMAR_TO_INT |\
64*4882a593Smuzhiyun DMAW_TO_INT |\
65*4882a593Smuzhiyun TXQ_TO_INT)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* in sync with enum emac_clk_id */
68*4882a593Smuzhiyun static const char * const emac_clk_name[] = {
69*4882a593Smuzhiyun "axi_clk", "cfg_ahb_clk", "high_speed_clk", "mdio_clk", "tx_clk",
70*4882a593Smuzhiyun "rx_clk", "sys_clk"
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
emac_reg_update32(void __iomem * addr,u32 mask,u32 val)73*4882a593Smuzhiyun void emac_reg_update32(void __iomem *addr, u32 mask, u32 val)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun u32 data = readl(addr);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun writel(((data & ~mask) | val), addr);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* reinitialize */
emac_reinit_locked(struct emac_adapter * adpt)81*4882a593Smuzhiyun int emac_reinit_locked(struct emac_adapter *adpt)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun int ret;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun mutex_lock(&adpt->reset_lock);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun emac_mac_down(adpt);
88*4882a593Smuzhiyun emac_sgmii_reset(adpt);
89*4882a593Smuzhiyun ret = emac_mac_up(adpt);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun mutex_unlock(&adpt->reset_lock);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return ret;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* NAPI */
emac_napi_rtx(struct napi_struct * napi,int budget)97*4882a593Smuzhiyun static int emac_napi_rtx(struct napi_struct *napi, int budget)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct emac_rx_queue *rx_q =
100*4882a593Smuzhiyun container_of(napi, struct emac_rx_queue, napi);
101*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(rx_q->netdev);
102*4882a593Smuzhiyun struct emac_irq *irq = rx_q->irq;
103*4882a593Smuzhiyun int work_done = 0;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun emac_mac_rx_process(adpt, rx_q, &work_done, budget);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun if (work_done < budget) {
108*4882a593Smuzhiyun napi_complete_done(napi, work_done);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun irq->mask |= rx_q->intr;
111*4882a593Smuzhiyun writel(irq->mask, adpt->base + EMAC_INT_MASK);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return work_done;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Transmit the packet */
emac_start_xmit(struct sk_buff * skb,struct net_device * netdev)118*4882a593Smuzhiyun static netdev_tx_t emac_start_xmit(struct sk_buff *skb,
119*4882a593Smuzhiyun struct net_device *netdev)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return emac_mac_tx_buf_send(adpt, &adpt->tx_q, skb);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
emac_isr(int _irq,void * data)126*4882a593Smuzhiyun static irqreturn_t emac_isr(int _irq, void *data)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun struct emac_irq *irq = data;
129*4882a593Smuzhiyun struct emac_adapter *adpt =
130*4882a593Smuzhiyun container_of(irq, struct emac_adapter, irq);
131*4882a593Smuzhiyun struct emac_rx_queue *rx_q = &adpt->rx_q;
132*4882a593Smuzhiyun u32 isr, status;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* disable the interrupt */
135*4882a593Smuzhiyun writel(0, adpt->base + EMAC_INT_MASK);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun isr = readl_relaxed(adpt->base + EMAC_INT_STATUS);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun status = isr & irq->mask;
140*4882a593Smuzhiyun if (status == 0)
141*4882a593Smuzhiyun goto exit;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun if (status & ISR_ERROR) {
144*4882a593Smuzhiyun net_err_ratelimited("%s: error interrupt 0x%lx\n",
145*4882a593Smuzhiyun adpt->netdev->name, status & ISR_ERROR);
146*4882a593Smuzhiyun /* reset MAC */
147*4882a593Smuzhiyun schedule_work(&adpt->work_thread);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* Schedule the napi for receive queue with interrupt
151*4882a593Smuzhiyun * status bit set
152*4882a593Smuzhiyun */
153*4882a593Smuzhiyun if (status & rx_q->intr) {
154*4882a593Smuzhiyun if (napi_schedule_prep(&rx_q->napi)) {
155*4882a593Smuzhiyun irq->mask &= ~rx_q->intr;
156*4882a593Smuzhiyun __napi_schedule(&rx_q->napi);
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (status & TX_PKT_INT)
161*4882a593Smuzhiyun emac_mac_tx_process(adpt, &adpt->tx_q);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun if (status & ISR_OVER)
164*4882a593Smuzhiyun net_warn_ratelimited("%s: TX/RX overflow interrupt\n",
165*4882a593Smuzhiyun adpt->netdev->name);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun exit:
168*4882a593Smuzhiyun /* enable the interrupt */
169*4882a593Smuzhiyun writel(irq->mask, adpt->base + EMAC_INT_MASK);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return IRQ_HANDLED;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* Configure VLAN tag strip/insert feature */
emac_set_features(struct net_device * netdev,netdev_features_t features)175*4882a593Smuzhiyun static int emac_set_features(struct net_device *netdev,
176*4882a593Smuzhiyun netdev_features_t features)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun netdev_features_t changed = features ^ netdev->features;
179*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* We only need to reprogram the hardware if the VLAN tag features
182*4882a593Smuzhiyun * have changed, and if it's already running.
183*4882a593Smuzhiyun */
184*4882a593Smuzhiyun if (!(changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX)))
185*4882a593Smuzhiyun return 0;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun if (!netif_running(netdev))
188*4882a593Smuzhiyun return 0;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* emac_mac_mode_config() uses netdev->features to configure the EMAC,
191*4882a593Smuzhiyun * so make sure it's set first.
192*4882a593Smuzhiyun */
193*4882a593Smuzhiyun netdev->features = features;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return emac_reinit_locked(adpt);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* Configure Multicast and Promiscuous modes */
emac_rx_mode_set(struct net_device * netdev)199*4882a593Smuzhiyun static void emac_rx_mode_set(struct net_device *netdev)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
202*4882a593Smuzhiyun struct netdev_hw_addr *ha;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun emac_mac_mode_config(adpt);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /* update multicast address filtering */
207*4882a593Smuzhiyun emac_mac_multicast_addr_clear(adpt);
208*4882a593Smuzhiyun netdev_for_each_mc_addr(ha, netdev)
209*4882a593Smuzhiyun emac_mac_multicast_addr_set(adpt, ha->addr);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* Change the Maximum Transfer Unit (MTU) */
emac_change_mtu(struct net_device * netdev,int new_mtu)213*4882a593Smuzhiyun static int emac_change_mtu(struct net_device *netdev, int new_mtu)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun netif_dbg(adpt, hw, adpt->netdev,
218*4882a593Smuzhiyun "changing MTU from %d to %d\n", netdev->mtu,
219*4882a593Smuzhiyun new_mtu);
220*4882a593Smuzhiyun netdev->mtu = new_mtu;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (netif_running(netdev))
223*4882a593Smuzhiyun return emac_reinit_locked(adpt);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun return 0;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /* Called when the network interface is made active */
emac_open(struct net_device * netdev)229*4882a593Smuzhiyun static int emac_open(struct net_device *netdev)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
232*4882a593Smuzhiyun struct emac_irq *irq = &adpt->irq;
233*4882a593Smuzhiyun int ret;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun ret = request_irq(irq->irq, emac_isr, 0, "emac-core0", irq);
236*4882a593Smuzhiyun if (ret) {
237*4882a593Smuzhiyun netdev_err(adpt->netdev, "could not request emac-core0 irq\n");
238*4882a593Smuzhiyun return ret;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /* allocate rx/tx dma buffer & descriptors */
242*4882a593Smuzhiyun ret = emac_mac_rx_tx_rings_alloc_all(adpt);
243*4882a593Smuzhiyun if (ret) {
244*4882a593Smuzhiyun netdev_err(adpt->netdev, "error allocating rx/tx rings\n");
245*4882a593Smuzhiyun free_irq(irq->irq, irq);
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun ret = emac_sgmii_open(adpt);
250*4882a593Smuzhiyun if (ret) {
251*4882a593Smuzhiyun emac_mac_rx_tx_rings_free_all(adpt);
252*4882a593Smuzhiyun free_irq(irq->irq, irq);
253*4882a593Smuzhiyun return ret;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun ret = emac_mac_up(adpt);
257*4882a593Smuzhiyun if (ret) {
258*4882a593Smuzhiyun emac_mac_rx_tx_rings_free_all(adpt);
259*4882a593Smuzhiyun free_irq(irq->irq, irq);
260*4882a593Smuzhiyun emac_sgmii_close(adpt);
261*4882a593Smuzhiyun return ret;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun return 0;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun /* Called when the network interface is disabled */
emac_close(struct net_device * netdev)268*4882a593Smuzhiyun static int emac_close(struct net_device *netdev)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun mutex_lock(&adpt->reset_lock);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun emac_sgmii_close(adpt);
275*4882a593Smuzhiyun emac_mac_down(adpt);
276*4882a593Smuzhiyun emac_mac_rx_tx_rings_free_all(adpt);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun free_irq(adpt->irq.irq, &adpt->irq);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun mutex_unlock(&adpt->reset_lock);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun return 0;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /* Respond to a TX hang */
emac_tx_timeout(struct net_device * netdev,unsigned int txqueue)286*4882a593Smuzhiyun static void emac_tx_timeout(struct net_device *netdev, unsigned int txqueue)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun schedule_work(&adpt->work_thread);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /**
294*4882a593Smuzhiyun * emac_update_hw_stats - read the EMAC stat registers
295*4882a593Smuzhiyun * @adpt: pointer to adapter struct
296*4882a593Smuzhiyun *
297*4882a593Smuzhiyun * Reads the stats registers and write the values to adpt->stats.
298*4882a593Smuzhiyun *
299*4882a593Smuzhiyun * adpt->stats.lock must be held while calling this function,
300*4882a593Smuzhiyun * and while reading from adpt->stats.
301*4882a593Smuzhiyun */
emac_update_hw_stats(struct emac_adapter * adpt)302*4882a593Smuzhiyun void emac_update_hw_stats(struct emac_adapter *adpt)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun struct emac_stats *stats = &adpt->stats;
305*4882a593Smuzhiyun u64 *stats_itr = &adpt->stats.rx_ok;
306*4882a593Smuzhiyun void __iomem *base = adpt->base;
307*4882a593Smuzhiyun unsigned int addr;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun addr = REG_MAC_RX_STATUS_BIN;
310*4882a593Smuzhiyun while (addr <= REG_MAC_RX_STATUS_END) {
311*4882a593Smuzhiyun *stats_itr += readl_relaxed(base + addr);
312*4882a593Smuzhiyun stats_itr++;
313*4882a593Smuzhiyun addr += sizeof(u32);
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* additional rx status */
317*4882a593Smuzhiyun stats->rx_crc_align += readl_relaxed(base + EMAC_RXMAC_STATC_REG23);
318*4882a593Smuzhiyun stats->rx_jabbers += readl_relaxed(base + EMAC_RXMAC_STATC_REG24);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun /* update tx status */
321*4882a593Smuzhiyun addr = REG_MAC_TX_STATUS_BIN;
322*4882a593Smuzhiyun stats_itr = &stats->tx_ok;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun while (addr <= REG_MAC_TX_STATUS_END) {
325*4882a593Smuzhiyun *stats_itr += readl_relaxed(base + addr);
326*4882a593Smuzhiyun stats_itr++;
327*4882a593Smuzhiyun addr += sizeof(u32);
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun /* additional tx status */
331*4882a593Smuzhiyun stats->tx_col += readl_relaxed(base + EMAC_TXMAC_STATC_REG25);
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* Provide network statistics info for the interface */
emac_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * net_stats)335*4882a593Smuzhiyun static void emac_get_stats64(struct net_device *netdev,
336*4882a593Smuzhiyun struct rtnl_link_stats64 *net_stats)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
339*4882a593Smuzhiyun struct emac_stats *stats = &adpt->stats;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun spin_lock(&stats->lock);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun emac_update_hw_stats(adpt);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /* return parsed statistics */
346*4882a593Smuzhiyun net_stats->rx_packets = stats->rx_ok;
347*4882a593Smuzhiyun net_stats->tx_packets = stats->tx_ok;
348*4882a593Smuzhiyun net_stats->rx_bytes = stats->rx_byte_cnt;
349*4882a593Smuzhiyun net_stats->tx_bytes = stats->tx_byte_cnt;
350*4882a593Smuzhiyun net_stats->multicast = stats->rx_mcast;
351*4882a593Smuzhiyun net_stats->collisions = stats->tx_1_col + stats->tx_2_col * 2 +
352*4882a593Smuzhiyun stats->tx_late_col + stats->tx_abort_col;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun net_stats->rx_errors = stats->rx_frag + stats->rx_fcs_err +
355*4882a593Smuzhiyun stats->rx_len_err + stats->rx_sz_ov +
356*4882a593Smuzhiyun stats->rx_align_err;
357*4882a593Smuzhiyun net_stats->rx_fifo_errors = stats->rx_rxf_ov;
358*4882a593Smuzhiyun net_stats->rx_length_errors = stats->rx_len_err;
359*4882a593Smuzhiyun net_stats->rx_crc_errors = stats->rx_fcs_err;
360*4882a593Smuzhiyun net_stats->rx_frame_errors = stats->rx_align_err;
361*4882a593Smuzhiyun net_stats->rx_over_errors = stats->rx_rxf_ov;
362*4882a593Smuzhiyun net_stats->rx_missed_errors = stats->rx_rxf_ov;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun net_stats->tx_errors = stats->tx_late_col + stats->tx_abort_col +
365*4882a593Smuzhiyun stats->tx_underrun + stats->tx_trunc;
366*4882a593Smuzhiyun net_stats->tx_fifo_errors = stats->tx_underrun;
367*4882a593Smuzhiyun net_stats->tx_aborted_errors = stats->tx_abort_col;
368*4882a593Smuzhiyun net_stats->tx_window_errors = stats->tx_late_col;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun spin_unlock(&stats->lock);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun static const struct net_device_ops emac_netdev_ops = {
374*4882a593Smuzhiyun .ndo_open = emac_open,
375*4882a593Smuzhiyun .ndo_stop = emac_close,
376*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
377*4882a593Smuzhiyun .ndo_start_xmit = emac_start_xmit,
378*4882a593Smuzhiyun .ndo_set_mac_address = eth_mac_addr,
379*4882a593Smuzhiyun .ndo_change_mtu = emac_change_mtu,
380*4882a593Smuzhiyun .ndo_do_ioctl = phy_do_ioctl_running,
381*4882a593Smuzhiyun .ndo_tx_timeout = emac_tx_timeout,
382*4882a593Smuzhiyun .ndo_get_stats64 = emac_get_stats64,
383*4882a593Smuzhiyun .ndo_set_features = emac_set_features,
384*4882a593Smuzhiyun .ndo_set_rx_mode = emac_rx_mode_set,
385*4882a593Smuzhiyun };
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /* Watchdog task routine, called to reinitialize the EMAC */
emac_work_thread(struct work_struct * work)388*4882a593Smuzhiyun static void emac_work_thread(struct work_struct *work)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun struct emac_adapter *adpt =
391*4882a593Smuzhiyun container_of(work, struct emac_adapter, work_thread);
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun emac_reinit_locked(adpt);
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun /* Initialize various data structures */
emac_init_adapter(struct emac_adapter * adpt)397*4882a593Smuzhiyun static void emac_init_adapter(struct emac_adapter *adpt)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun u32 reg;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun adpt->rrd_size = EMAC_RRD_SIZE;
402*4882a593Smuzhiyun adpt->tpd_size = EMAC_TPD_SIZE;
403*4882a593Smuzhiyun adpt->rfd_size = EMAC_RFD_SIZE;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun /* descriptors */
406*4882a593Smuzhiyun adpt->tx_desc_cnt = EMAC_DEF_TX_DESCS;
407*4882a593Smuzhiyun adpt->rx_desc_cnt = EMAC_DEF_RX_DESCS;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /* dma */
410*4882a593Smuzhiyun adpt->dma_order = emac_dma_ord_out;
411*4882a593Smuzhiyun adpt->dmar_block = emac_dma_req_4096;
412*4882a593Smuzhiyun adpt->dmaw_block = emac_dma_req_128;
413*4882a593Smuzhiyun adpt->dmar_dly_cnt = DMAR_DLY_CNT_DEF;
414*4882a593Smuzhiyun adpt->dmaw_dly_cnt = DMAW_DLY_CNT_DEF;
415*4882a593Smuzhiyun adpt->tpd_burst = TXQ0_NUM_TPD_PREF_DEF;
416*4882a593Smuzhiyun adpt->rfd_burst = RXQ0_NUM_RFD_PREF_DEF;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun /* irq moderator */
419*4882a593Smuzhiyun reg = ((EMAC_DEF_RX_IRQ_MOD >> 1) << IRQ_MODERATOR2_INIT_SHFT) |
420*4882a593Smuzhiyun ((EMAC_DEF_TX_IRQ_MOD >> 1) << IRQ_MODERATOR_INIT_SHFT);
421*4882a593Smuzhiyun adpt->irq_mod = reg;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun /* others */
424*4882a593Smuzhiyun adpt->preamble = EMAC_PREAMBLE_DEF;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun /* default to automatic flow control */
427*4882a593Smuzhiyun adpt->automatic = true;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* Disable single-pause-frame mode by default */
430*4882a593Smuzhiyun adpt->single_pause_mode = false;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun /* Get the clock */
emac_clks_get(struct platform_device * pdev,struct emac_adapter * adpt)434*4882a593Smuzhiyun static int emac_clks_get(struct platform_device *pdev,
435*4882a593Smuzhiyun struct emac_adapter *adpt)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun unsigned int i;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun for (i = 0; i < EMAC_CLK_CNT; i++) {
440*4882a593Smuzhiyun struct clk *clk = devm_clk_get(&pdev->dev, emac_clk_name[i]);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun if (IS_ERR(clk)) {
443*4882a593Smuzhiyun dev_err(&pdev->dev,
444*4882a593Smuzhiyun "could not claim clock %s (error=%li)\n",
445*4882a593Smuzhiyun emac_clk_name[i], PTR_ERR(clk));
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun return PTR_ERR(clk);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun adpt->clk[i] = clk;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun return 0;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun /* Initialize clocks */
emac_clks_phase1_init(struct platform_device * pdev,struct emac_adapter * adpt)457*4882a593Smuzhiyun static int emac_clks_phase1_init(struct platform_device *pdev,
458*4882a593Smuzhiyun struct emac_adapter *adpt)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun int ret;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /* On ACPI platforms, clocks are controlled by firmware and/or
463*4882a593Smuzhiyun * ACPI, not by drivers.
464*4882a593Smuzhiyun */
465*4882a593Smuzhiyun if (has_acpi_companion(&pdev->dev))
466*4882a593Smuzhiyun return 0;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun ret = emac_clks_get(pdev, adpt);
469*4882a593Smuzhiyun if (ret)
470*4882a593Smuzhiyun return ret;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun ret = clk_prepare_enable(adpt->clk[EMAC_CLK_AXI]);
473*4882a593Smuzhiyun if (ret)
474*4882a593Smuzhiyun return ret;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun ret = clk_prepare_enable(adpt->clk[EMAC_CLK_CFG_AHB]);
477*4882a593Smuzhiyun if (ret)
478*4882a593Smuzhiyun goto disable_clk_axi;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000);
481*4882a593Smuzhiyun if (ret)
482*4882a593Smuzhiyun goto disable_clk_cfg_ahb;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun ret = clk_prepare_enable(adpt->clk[EMAC_CLK_HIGH_SPEED]);
485*4882a593Smuzhiyun if (ret)
486*4882a593Smuzhiyun goto disable_clk_cfg_ahb;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun return 0;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun disable_clk_cfg_ahb:
491*4882a593Smuzhiyun clk_disable_unprepare(adpt->clk[EMAC_CLK_CFG_AHB]);
492*4882a593Smuzhiyun disable_clk_axi:
493*4882a593Smuzhiyun clk_disable_unprepare(adpt->clk[EMAC_CLK_AXI]);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun return ret;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun /* Enable clocks; needs emac_clks_phase1_init to be called before */
emac_clks_phase2_init(struct platform_device * pdev,struct emac_adapter * adpt)499*4882a593Smuzhiyun static int emac_clks_phase2_init(struct platform_device *pdev,
500*4882a593Smuzhiyun struct emac_adapter *adpt)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun int ret;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun if (has_acpi_companion(&pdev->dev))
505*4882a593Smuzhiyun return 0;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun ret = clk_set_rate(adpt->clk[EMAC_CLK_TX], 125000000);
508*4882a593Smuzhiyun if (ret)
509*4882a593Smuzhiyun return ret;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun ret = clk_prepare_enable(adpt->clk[EMAC_CLK_TX]);
512*4882a593Smuzhiyun if (ret)
513*4882a593Smuzhiyun return ret;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000);
516*4882a593Smuzhiyun if (ret)
517*4882a593Smuzhiyun return ret;
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun ret = clk_set_rate(adpt->clk[EMAC_CLK_MDIO], 25000000);
520*4882a593Smuzhiyun if (ret)
521*4882a593Smuzhiyun return ret;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun ret = clk_prepare_enable(adpt->clk[EMAC_CLK_MDIO]);
524*4882a593Smuzhiyun if (ret)
525*4882a593Smuzhiyun return ret;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun ret = clk_prepare_enable(adpt->clk[EMAC_CLK_RX]);
528*4882a593Smuzhiyun if (ret)
529*4882a593Smuzhiyun return ret;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun return clk_prepare_enable(adpt->clk[EMAC_CLK_SYS]);
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
emac_clks_teardown(struct emac_adapter * adpt)534*4882a593Smuzhiyun static void emac_clks_teardown(struct emac_adapter *adpt)
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun unsigned int i;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun for (i = 0; i < EMAC_CLK_CNT; i++)
540*4882a593Smuzhiyun clk_disable_unprepare(adpt->clk[i]);
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /* Get the resources */
emac_probe_resources(struct platform_device * pdev,struct emac_adapter * adpt)544*4882a593Smuzhiyun static int emac_probe_resources(struct platform_device *pdev,
545*4882a593Smuzhiyun struct emac_adapter *adpt)
546*4882a593Smuzhiyun {
547*4882a593Smuzhiyun struct net_device *netdev = adpt->netdev;
548*4882a593Smuzhiyun char maddr[ETH_ALEN];
549*4882a593Smuzhiyun int ret = 0;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun /* get mac address */
552*4882a593Smuzhiyun if (device_get_mac_address(&pdev->dev, maddr, ETH_ALEN))
553*4882a593Smuzhiyun ether_addr_copy(netdev->dev_addr, maddr);
554*4882a593Smuzhiyun else
555*4882a593Smuzhiyun eth_hw_addr_random(netdev);
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun /* Core 0 interrupt */
558*4882a593Smuzhiyun ret = platform_get_irq(pdev, 0);
559*4882a593Smuzhiyun if (ret < 0)
560*4882a593Smuzhiyun return ret;
561*4882a593Smuzhiyun adpt->irq.irq = ret;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun /* base register address */
564*4882a593Smuzhiyun adpt->base = devm_platform_ioremap_resource(pdev, 0);
565*4882a593Smuzhiyun if (IS_ERR(adpt->base))
566*4882a593Smuzhiyun return PTR_ERR(adpt->base);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun /* CSR register address */
569*4882a593Smuzhiyun adpt->csr = devm_platform_ioremap_resource(pdev, 1);
570*4882a593Smuzhiyun if (IS_ERR(adpt->csr))
571*4882a593Smuzhiyun return PTR_ERR(adpt->csr);
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun netdev->base_addr = (unsigned long)adpt->base;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun return 0;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun static const struct of_device_id emac_dt_match[] = {
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun .compatible = "qcom,fsm9900-emac",
581*4882a593Smuzhiyun },
582*4882a593Smuzhiyun {}
583*4882a593Smuzhiyun };
584*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, emac_dt_match);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_ACPI)
587*4882a593Smuzhiyun static const struct acpi_device_id emac_acpi_match[] = {
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun .id = "QCOM8070",
590*4882a593Smuzhiyun },
591*4882a593Smuzhiyun {}
592*4882a593Smuzhiyun };
593*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, emac_acpi_match);
594*4882a593Smuzhiyun #endif
595*4882a593Smuzhiyun
emac_probe(struct platform_device * pdev)596*4882a593Smuzhiyun static int emac_probe(struct platform_device *pdev)
597*4882a593Smuzhiyun {
598*4882a593Smuzhiyun struct net_device *netdev;
599*4882a593Smuzhiyun struct emac_adapter *adpt;
600*4882a593Smuzhiyun struct emac_sgmii *phy;
601*4882a593Smuzhiyun u16 devid, revid;
602*4882a593Smuzhiyun u32 reg;
603*4882a593Smuzhiyun int ret;
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun /* The TPD buffer address is limited to:
606*4882a593Smuzhiyun * 1. PTP: 45bits. (Driver doesn't support yet.)
607*4882a593Smuzhiyun * 2. NON-PTP: 46bits.
608*4882a593Smuzhiyun */
609*4882a593Smuzhiyun ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(46));
610*4882a593Smuzhiyun if (ret) {
611*4882a593Smuzhiyun dev_err(&pdev->dev, "could not set DMA mask\n");
612*4882a593Smuzhiyun return ret;
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun netdev = alloc_etherdev(sizeof(struct emac_adapter));
616*4882a593Smuzhiyun if (!netdev)
617*4882a593Smuzhiyun return -ENOMEM;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun dev_set_drvdata(&pdev->dev, netdev);
620*4882a593Smuzhiyun SET_NETDEV_DEV(netdev, &pdev->dev);
621*4882a593Smuzhiyun emac_set_ethtool_ops(netdev);
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun adpt = netdev_priv(netdev);
624*4882a593Smuzhiyun adpt->netdev = netdev;
625*4882a593Smuzhiyun adpt->msg_enable = EMAC_MSG_DEFAULT;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun phy = &adpt->phy;
628*4882a593Smuzhiyun atomic_set(&phy->decode_error_count, 0);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun mutex_init(&adpt->reset_lock);
631*4882a593Smuzhiyun spin_lock_init(&adpt->stats.lock);
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun adpt->irq.mask = RX_PKT_INT0 | IMR_NORMAL_MASK;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun ret = emac_probe_resources(pdev, adpt);
636*4882a593Smuzhiyun if (ret)
637*4882a593Smuzhiyun goto err_undo_netdev;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun /* initialize clocks */
640*4882a593Smuzhiyun ret = emac_clks_phase1_init(pdev, adpt);
641*4882a593Smuzhiyun if (ret) {
642*4882a593Smuzhiyun dev_err(&pdev->dev, "could not initialize clocks\n");
643*4882a593Smuzhiyun goto err_undo_netdev;
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun netdev->watchdog_timeo = EMAC_WATCHDOG_TIME;
647*4882a593Smuzhiyun netdev->irq = adpt->irq.irq;
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun netdev->netdev_ops = &emac_netdev_ops;
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun emac_init_adapter(adpt);
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun /* init external phy */
654*4882a593Smuzhiyun ret = emac_phy_config(pdev, adpt);
655*4882a593Smuzhiyun if (ret)
656*4882a593Smuzhiyun goto err_undo_clocks;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun /* init internal sgmii phy */
659*4882a593Smuzhiyun ret = emac_sgmii_config(pdev, adpt);
660*4882a593Smuzhiyun if (ret)
661*4882a593Smuzhiyun goto err_undo_mdiobus;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun /* enable clocks */
664*4882a593Smuzhiyun ret = emac_clks_phase2_init(pdev, adpt);
665*4882a593Smuzhiyun if (ret) {
666*4882a593Smuzhiyun dev_err(&pdev->dev, "could not initialize clocks\n");
667*4882a593Smuzhiyun goto err_undo_mdiobus;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun /* set hw features */
671*4882a593Smuzhiyun netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
672*4882a593Smuzhiyun NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
673*4882a593Smuzhiyun NETIF_F_HW_VLAN_CTAG_TX;
674*4882a593Smuzhiyun netdev->hw_features = netdev->features;
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun netdev->vlan_features |= NETIF_F_SG | NETIF_F_HW_CSUM |
677*4882a593Smuzhiyun NETIF_F_TSO | NETIF_F_TSO6;
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun /* MTU range: 46 - 9194 */
680*4882a593Smuzhiyun netdev->min_mtu = EMAC_MIN_ETH_FRAME_SIZE -
681*4882a593Smuzhiyun (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
682*4882a593Smuzhiyun netdev->max_mtu = EMAC_MAX_ETH_FRAME_SIZE -
683*4882a593Smuzhiyun (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun INIT_WORK(&adpt->work_thread, emac_work_thread);
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun /* Initialize queues */
688*4882a593Smuzhiyun emac_mac_rx_tx_ring_init_all(pdev, adpt);
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun netif_napi_add(netdev, &adpt->rx_q.napi, emac_napi_rtx,
691*4882a593Smuzhiyun NAPI_POLL_WEIGHT);
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun ret = register_netdev(netdev);
694*4882a593Smuzhiyun if (ret) {
695*4882a593Smuzhiyun dev_err(&pdev->dev, "could not register net device\n");
696*4882a593Smuzhiyun goto err_undo_napi;
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun reg = readl_relaxed(adpt->base + EMAC_DMA_MAS_CTRL);
700*4882a593Smuzhiyun devid = (reg & DEV_ID_NUM_BMSK) >> DEV_ID_NUM_SHFT;
701*4882a593Smuzhiyun revid = (reg & DEV_REV_NUM_BMSK) >> DEV_REV_NUM_SHFT;
702*4882a593Smuzhiyun reg = readl_relaxed(adpt->base + EMAC_CORE_HW_VERSION);
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun netif_info(adpt, probe, netdev,
705*4882a593Smuzhiyun "hardware id %d.%d, hardware version %d.%d.%d\n",
706*4882a593Smuzhiyun devid, revid,
707*4882a593Smuzhiyun (reg & MAJOR_BMSK) >> MAJOR_SHFT,
708*4882a593Smuzhiyun (reg & MINOR_BMSK) >> MINOR_SHFT,
709*4882a593Smuzhiyun (reg & STEP_BMSK) >> STEP_SHFT);
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun return 0;
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun err_undo_napi:
714*4882a593Smuzhiyun netif_napi_del(&adpt->rx_q.napi);
715*4882a593Smuzhiyun err_undo_mdiobus:
716*4882a593Smuzhiyun put_device(&adpt->phydev->mdio.dev);
717*4882a593Smuzhiyun mdiobus_unregister(adpt->mii_bus);
718*4882a593Smuzhiyun err_undo_clocks:
719*4882a593Smuzhiyun emac_clks_teardown(adpt);
720*4882a593Smuzhiyun err_undo_netdev:
721*4882a593Smuzhiyun free_netdev(netdev);
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun return ret;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
emac_remove(struct platform_device * pdev)726*4882a593Smuzhiyun static int emac_remove(struct platform_device *pdev)
727*4882a593Smuzhiyun {
728*4882a593Smuzhiyun struct net_device *netdev = dev_get_drvdata(&pdev->dev);
729*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun unregister_netdev(netdev);
732*4882a593Smuzhiyun netif_napi_del(&adpt->rx_q.napi);
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun emac_clks_teardown(adpt);
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun put_device(&adpt->phydev->mdio.dev);
737*4882a593Smuzhiyun mdiobus_unregister(adpt->mii_bus);
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun if (adpt->phy.digital)
740*4882a593Smuzhiyun iounmap(adpt->phy.digital);
741*4882a593Smuzhiyun iounmap(adpt->phy.base);
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun free_netdev(netdev);
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun return 0;
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun
emac_shutdown(struct platform_device * pdev)748*4882a593Smuzhiyun static void emac_shutdown(struct platform_device *pdev)
749*4882a593Smuzhiyun {
750*4882a593Smuzhiyun struct net_device *netdev = dev_get_drvdata(&pdev->dev);
751*4882a593Smuzhiyun struct emac_adapter *adpt = netdev_priv(netdev);
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun if (netdev->flags & IFF_UP) {
754*4882a593Smuzhiyun /* Closing the SGMII turns off its interrupts */
755*4882a593Smuzhiyun emac_sgmii_close(adpt);
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun /* Resetting the MAC turns off all DMA and its interrupts */
758*4882a593Smuzhiyun emac_mac_reset(adpt);
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun static struct platform_driver emac_platform_driver = {
763*4882a593Smuzhiyun .probe = emac_probe,
764*4882a593Smuzhiyun .remove = emac_remove,
765*4882a593Smuzhiyun .driver = {
766*4882a593Smuzhiyun .name = "qcom-emac",
767*4882a593Smuzhiyun .of_match_table = emac_dt_match,
768*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(emac_acpi_match),
769*4882a593Smuzhiyun },
770*4882a593Smuzhiyun .shutdown = emac_shutdown,
771*4882a593Smuzhiyun };
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun module_platform_driver(emac_platform_driver);
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
776*4882a593Smuzhiyun MODULE_ALIAS("platform:qcom-emac");
777