xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/qlogic/qede/qede_main.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2*4882a593Smuzhiyun /* QLogic qede NIC Driver
3*4882a593Smuzhiyun  * Copyright (c) 2015-2017  QLogic Corporation
4*4882a593Smuzhiyun  * Copyright (c) 2019-2020 Marvell International Ltd.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/crash_dump.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/pci.h>
10*4882a593Smuzhiyun #include <linux/version.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/netdevice.h>
13*4882a593Smuzhiyun #include <linux/etherdevice.h>
14*4882a593Smuzhiyun #include <linux/skbuff.h>
15*4882a593Smuzhiyun #include <linux/errno.h>
16*4882a593Smuzhiyun #include <linux/list.h>
17*4882a593Smuzhiyun #include <linux/string.h>
18*4882a593Smuzhiyun #include <linux/dma-mapping.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <asm/byteorder.h>
21*4882a593Smuzhiyun #include <asm/param.h>
22*4882a593Smuzhiyun #include <linux/io.h>
23*4882a593Smuzhiyun #include <linux/netdev_features.h>
24*4882a593Smuzhiyun #include <linux/udp.h>
25*4882a593Smuzhiyun #include <linux/tcp.h>
26*4882a593Smuzhiyun #include <net/udp_tunnel.h>
27*4882a593Smuzhiyun #include <linux/ip.h>
28*4882a593Smuzhiyun #include <net/ipv6.h>
29*4882a593Smuzhiyun #include <net/tcp.h>
30*4882a593Smuzhiyun #include <linux/if_ether.h>
31*4882a593Smuzhiyun #include <linux/if_vlan.h>
32*4882a593Smuzhiyun #include <linux/pkt_sched.h>
33*4882a593Smuzhiyun #include <linux/ethtool.h>
34*4882a593Smuzhiyun #include <linux/in.h>
35*4882a593Smuzhiyun #include <linux/random.h>
36*4882a593Smuzhiyun #include <net/ip6_checksum.h>
37*4882a593Smuzhiyun #include <linux/bitops.h>
38*4882a593Smuzhiyun #include <linux/vmalloc.h>
39*4882a593Smuzhiyun #include <linux/aer.h>
40*4882a593Smuzhiyun #include "qede.h"
41*4882a593Smuzhiyun #include "qede_ptp.h"
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun static char version[] =
44*4882a593Smuzhiyun 	"QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
47*4882a593Smuzhiyun MODULE_LICENSE("GPL");
48*4882a593Smuzhiyun MODULE_VERSION(DRV_MODULE_VERSION);
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun static uint debug;
51*4882a593Smuzhiyun module_param(debug, uint, 0);
52*4882a593Smuzhiyun MODULE_PARM_DESC(debug, " Default debug msglevel");
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun static const struct qed_eth_ops *qed_ops;
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define CHIP_NUM_57980S_40		0x1634
57*4882a593Smuzhiyun #define CHIP_NUM_57980S_10		0x1666
58*4882a593Smuzhiyun #define CHIP_NUM_57980S_MF		0x1636
59*4882a593Smuzhiyun #define CHIP_NUM_57980S_100		0x1644
60*4882a593Smuzhiyun #define CHIP_NUM_57980S_50		0x1654
61*4882a593Smuzhiyun #define CHIP_NUM_57980S_25		0x1656
62*4882a593Smuzhiyun #define CHIP_NUM_57980S_IOV		0x1664
63*4882a593Smuzhiyun #define CHIP_NUM_AH			0x8070
64*4882a593Smuzhiyun #define CHIP_NUM_AH_IOV			0x8090
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_NX2_57980E
67*4882a593Smuzhiyun #define PCI_DEVICE_ID_57980S_40		CHIP_NUM_57980S_40
68*4882a593Smuzhiyun #define PCI_DEVICE_ID_57980S_10		CHIP_NUM_57980S_10
69*4882a593Smuzhiyun #define PCI_DEVICE_ID_57980S_MF		CHIP_NUM_57980S_MF
70*4882a593Smuzhiyun #define PCI_DEVICE_ID_57980S_100	CHIP_NUM_57980S_100
71*4882a593Smuzhiyun #define PCI_DEVICE_ID_57980S_50		CHIP_NUM_57980S_50
72*4882a593Smuzhiyun #define PCI_DEVICE_ID_57980S_25		CHIP_NUM_57980S_25
73*4882a593Smuzhiyun #define PCI_DEVICE_ID_57980S_IOV	CHIP_NUM_57980S_IOV
74*4882a593Smuzhiyun #define PCI_DEVICE_ID_AH		CHIP_NUM_AH
75*4882a593Smuzhiyun #define PCI_DEVICE_ID_AH_IOV		CHIP_NUM_AH_IOV
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun enum qede_pci_private {
80*4882a593Smuzhiyun 	QEDE_PRIVATE_PF,
81*4882a593Smuzhiyun 	QEDE_PRIVATE_VF
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun static const struct pci_device_id qede_pci_tbl[] = {
85*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
86*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
87*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
88*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
89*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
90*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
91*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
92*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
93*4882a593Smuzhiyun #endif
94*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH), QEDE_PRIVATE_PF},
95*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
96*4882a593Smuzhiyun 	{PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH_IOV), QEDE_PRIVATE_VF},
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun 	{ 0 }
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
104*4882a593Smuzhiyun static pci_ers_result_t
105*4882a593Smuzhiyun qede_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #define TX_TIMEOUT		(5 * HZ)
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /* Utilize last protocol index for XDP */
110*4882a593Smuzhiyun #define XDP_PI	11
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun static void qede_remove(struct pci_dev *pdev);
113*4882a593Smuzhiyun static void qede_shutdown(struct pci_dev *pdev);
114*4882a593Smuzhiyun static void qede_link_update(void *dev, struct qed_link_output *link);
115*4882a593Smuzhiyun static void qede_schedule_recovery_handler(void *dev);
116*4882a593Smuzhiyun static void qede_recovery_handler(struct qede_dev *edev);
117*4882a593Smuzhiyun static void qede_schedule_hw_err_handler(void *dev,
118*4882a593Smuzhiyun 					 enum qed_hw_err_type err_type);
119*4882a593Smuzhiyun static void qede_get_eth_tlv_data(void *edev, void *data);
120*4882a593Smuzhiyun static void qede_get_generic_tlv_data(void *edev,
121*4882a593Smuzhiyun 				      struct qed_generic_tlvs *data);
122*4882a593Smuzhiyun static void qede_generic_hw_err_handler(struct qede_dev *edev);
123*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
qede_set_vf_vlan(struct net_device * ndev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)124*4882a593Smuzhiyun static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos,
125*4882a593Smuzhiyun 			    __be16 vlan_proto)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(ndev);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	if (vlan > 4095) {
130*4882a593Smuzhiyun 		DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
131*4882a593Smuzhiyun 		return -EINVAL;
132*4882a593Smuzhiyun 	}
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	if (vlan_proto != htons(ETH_P_8021Q))
135*4882a593Smuzhiyun 		return -EPROTONOSUPPORT;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
138*4882a593Smuzhiyun 		   vlan, vf);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
qede_set_vf_mac(struct net_device * ndev,int vfidx,u8 * mac)143*4882a593Smuzhiyun static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(ndev);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	DP_VERBOSE(edev, QED_MSG_IOV, "Setting MAC %pM to VF [%d]\n", mac, vfidx);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	if (!is_valid_ether_addr(mac)) {
150*4882a593Smuzhiyun 		DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
151*4882a593Smuzhiyun 		return -EINVAL;
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
qede_sriov_configure(struct pci_dev * pdev,int num_vfs_param)157*4882a593Smuzhiyun static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
160*4882a593Smuzhiyun 	struct qed_dev_info *qed_info = &edev->dev_info.common;
161*4882a593Smuzhiyun 	struct qed_update_vport_params *vport_params;
162*4882a593Smuzhiyun 	int rc;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	vport_params = vzalloc(sizeof(*vport_params));
165*4882a593Smuzhiyun 	if (!vport_params)
166*4882a593Smuzhiyun 		return -ENOMEM;
167*4882a593Smuzhiyun 	DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	/* Enable/Disable Tx switching for PF */
172*4882a593Smuzhiyun 	if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
173*4882a593Smuzhiyun 	    !qed_info->b_inter_pf_switch && qed_info->tx_switching) {
174*4882a593Smuzhiyun 		vport_params->vport_id = 0;
175*4882a593Smuzhiyun 		vport_params->update_tx_switching_flg = 1;
176*4882a593Smuzhiyun 		vport_params->tx_switching_flg = num_vfs_param ? 1 : 0;
177*4882a593Smuzhiyun 		edev->ops->vport_update(edev->cdev, vport_params);
178*4882a593Smuzhiyun 	}
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	vfree(vport_params);
181*4882a593Smuzhiyun 	return rc;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun #endif
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun static const struct pci_error_handlers qede_err_handler = {
186*4882a593Smuzhiyun 	.error_detected = qede_io_error_detected,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static struct pci_driver qede_pci_driver = {
190*4882a593Smuzhiyun 	.name = "qede",
191*4882a593Smuzhiyun 	.id_table = qede_pci_tbl,
192*4882a593Smuzhiyun 	.probe = qede_probe,
193*4882a593Smuzhiyun 	.remove = qede_remove,
194*4882a593Smuzhiyun 	.shutdown = qede_shutdown,
195*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
196*4882a593Smuzhiyun 	.sriov_configure = qede_sriov_configure,
197*4882a593Smuzhiyun #endif
198*4882a593Smuzhiyun 	.err_handler = &qede_err_handler,
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun static struct qed_eth_cb_ops qede_ll_ops = {
202*4882a593Smuzhiyun 	{
203*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
204*4882a593Smuzhiyun 		.arfs_filter_op = qede_arfs_filter_op,
205*4882a593Smuzhiyun #endif
206*4882a593Smuzhiyun 		.link_update = qede_link_update,
207*4882a593Smuzhiyun 		.schedule_recovery_handler = qede_schedule_recovery_handler,
208*4882a593Smuzhiyun 		.schedule_hw_err_handler = qede_schedule_hw_err_handler,
209*4882a593Smuzhiyun 		.get_generic_tlv_data = qede_get_generic_tlv_data,
210*4882a593Smuzhiyun 		.get_protocol_tlv_data = qede_get_eth_tlv_data,
211*4882a593Smuzhiyun 	},
212*4882a593Smuzhiyun 	.force_mac = qede_force_mac,
213*4882a593Smuzhiyun 	.ports_update = qede_udp_ports_update,
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
qede_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)216*4882a593Smuzhiyun static int qede_netdev_event(struct notifier_block *this, unsigned long event,
217*4882a593Smuzhiyun 			     void *ptr)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun 	struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
220*4882a593Smuzhiyun 	struct ethtool_drvinfo drvinfo;
221*4882a593Smuzhiyun 	struct qede_dev *edev;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	if (event != NETDEV_CHANGENAME && event != NETDEV_CHANGEADDR)
224*4882a593Smuzhiyun 		goto done;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	/* Check whether this is a qede device */
227*4882a593Smuzhiyun 	if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
228*4882a593Smuzhiyun 		goto done;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	memset(&drvinfo, 0, sizeof(drvinfo));
231*4882a593Smuzhiyun 	ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
232*4882a593Smuzhiyun 	if (strcmp(drvinfo.driver, "qede"))
233*4882a593Smuzhiyun 		goto done;
234*4882a593Smuzhiyun 	edev = netdev_priv(ndev);
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	switch (event) {
237*4882a593Smuzhiyun 	case NETDEV_CHANGENAME:
238*4882a593Smuzhiyun 		/* Notify qed of the name change */
239*4882a593Smuzhiyun 		if (!edev->ops || !edev->ops->common)
240*4882a593Smuzhiyun 			goto done;
241*4882a593Smuzhiyun 		edev->ops->common->set_name(edev->cdev, edev->ndev->name);
242*4882a593Smuzhiyun 		break;
243*4882a593Smuzhiyun 	case NETDEV_CHANGEADDR:
244*4882a593Smuzhiyun 		edev = netdev_priv(ndev);
245*4882a593Smuzhiyun 		qede_rdma_event_changeaddr(edev);
246*4882a593Smuzhiyun 		break;
247*4882a593Smuzhiyun 	}
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun done:
250*4882a593Smuzhiyun 	return NOTIFY_DONE;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun static struct notifier_block qede_netdev_notifier = {
254*4882a593Smuzhiyun 	.notifier_call = qede_netdev_event,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun static
qede_init(void)258*4882a593Smuzhiyun int __init qede_init(void)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	int ret;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	pr_info("qede_init: %s\n", version);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	qede_forced_speed_maps_init();
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	qed_ops = qed_get_eth_ops();
267*4882a593Smuzhiyun 	if (!qed_ops) {
268*4882a593Smuzhiyun 		pr_notice("Failed to get qed ethtool operations\n");
269*4882a593Smuzhiyun 		return -EINVAL;
270*4882a593Smuzhiyun 	}
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	/* Must register notifier before pci ops, since we might miss
273*4882a593Smuzhiyun 	 * interface rename after pci probe and netdev registration.
274*4882a593Smuzhiyun 	 */
275*4882a593Smuzhiyun 	ret = register_netdevice_notifier(&qede_netdev_notifier);
276*4882a593Smuzhiyun 	if (ret) {
277*4882a593Smuzhiyun 		pr_notice("Failed to register netdevice_notifier\n");
278*4882a593Smuzhiyun 		qed_put_eth_ops();
279*4882a593Smuzhiyun 		return -EINVAL;
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	ret = pci_register_driver(&qede_pci_driver);
283*4882a593Smuzhiyun 	if (ret) {
284*4882a593Smuzhiyun 		pr_notice("Failed to register driver\n");
285*4882a593Smuzhiyun 		unregister_netdevice_notifier(&qede_netdev_notifier);
286*4882a593Smuzhiyun 		qed_put_eth_ops();
287*4882a593Smuzhiyun 		return -EINVAL;
288*4882a593Smuzhiyun 	}
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	return 0;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun 
qede_cleanup(void)293*4882a593Smuzhiyun static void __exit qede_cleanup(void)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun 	if (debug & QED_LOG_INFO_MASK)
296*4882a593Smuzhiyun 		pr_info("qede_cleanup called\n");
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	unregister_netdevice_notifier(&qede_netdev_notifier);
299*4882a593Smuzhiyun 	pci_unregister_driver(&qede_pci_driver);
300*4882a593Smuzhiyun 	qed_put_eth_ops();
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun module_init(qede_init);
304*4882a593Smuzhiyun module_exit(qede_cleanup);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun static int qede_open(struct net_device *ndev);
307*4882a593Smuzhiyun static int qede_close(struct net_device *ndev);
308*4882a593Smuzhiyun 
qede_fill_by_demand_stats(struct qede_dev * edev)309*4882a593Smuzhiyun void qede_fill_by_demand_stats(struct qede_dev *edev)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun 	struct qede_stats_common *p_common = &edev->stats.common;
312*4882a593Smuzhiyun 	struct qed_eth_stats stats;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	edev->ops->get_vport_stats(edev->cdev, &stats);
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	p_common->no_buff_discards = stats.common.no_buff_discards;
317*4882a593Smuzhiyun 	p_common->packet_too_big_discard = stats.common.packet_too_big_discard;
318*4882a593Smuzhiyun 	p_common->ttl0_discard = stats.common.ttl0_discard;
319*4882a593Smuzhiyun 	p_common->rx_ucast_bytes = stats.common.rx_ucast_bytes;
320*4882a593Smuzhiyun 	p_common->rx_mcast_bytes = stats.common.rx_mcast_bytes;
321*4882a593Smuzhiyun 	p_common->rx_bcast_bytes = stats.common.rx_bcast_bytes;
322*4882a593Smuzhiyun 	p_common->rx_ucast_pkts = stats.common.rx_ucast_pkts;
323*4882a593Smuzhiyun 	p_common->rx_mcast_pkts = stats.common.rx_mcast_pkts;
324*4882a593Smuzhiyun 	p_common->rx_bcast_pkts = stats.common.rx_bcast_pkts;
325*4882a593Smuzhiyun 	p_common->mftag_filter_discards = stats.common.mftag_filter_discards;
326*4882a593Smuzhiyun 	p_common->mac_filter_discards = stats.common.mac_filter_discards;
327*4882a593Smuzhiyun 	p_common->gft_filter_drop = stats.common.gft_filter_drop;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	p_common->tx_ucast_bytes = stats.common.tx_ucast_bytes;
330*4882a593Smuzhiyun 	p_common->tx_mcast_bytes = stats.common.tx_mcast_bytes;
331*4882a593Smuzhiyun 	p_common->tx_bcast_bytes = stats.common.tx_bcast_bytes;
332*4882a593Smuzhiyun 	p_common->tx_ucast_pkts = stats.common.tx_ucast_pkts;
333*4882a593Smuzhiyun 	p_common->tx_mcast_pkts = stats.common.tx_mcast_pkts;
334*4882a593Smuzhiyun 	p_common->tx_bcast_pkts = stats.common.tx_bcast_pkts;
335*4882a593Smuzhiyun 	p_common->tx_err_drop_pkts = stats.common.tx_err_drop_pkts;
336*4882a593Smuzhiyun 	p_common->coalesced_pkts = stats.common.tpa_coalesced_pkts;
337*4882a593Smuzhiyun 	p_common->coalesced_events = stats.common.tpa_coalesced_events;
338*4882a593Smuzhiyun 	p_common->coalesced_aborts_num = stats.common.tpa_aborts_num;
339*4882a593Smuzhiyun 	p_common->non_coalesced_pkts = stats.common.tpa_not_coalesced_pkts;
340*4882a593Smuzhiyun 	p_common->coalesced_bytes = stats.common.tpa_coalesced_bytes;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	p_common->rx_64_byte_packets = stats.common.rx_64_byte_packets;
343*4882a593Smuzhiyun 	p_common->rx_65_to_127_byte_packets =
344*4882a593Smuzhiyun 	    stats.common.rx_65_to_127_byte_packets;
345*4882a593Smuzhiyun 	p_common->rx_128_to_255_byte_packets =
346*4882a593Smuzhiyun 	    stats.common.rx_128_to_255_byte_packets;
347*4882a593Smuzhiyun 	p_common->rx_256_to_511_byte_packets =
348*4882a593Smuzhiyun 	    stats.common.rx_256_to_511_byte_packets;
349*4882a593Smuzhiyun 	p_common->rx_512_to_1023_byte_packets =
350*4882a593Smuzhiyun 	    stats.common.rx_512_to_1023_byte_packets;
351*4882a593Smuzhiyun 	p_common->rx_1024_to_1518_byte_packets =
352*4882a593Smuzhiyun 	    stats.common.rx_1024_to_1518_byte_packets;
353*4882a593Smuzhiyun 	p_common->rx_crc_errors = stats.common.rx_crc_errors;
354*4882a593Smuzhiyun 	p_common->rx_mac_crtl_frames = stats.common.rx_mac_crtl_frames;
355*4882a593Smuzhiyun 	p_common->rx_pause_frames = stats.common.rx_pause_frames;
356*4882a593Smuzhiyun 	p_common->rx_pfc_frames = stats.common.rx_pfc_frames;
357*4882a593Smuzhiyun 	p_common->rx_align_errors = stats.common.rx_align_errors;
358*4882a593Smuzhiyun 	p_common->rx_carrier_errors = stats.common.rx_carrier_errors;
359*4882a593Smuzhiyun 	p_common->rx_oversize_packets = stats.common.rx_oversize_packets;
360*4882a593Smuzhiyun 	p_common->rx_jabbers = stats.common.rx_jabbers;
361*4882a593Smuzhiyun 	p_common->rx_undersize_packets = stats.common.rx_undersize_packets;
362*4882a593Smuzhiyun 	p_common->rx_fragments = stats.common.rx_fragments;
363*4882a593Smuzhiyun 	p_common->tx_64_byte_packets = stats.common.tx_64_byte_packets;
364*4882a593Smuzhiyun 	p_common->tx_65_to_127_byte_packets =
365*4882a593Smuzhiyun 	    stats.common.tx_65_to_127_byte_packets;
366*4882a593Smuzhiyun 	p_common->tx_128_to_255_byte_packets =
367*4882a593Smuzhiyun 	    stats.common.tx_128_to_255_byte_packets;
368*4882a593Smuzhiyun 	p_common->tx_256_to_511_byte_packets =
369*4882a593Smuzhiyun 	    stats.common.tx_256_to_511_byte_packets;
370*4882a593Smuzhiyun 	p_common->tx_512_to_1023_byte_packets =
371*4882a593Smuzhiyun 	    stats.common.tx_512_to_1023_byte_packets;
372*4882a593Smuzhiyun 	p_common->tx_1024_to_1518_byte_packets =
373*4882a593Smuzhiyun 	    stats.common.tx_1024_to_1518_byte_packets;
374*4882a593Smuzhiyun 	p_common->tx_pause_frames = stats.common.tx_pause_frames;
375*4882a593Smuzhiyun 	p_common->tx_pfc_frames = stats.common.tx_pfc_frames;
376*4882a593Smuzhiyun 	p_common->brb_truncates = stats.common.brb_truncates;
377*4882a593Smuzhiyun 	p_common->brb_discards = stats.common.brb_discards;
378*4882a593Smuzhiyun 	p_common->tx_mac_ctrl_frames = stats.common.tx_mac_ctrl_frames;
379*4882a593Smuzhiyun 	p_common->link_change_count = stats.common.link_change_count;
380*4882a593Smuzhiyun 	p_common->ptp_skip_txts = edev->ptp_skip_txts;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	if (QEDE_IS_BB(edev)) {
383*4882a593Smuzhiyun 		struct qede_stats_bb *p_bb = &edev->stats.bb;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 		p_bb->rx_1519_to_1522_byte_packets =
386*4882a593Smuzhiyun 		    stats.bb.rx_1519_to_1522_byte_packets;
387*4882a593Smuzhiyun 		p_bb->rx_1519_to_2047_byte_packets =
388*4882a593Smuzhiyun 		    stats.bb.rx_1519_to_2047_byte_packets;
389*4882a593Smuzhiyun 		p_bb->rx_2048_to_4095_byte_packets =
390*4882a593Smuzhiyun 		    stats.bb.rx_2048_to_4095_byte_packets;
391*4882a593Smuzhiyun 		p_bb->rx_4096_to_9216_byte_packets =
392*4882a593Smuzhiyun 		    stats.bb.rx_4096_to_9216_byte_packets;
393*4882a593Smuzhiyun 		p_bb->rx_9217_to_16383_byte_packets =
394*4882a593Smuzhiyun 		    stats.bb.rx_9217_to_16383_byte_packets;
395*4882a593Smuzhiyun 		p_bb->tx_1519_to_2047_byte_packets =
396*4882a593Smuzhiyun 		    stats.bb.tx_1519_to_2047_byte_packets;
397*4882a593Smuzhiyun 		p_bb->tx_2048_to_4095_byte_packets =
398*4882a593Smuzhiyun 		    stats.bb.tx_2048_to_4095_byte_packets;
399*4882a593Smuzhiyun 		p_bb->tx_4096_to_9216_byte_packets =
400*4882a593Smuzhiyun 		    stats.bb.tx_4096_to_9216_byte_packets;
401*4882a593Smuzhiyun 		p_bb->tx_9217_to_16383_byte_packets =
402*4882a593Smuzhiyun 		    stats.bb.tx_9217_to_16383_byte_packets;
403*4882a593Smuzhiyun 		p_bb->tx_lpi_entry_count = stats.bb.tx_lpi_entry_count;
404*4882a593Smuzhiyun 		p_bb->tx_total_collisions = stats.bb.tx_total_collisions;
405*4882a593Smuzhiyun 	} else {
406*4882a593Smuzhiyun 		struct qede_stats_ah *p_ah = &edev->stats.ah;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 		p_ah->rx_1519_to_max_byte_packets =
409*4882a593Smuzhiyun 		    stats.ah.rx_1519_to_max_byte_packets;
410*4882a593Smuzhiyun 		p_ah->tx_1519_to_max_byte_packets =
411*4882a593Smuzhiyun 		    stats.ah.tx_1519_to_max_byte_packets;
412*4882a593Smuzhiyun 	}
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun 
qede_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)415*4882a593Smuzhiyun static void qede_get_stats64(struct net_device *dev,
416*4882a593Smuzhiyun 			     struct rtnl_link_stats64 *stats)
417*4882a593Smuzhiyun {
418*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
419*4882a593Smuzhiyun 	struct qede_stats_common *p_common;
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	qede_fill_by_demand_stats(edev);
422*4882a593Smuzhiyun 	p_common = &edev->stats.common;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	stats->rx_packets = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
425*4882a593Smuzhiyun 			    p_common->rx_bcast_pkts;
426*4882a593Smuzhiyun 	stats->tx_packets = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
427*4882a593Smuzhiyun 			    p_common->tx_bcast_pkts;
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	stats->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
430*4882a593Smuzhiyun 			  p_common->rx_bcast_bytes;
431*4882a593Smuzhiyun 	stats->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
432*4882a593Smuzhiyun 			  p_common->tx_bcast_bytes;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	stats->tx_errors = p_common->tx_err_drop_pkts;
435*4882a593Smuzhiyun 	stats->multicast = p_common->rx_mcast_pkts + p_common->rx_bcast_pkts;
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	stats->rx_fifo_errors = p_common->no_buff_discards;
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	if (QEDE_IS_BB(edev))
440*4882a593Smuzhiyun 		stats->collisions = edev->stats.bb.tx_total_collisions;
441*4882a593Smuzhiyun 	stats->rx_crc_errors = p_common->rx_crc_errors;
442*4882a593Smuzhiyun 	stats->rx_frame_errors = p_common->rx_align_errors;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
qede_get_vf_config(struct net_device * dev,int vfidx,struct ifla_vf_info * ivi)446*4882a593Smuzhiyun static int qede_get_vf_config(struct net_device *dev, int vfidx,
447*4882a593Smuzhiyun 			      struct ifla_vf_info *ivi)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	if (!edev->ops)
452*4882a593Smuzhiyun 		return -EINVAL;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun 
qede_set_vf_rate(struct net_device * dev,int vfidx,int min_tx_rate,int max_tx_rate)457*4882a593Smuzhiyun static int qede_set_vf_rate(struct net_device *dev, int vfidx,
458*4882a593Smuzhiyun 			    int min_tx_rate, int max_tx_rate)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
463*4882a593Smuzhiyun 					max_tx_rate);
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun 
qede_set_vf_spoofchk(struct net_device * dev,int vfidx,bool val)466*4882a593Smuzhiyun static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	if (!edev->ops)
471*4882a593Smuzhiyun 		return -EINVAL;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun 
qede_set_vf_link_state(struct net_device * dev,int vfidx,int link_state)476*4882a593Smuzhiyun static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
477*4882a593Smuzhiyun 				  int link_state)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	if (!edev->ops)
482*4882a593Smuzhiyun 		return -EINVAL;
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun 
qede_set_vf_trust(struct net_device * dev,int vfidx,bool setting)487*4882a593Smuzhiyun static int qede_set_vf_trust(struct net_device *dev, int vfidx, bool setting)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	if (!edev->ops)
492*4882a593Smuzhiyun 		return -EINVAL;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	return edev->ops->iov->set_trust(edev->cdev, vfidx, setting);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun #endif
497*4882a593Smuzhiyun 
qede_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)498*4882a593Smuzhiyun static int qede_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	if (!netif_running(dev))
503*4882a593Smuzhiyun 		return -EAGAIN;
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	switch (cmd) {
506*4882a593Smuzhiyun 	case SIOCSHWTSTAMP:
507*4882a593Smuzhiyun 		return qede_ptp_hw_ts(edev, ifr);
508*4882a593Smuzhiyun 	default:
509*4882a593Smuzhiyun 		DP_VERBOSE(edev, QED_MSG_DEBUG,
510*4882a593Smuzhiyun 			   "default IOCTL cmd 0x%x\n", cmd);
511*4882a593Smuzhiyun 		return -EOPNOTSUPP;
512*4882a593Smuzhiyun 	}
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	return 0;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun 
qede_tx_log_print(struct qede_dev * edev,struct qede_tx_queue * txq)517*4882a593Smuzhiyun static void qede_tx_log_print(struct qede_dev *edev, struct qede_tx_queue *txq)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun 	DP_NOTICE(edev,
520*4882a593Smuzhiyun 		  "Txq[%d]: FW cons [host] %04x, SW cons %04x, SW prod %04x [Jiffies %lu]\n",
521*4882a593Smuzhiyun 		  txq->index, le16_to_cpu(*txq->hw_cons_ptr),
522*4882a593Smuzhiyun 		  qed_chain_get_cons_idx(&txq->tx_pbl),
523*4882a593Smuzhiyun 		  qed_chain_get_prod_idx(&txq->tx_pbl),
524*4882a593Smuzhiyun 		  jiffies);
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
qede_tx_timeout(struct net_device * dev,unsigned int txqueue)527*4882a593Smuzhiyun static void qede_tx_timeout(struct net_device *dev, unsigned int txqueue)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
530*4882a593Smuzhiyun 	struct qede_tx_queue *txq;
531*4882a593Smuzhiyun 	int cos;
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 	netif_carrier_off(dev);
534*4882a593Smuzhiyun 	DP_NOTICE(edev, "TX timeout on queue %u!\n", txqueue);
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	if (!(edev->fp_array[txqueue].type & QEDE_FASTPATH_TX))
537*4882a593Smuzhiyun 		return;
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	for_each_cos_in_txq(edev, cos) {
540*4882a593Smuzhiyun 		txq = &edev->fp_array[txqueue].txq[cos];
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 		if (qed_chain_get_cons_idx(&txq->tx_pbl) !=
543*4882a593Smuzhiyun 		    qed_chain_get_prod_idx(&txq->tx_pbl))
544*4882a593Smuzhiyun 			qede_tx_log_print(edev, txq);
545*4882a593Smuzhiyun 	}
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	if (IS_VF(edev))
548*4882a593Smuzhiyun 		return;
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	if (test_and_set_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags) ||
551*4882a593Smuzhiyun 	    edev->state == QEDE_STATE_RECOVERY) {
552*4882a593Smuzhiyun 		DP_INFO(edev,
553*4882a593Smuzhiyun 			"Avoid handling a Tx timeout while another HW error is being handled\n");
554*4882a593Smuzhiyun 		return;
555*4882a593Smuzhiyun 	}
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	set_bit(QEDE_ERR_GET_DBG_INFO, &edev->err_flags);
558*4882a593Smuzhiyun 	set_bit(QEDE_SP_HW_ERR, &edev->sp_flags);
559*4882a593Smuzhiyun 	schedule_delayed_work(&edev->sp_task, 0);
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun 
qede_setup_tc(struct net_device * ndev,u8 num_tc)562*4882a593Smuzhiyun static int qede_setup_tc(struct net_device *ndev, u8 num_tc)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(ndev);
565*4882a593Smuzhiyun 	int cos, count, offset;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	if (num_tc > edev->dev_info.num_tc)
568*4882a593Smuzhiyun 		return -EINVAL;
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	netdev_reset_tc(ndev);
571*4882a593Smuzhiyun 	netdev_set_num_tc(ndev, num_tc);
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	for_each_cos_in_txq(edev, cos) {
574*4882a593Smuzhiyun 		count = QEDE_TSS_COUNT(edev);
575*4882a593Smuzhiyun 		offset = cos * QEDE_TSS_COUNT(edev);
576*4882a593Smuzhiyun 		netdev_set_tc_queue(ndev, cos, count, offset);
577*4882a593Smuzhiyun 	}
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	return 0;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun static int
qede_set_flower(struct qede_dev * edev,struct flow_cls_offload * f,__be16 proto)583*4882a593Smuzhiyun qede_set_flower(struct qede_dev *edev, struct flow_cls_offload *f,
584*4882a593Smuzhiyun 		__be16 proto)
585*4882a593Smuzhiyun {
586*4882a593Smuzhiyun 	switch (f->command) {
587*4882a593Smuzhiyun 	case FLOW_CLS_REPLACE:
588*4882a593Smuzhiyun 		return qede_add_tc_flower_fltr(edev, proto, f);
589*4882a593Smuzhiyun 	case FLOW_CLS_DESTROY:
590*4882a593Smuzhiyun 		return qede_delete_flow_filter(edev, f->cookie);
591*4882a593Smuzhiyun 	default:
592*4882a593Smuzhiyun 		return -EOPNOTSUPP;
593*4882a593Smuzhiyun 	}
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun 
qede_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)596*4882a593Smuzhiyun static int qede_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
597*4882a593Smuzhiyun 				  void *cb_priv)
598*4882a593Smuzhiyun {
599*4882a593Smuzhiyun 	struct flow_cls_offload *f;
600*4882a593Smuzhiyun 	struct qede_dev *edev = cb_priv;
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	if (!tc_cls_can_offload_and_chain0(edev->ndev, type_data))
603*4882a593Smuzhiyun 		return -EOPNOTSUPP;
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 	switch (type) {
606*4882a593Smuzhiyun 	case TC_SETUP_CLSFLOWER:
607*4882a593Smuzhiyun 		f = type_data;
608*4882a593Smuzhiyun 		return qede_set_flower(edev, f, f->common.protocol);
609*4882a593Smuzhiyun 	default:
610*4882a593Smuzhiyun 		return -EOPNOTSUPP;
611*4882a593Smuzhiyun 	}
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun static LIST_HEAD(qede_block_cb_list);
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun static int
qede_setup_tc_offload(struct net_device * dev,enum tc_setup_type type,void * type_data)617*4882a593Smuzhiyun qede_setup_tc_offload(struct net_device *dev, enum tc_setup_type type,
618*4882a593Smuzhiyun 		      void *type_data)
619*4882a593Smuzhiyun {
620*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
621*4882a593Smuzhiyun 	struct tc_mqprio_qopt *mqprio;
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	switch (type) {
624*4882a593Smuzhiyun 	case TC_SETUP_BLOCK:
625*4882a593Smuzhiyun 		return flow_block_cb_setup_simple(type_data,
626*4882a593Smuzhiyun 						  &qede_block_cb_list,
627*4882a593Smuzhiyun 						  qede_setup_tc_block_cb,
628*4882a593Smuzhiyun 						  edev, edev, true);
629*4882a593Smuzhiyun 	case TC_SETUP_QDISC_MQPRIO:
630*4882a593Smuzhiyun 		mqprio = type_data;
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 		mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
633*4882a593Smuzhiyun 		return qede_setup_tc(dev, mqprio->num_tc);
634*4882a593Smuzhiyun 	default:
635*4882a593Smuzhiyun 		return -EOPNOTSUPP;
636*4882a593Smuzhiyun 	}
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun static const struct net_device_ops qede_netdev_ops = {
640*4882a593Smuzhiyun 	.ndo_open		= qede_open,
641*4882a593Smuzhiyun 	.ndo_stop		= qede_close,
642*4882a593Smuzhiyun 	.ndo_start_xmit		= qede_start_xmit,
643*4882a593Smuzhiyun 	.ndo_select_queue	= qede_select_queue,
644*4882a593Smuzhiyun 	.ndo_set_rx_mode	= qede_set_rx_mode,
645*4882a593Smuzhiyun 	.ndo_set_mac_address	= qede_set_mac_addr,
646*4882a593Smuzhiyun 	.ndo_validate_addr	= eth_validate_addr,
647*4882a593Smuzhiyun 	.ndo_change_mtu		= qede_change_mtu,
648*4882a593Smuzhiyun 	.ndo_do_ioctl		= qede_ioctl,
649*4882a593Smuzhiyun 	.ndo_tx_timeout		= qede_tx_timeout,
650*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
651*4882a593Smuzhiyun 	.ndo_set_vf_mac		= qede_set_vf_mac,
652*4882a593Smuzhiyun 	.ndo_set_vf_vlan	= qede_set_vf_vlan,
653*4882a593Smuzhiyun 	.ndo_set_vf_trust	= qede_set_vf_trust,
654*4882a593Smuzhiyun #endif
655*4882a593Smuzhiyun 	.ndo_vlan_rx_add_vid	= qede_vlan_rx_add_vid,
656*4882a593Smuzhiyun 	.ndo_vlan_rx_kill_vid	= qede_vlan_rx_kill_vid,
657*4882a593Smuzhiyun 	.ndo_fix_features	= qede_fix_features,
658*4882a593Smuzhiyun 	.ndo_set_features	= qede_set_features,
659*4882a593Smuzhiyun 	.ndo_get_stats64	= qede_get_stats64,
660*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
661*4882a593Smuzhiyun 	.ndo_set_vf_link_state	= qede_set_vf_link_state,
662*4882a593Smuzhiyun 	.ndo_set_vf_spoofchk	= qede_set_vf_spoofchk,
663*4882a593Smuzhiyun 	.ndo_get_vf_config	= qede_get_vf_config,
664*4882a593Smuzhiyun 	.ndo_set_vf_rate	= qede_set_vf_rate,
665*4882a593Smuzhiyun #endif
666*4882a593Smuzhiyun 	.ndo_udp_tunnel_add	= udp_tunnel_nic_add_port,
667*4882a593Smuzhiyun 	.ndo_udp_tunnel_del	= udp_tunnel_nic_del_port,
668*4882a593Smuzhiyun 	.ndo_features_check	= qede_features_check,
669*4882a593Smuzhiyun 	.ndo_bpf		= qede_xdp,
670*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
671*4882a593Smuzhiyun 	.ndo_rx_flow_steer	= qede_rx_flow_steer,
672*4882a593Smuzhiyun #endif
673*4882a593Smuzhiyun 	.ndo_xdp_xmit		= qede_xdp_transmit,
674*4882a593Smuzhiyun 	.ndo_setup_tc		= qede_setup_tc_offload,
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun static const struct net_device_ops qede_netdev_vf_ops = {
678*4882a593Smuzhiyun 	.ndo_open		= qede_open,
679*4882a593Smuzhiyun 	.ndo_stop		= qede_close,
680*4882a593Smuzhiyun 	.ndo_start_xmit		= qede_start_xmit,
681*4882a593Smuzhiyun 	.ndo_select_queue	= qede_select_queue,
682*4882a593Smuzhiyun 	.ndo_set_rx_mode	= qede_set_rx_mode,
683*4882a593Smuzhiyun 	.ndo_set_mac_address	= qede_set_mac_addr,
684*4882a593Smuzhiyun 	.ndo_validate_addr	= eth_validate_addr,
685*4882a593Smuzhiyun 	.ndo_change_mtu		= qede_change_mtu,
686*4882a593Smuzhiyun 	.ndo_vlan_rx_add_vid	= qede_vlan_rx_add_vid,
687*4882a593Smuzhiyun 	.ndo_vlan_rx_kill_vid	= qede_vlan_rx_kill_vid,
688*4882a593Smuzhiyun 	.ndo_fix_features	= qede_fix_features,
689*4882a593Smuzhiyun 	.ndo_set_features	= qede_set_features,
690*4882a593Smuzhiyun 	.ndo_get_stats64	= qede_get_stats64,
691*4882a593Smuzhiyun 	.ndo_udp_tunnel_add	= udp_tunnel_nic_add_port,
692*4882a593Smuzhiyun 	.ndo_udp_tunnel_del	= udp_tunnel_nic_del_port,
693*4882a593Smuzhiyun 	.ndo_features_check	= qede_features_check,
694*4882a593Smuzhiyun };
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun static const struct net_device_ops qede_netdev_vf_xdp_ops = {
697*4882a593Smuzhiyun 	.ndo_open		= qede_open,
698*4882a593Smuzhiyun 	.ndo_stop		= qede_close,
699*4882a593Smuzhiyun 	.ndo_start_xmit		= qede_start_xmit,
700*4882a593Smuzhiyun 	.ndo_select_queue	= qede_select_queue,
701*4882a593Smuzhiyun 	.ndo_set_rx_mode	= qede_set_rx_mode,
702*4882a593Smuzhiyun 	.ndo_set_mac_address	= qede_set_mac_addr,
703*4882a593Smuzhiyun 	.ndo_validate_addr	= eth_validate_addr,
704*4882a593Smuzhiyun 	.ndo_change_mtu		= qede_change_mtu,
705*4882a593Smuzhiyun 	.ndo_vlan_rx_add_vid	= qede_vlan_rx_add_vid,
706*4882a593Smuzhiyun 	.ndo_vlan_rx_kill_vid	= qede_vlan_rx_kill_vid,
707*4882a593Smuzhiyun 	.ndo_fix_features	= qede_fix_features,
708*4882a593Smuzhiyun 	.ndo_set_features	= qede_set_features,
709*4882a593Smuzhiyun 	.ndo_get_stats64	= qede_get_stats64,
710*4882a593Smuzhiyun 	.ndo_udp_tunnel_add	= udp_tunnel_nic_add_port,
711*4882a593Smuzhiyun 	.ndo_udp_tunnel_del	= udp_tunnel_nic_del_port,
712*4882a593Smuzhiyun 	.ndo_features_check	= qede_features_check,
713*4882a593Smuzhiyun 	.ndo_bpf		= qede_xdp,
714*4882a593Smuzhiyun 	.ndo_xdp_xmit		= qede_xdp_transmit,
715*4882a593Smuzhiyun };
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun /* -------------------------------------------------------------------------
718*4882a593Smuzhiyun  * START OF PROBE / REMOVE
719*4882a593Smuzhiyun  * -------------------------------------------------------------------------
720*4882a593Smuzhiyun  */
721*4882a593Smuzhiyun 
qede_alloc_etherdev(struct qed_dev * cdev,struct pci_dev * pdev,struct qed_dev_eth_info * info,u32 dp_module,u8 dp_level)722*4882a593Smuzhiyun static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
723*4882a593Smuzhiyun 					    struct pci_dev *pdev,
724*4882a593Smuzhiyun 					    struct qed_dev_eth_info *info,
725*4882a593Smuzhiyun 					    u32 dp_module, u8 dp_level)
726*4882a593Smuzhiyun {
727*4882a593Smuzhiyun 	struct net_device *ndev;
728*4882a593Smuzhiyun 	struct qede_dev *edev;
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun 	ndev = alloc_etherdev_mqs(sizeof(*edev),
731*4882a593Smuzhiyun 				  info->num_queues * info->num_tc,
732*4882a593Smuzhiyun 				  info->num_queues);
733*4882a593Smuzhiyun 	if (!ndev) {
734*4882a593Smuzhiyun 		pr_err("etherdev allocation failed\n");
735*4882a593Smuzhiyun 		return NULL;
736*4882a593Smuzhiyun 	}
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun 	edev = netdev_priv(ndev);
739*4882a593Smuzhiyun 	edev->ndev = ndev;
740*4882a593Smuzhiyun 	edev->cdev = cdev;
741*4882a593Smuzhiyun 	edev->pdev = pdev;
742*4882a593Smuzhiyun 	edev->dp_module = dp_module;
743*4882a593Smuzhiyun 	edev->dp_level = dp_level;
744*4882a593Smuzhiyun 	edev->ops = qed_ops;
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun 	if (is_kdump_kernel()) {
747*4882a593Smuzhiyun 		edev->q_num_rx_buffers = NUM_RX_BDS_KDUMP_MIN;
748*4882a593Smuzhiyun 		edev->q_num_tx_buffers = NUM_TX_BDS_KDUMP_MIN;
749*4882a593Smuzhiyun 	} else {
750*4882a593Smuzhiyun 		edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
751*4882a593Smuzhiyun 		edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
752*4882a593Smuzhiyun 	}
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun 	DP_INFO(edev, "Allocated netdev with %d tx queues and %d rx queues\n",
755*4882a593Smuzhiyun 		info->num_queues, info->num_queues);
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	SET_NETDEV_DEV(ndev, &pdev->dev);
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 	memset(&edev->stats, 0, sizeof(edev->stats));
760*4882a593Smuzhiyun 	memcpy(&edev->dev_info, info, sizeof(*info));
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun 	/* As ethtool doesn't have the ability to show WoL behavior as
763*4882a593Smuzhiyun 	 * 'default', if device supports it declare it's enabled.
764*4882a593Smuzhiyun 	 */
765*4882a593Smuzhiyun 	if (edev->dev_info.common.wol_support)
766*4882a593Smuzhiyun 		edev->wol_enabled = true;
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 	INIT_LIST_HEAD(&edev->vlan_list);
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	return edev;
771*4882a593Smuzhiyun }
772*4882a593Smuzhiyun 
qede_init_ndev(struct qede_dev * edev)773*4882a593Smuzhiyun static void qede_init_ndev(struct qede_dev *edev)
774*4882a593Smuzhiyun {
775*4882a593Smuzhiyun 	struct net_device *ndev = edev->ndev;
776*4882a593Smuzhiyun 	struct pci_dev *pdev = edev->pdev;
777*4882a593Smuzhiyun 	bool udp_tunnel_enable = false;
778*4882a593Smuzhiyun 	netdev_features_t hw_features;
779*4882a593Smuzhiyun 
780*4882a593Smuzhiyun 	pci_set_drvdata(pdev, ndev);
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun 	ndev->mem_start = edev->dev_info.common.pci_mem_start;
783*4882a593Smuzhiyun 	ndev->base_addr = ndev->mem_start;
784*4882a593Smuzhiyun 	ndev->mem_end = edev->dev_info.common.pci_mem_end;
785*4882a593Smuzhiyun 	ndev->irq = edev->dev_info.common.pci_irq;
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 	ndev->watchdog_timeo = TX_TIMEOUT;
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun 	if (IS_VF(edev)) {
790*4882a593Smuzhiyun 		if (edev->dev_info.xdp_supported)
791*4882a593Smuzhiyun 			ndev->netdev_ops = &qede_netdev_vf_xdp_ops;
792*4882a593Smuzhiyun 		else
793*4882a593Smuzhiyun 			ndev->netdev_ops = &qede_netdev_vf_ops;
794*4882a593Smuzhiyun 	} else {
795*4882a593Smuzhiyun 		ndev->netdev_ops = &qede_netdev_ops;
796*4882a593Smuzhiyun 	}
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 	qede_set_ethtool_ops(ndev);
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun 	ndev->priv_flags |= IFF_UNICAST_FLT;
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	/* user-changeble features */
803*4882a593Smuzhiyun 	hw_features = NETIF_F_GRO | NETIF_F_GRO_HW | NETIF_F_SG |
804*4882a593Smuzhiyun 		      NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
805*4882a593Smuzhiyun 		      NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_TC;
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 	if (edev->dev_info.common.b_arfs_capable)
808*4882a593Smuzhiyun 		hw_features |= NETIF_F_NTUPLE;
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	if (edev->dev_info.common.vxlan_enable ||
811*4882a593Smuzhiyun 	    edev->dev_info.common.geneve_enable)
812*4882a593Smuzhiyun 		udp_tunnel_enable = true;
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	if (udp_tunnel_enable || edev->dev_info.common.gre_enable) {
815*4882a593Smuzhiyun 		hw_features |= NETIF_F_TSO_ECN;
816*4882a593Smuzhiyun 		ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
817*4882a593Smuzhiyun 					NETIF_F_SG | NETIF_F_TSO |
818*4882a593Smuzhiyun 					NETIF_F_TSO_ECN | NETIF_F_TSO6 |
819*4882a593Smuzhiyun 					NETIF_F_RXCSUM;
820*4882a593Smuzhiyun 	}
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	if (udp_tunnel_enable) {
823*4882a593Smuzhiyun 		hw_features |= (NETIF_F_GSO_UDP_TUNNEL |
824*4882a593Smuzhiyun 				NETIF_F_GSO_UDP_TUNNEL_CSUM);
825*4882a593Smuzhiyun 		ndev->hw_enc_features |= (NETIF_F_GSO_UDP_TUNNEL |
826*4882a593Smuzhiyun 					  NETIF_F_GSO_UDP_TUNNEL_CSUM);
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 		qede_set_udp_tunnels(edev);
829*4882a593Smuzhiyun 	}
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun 	if (edev->dev_info.common.gre_enable) {
832*4882a593Smuzhiyun 		hw_features |= (NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM);
833*4882a593Smuzhiyun 		ndev->hw_enc_features |= (NETIF_F_GSO_GRE |
834*4882a593Smuzhiyun 					  NETIF_F_GSO_GRE_CSUM);
835*4882a593Smuzhiyun 	}
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 	ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
838*4882a593Smuzhiyun 			      NETIF_F_HIGHDMA;
839*4882a593Smuzhiyun 	ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
840*4882a593Smuzhiyun 			 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
841*4882a593Smuzhiyun 			 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 	ndev->hw_features = hw_features;
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 	/* MTU range: 46 - 9600 */
846*4882a593Smuzhiyun 	ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
847*4882a593Smuzhiyun 	ndev->max_mtu = QEDE_MAX_JUMBO_PACKET_SIZE;
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	/* Set network device HW mac */
850*4882a593Smuzhiyun 	ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 	ndev->mtu = edev->dev_info.common.mtu;
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun /* This function converts from 32b param to two params of level and module
856*4882a593Smuzhiyun  * Input 32b decoding:
857*4882a593Smuzhiyun  * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
858*4882a593Smuzhiyun  * 'happy' flow, e.g. memory allocation failed.
859*4882a593Smuzhiyun  * b30 - enable all INFO prints. INFO prints are for major steps in the flow
860*4882a593Smuzhiyun  * and provide important parameters.
861*4882a593Smuzhiyun  * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
862*4882a593Smuzhiyun  * module. VERBOSE prints are for tracking the specific flow in low level.
863*4882a593Smuzhiyun  *
864*4882a593Smuzhiyun  * Notice that the level should be that of the lowest required logs.
865*4882a593Smuzhiyun  */
qede_config_debug(uint debug,u32 * p_dp_module,u8 * p_dp_level)866*4882a593Smuzhiyun void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
867*4882a593Smuzhiyun {
868*4882a593Smuzhiyun 	*p_dp_level = QED_LEVEL_NOTICE;
869*4882a593Smuzhiyun 	*p_dp_module = 0;
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun 	if (debug & QED_LOG_VERBOSE_MASK) {
872*4882a593Smuzhiyun 		*p_dp_level = QED_LEVEL_VERBOSE;
873*4882a593Smuzhiyun 		*p_dp_module = (debug & 0x3FFFFFFF);
874*4882a593Smuzhiyun 	} else if (debug & QED_LOG_INFO_MASK) {
875*4882a593Smuzhiyun 		*p_dp_level = QED_LEVEL_INFO;
876*4882a593Smuzhiyun 	} else if (debug & QED_LOG_NOTICE_MASK) {
877*4882a593Smuzhiyun 		*p_dp_level = QED_LEVEL_NOTICE;
878*4882a593Smuzhiyun 	}
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun 
qede_free_fp_array(struct qede_dev * edev)881*4882a593Smuzhiyun static void qede_free_fp_array(struct qede_dev *edev)
882*4882a593Smuzhiyun {
883*4882a593Smuzhiyun 	if (edev->fp_array) {
884*4882a593Smuzhiyun 		struct qede_fastpath *fp;
885*4882a593Smuzhiyun 		int i;
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 		for_each_queue(i) {
888*4882a593Smuzhiyun 			fp = &edev->fp_array[i];
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun 			kfree(fp->sb_info);
891*4882a593Smuzhiyun 			/* Handle mem alloc failure case where qede_init_fp
892*4882a593Smuzhiyun 			 * didn't register xdp_rxq_info yet.
893*4882a593Smuzhiyun 			 * Implicit only (fp->type & QEDE_FASTPATH_RX)
894*4882a593Smuzhiyun 			 */
895*4882a593Smuzhiyun 			if (fp->rxq && xdp_rxq_info_is_reg(&fp->rxq->xdp_rxq))
896*4882a593Smuzhiyun 				xdp_rxq_info_unreg(&fp->rxq->xdp_rxq);
897*4882a593Smuzhiyun 			kfree(fp->rxq);
898*4882a593Smuzhiyun 			kfree(fp->xdp_tx);
899*4882a593Smuzhiyun 			kfree(fp->txq);
900*4882a593Smuzhiyun 		}
901*4882a593Smuzhiyun 		kfree(edev->fp_array);
902*4882a593Smuzhiyun 	}
903*4882a593Smuzhiyun 
904*4882a593Smuzhiyun 	edev->num_queues = 0;
905*4882a593Smuzhiyun 	edev->fp_num_tx = 0;
906*4882a593Smuzhiyun 	edev->fp_num_rx = 0;
907*4882a593Smuzhiyun }
908*4882a593Smuzhiyun 
qede_alloc_fp_array(struct qede_dev * edev)909*4882a593Smuzhiyun static int qede_alloc_fp_array(struct qede_dev *edev)
910*4882a593Smuzhiyun {
911*4882a593Smuzhiyun 	u8 fp_combined, fp_rx = edev->fp_num_rx;
912*4882a593Smuzhiyun 	struct qede_fastpath *fp;
913*4882a593Smuzhiyun 	int i;
914*4882a593Smuzhiyun 
915*4882a593Smuzhiyun 	edev->fp_array = kcalloc(QEDE_QUEUE_CNT(edev),
916*4882a593Smuzhiyun 				 sizeof(*edev->fp_array), GFP_KERNEL);
917*4882a593Smuzhiyun 	if (!edev->fp_array) {
918*4882a593Smuzhiyun 		DP_NOTICE(edev, "fp array allocation failed\n");
919*4882a593Smuzhiyun 		goto err;
920*4882a593Smuzhiyun 	}
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 	fp_combined = QEDE_QUEUE_CNT(edev) - fp_rx - edev->fp_num_tx;
923*4882a593Smuzhiyun 
924*4882a593Smuzhiyun 	/* Allocate the FP elements for Rx queues followed by combined and then
925*4882a593Smuzhiyun 	 * the Tx. This ordering should be maintained so that the respective
926*4882a593Smuzhiyun 	 * queues (Rx or Tx) will be together in the fastpath array and the
927*4882a593Smuzhiyun 	 * associated ids will be sequential.
928*4882a593Smuzhiyun 	 */
929*4882a593Smuzhiyun 	for_each_queue(i) {
930*4882a593Smuzhiyun 		fp = &edev->fp_array[i];
931*4882a593Smuzhiyun 
932*4882a593Smuzhiyun 		fp->sb_info = kzalloc(sizeof(*fp->sb_info), GFP_KERNEL);
933*4882a593Smuzhiyun 		if (!fp->sb_info) {
934*4882a593Smuzhiyun 			DP_NOTICE(edev, "sb info struct allocation failed\n");
935*4882a593Smuzhiyun 			goto err;
936*4882a593Smuzhiyun 		}
937*4882a593Smuzhiyun 
938*4882a593Smuzhiyun 		if (fp_rx) {
939*4882a593Smuzhiyun 			fp->type = QEDE_FASTPATH_RX;
940*4882a593Smuzhiyun 			fp_rx--;
941*4882a593Smuzhiyun 		} else if (fp_combined) {
942*4882a593Smuzhiyun 			fp->type = QEDE_FASTPATH_COMBINED;
943*4882a593Smuzhiyun 			fp_combined--;
944*4882a593Smuzhiyun 		} else {
945*4882a593Smuzhiyun 			fp->type = QEDE_FASTPATH_TX;
946*4882a593Smuzhiyun 		}
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_TX) {
949*4882a593Smuzhiyun 			fp->txq = kcalloc(edev->dev_info.num_tc,
950*4882a593Smuzhiyun 					  sizeof(*fp->txq), GFP_KERNEL);
951*4882a593Smuzhiyun 			if (!fp->txq)
952*4882a593Smuzhiyun 				goto err;
953*4882a593Smuzhiyun 		}
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_RX) {
956*4882a593Smuzhiyun 			fp->rxq = kzalloc(sizeof(*fp->rxq), GFP_KERNEL);
957*4882a593Smuzhiyun 			if (!fp->rxq)
958*4882a593Smuzhiyun 				goto err;
959*4882a593Smuzhiyun 
960*4882a593Smuzhiyun 			if (edev->xdp_prog) {
961*4882a593Smuzhiyun 				fp->xdp_tx = kzalloc(sizeof(*fp->xdp_tx),
962*4882a593Smuzhiyun 						     GFP_KERNEL);
963*4882a593Smuzhiyun 				if (!fp->xdp_tx)
964*4882a593Smuzhiyun 					goto err;
965*4882a593Smuzhiyun 				fp->type |= QEDE_FASTPATH_XDP;
966*4882a593Smuzhiyun 			}
967*4882a593Smuzhiyun 		}
968*4882a593Smuzhiyun 	}
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 	return 0;
971*4882a593Smuzhiyun err:
972*4882a593Smuzhiyun 	qede_free_fp_array(edev);
973*4882a593Smuzhiyun 	return -ENOMEM;
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun /* The qede lock is used to protect driver state change and driver flows that
977*4882a593Smuzhiyun  * are not reentrant.
978*4882a593Smuzhiyun  */
__qede_lock(struct qede_dev * edev)979*4882a593Smuzhiyun void __qede_lock(struct qede_dev *edev)
980*4882a593Smuzhiyun {
981*4882a593Smuzhiyun 	mutex_lock(&edev->qede_lock);
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun 
__qede_unlock(struct qede_dev * edev)984*4882a593Smuzhiyun void __qede_unlock(struct qede_dev *edev)
985*4882a593Smuzhiyun {
986*4882a593Smuzhiyun 	mutex_unlock(&edev->qede_lock);
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun /* This version of the lock should be used when acquiring the RTNL lock is also
990*4882a593Smuzhiyun  * needed in addition to the internal qede lock.
991*4882a593Smuzhiyun  */
qede_lock(struct qede_dev * edev)992*4882a593Smuzhiyun static void qede_lock(struct qede_dev *edev)
993*4882a593Smuzhiyun {
994*4882a593Smuzhiyun 	rtnl_lock();
995*4882a593Smuzhiyun 	__qede_lock(edev);
996*4882a593Smuzhiyun }
997*4882a593Smuzhiyun 
qede_unlock(struct qede_dev * edev)998*4882a593Smuzhiyun static void qede_unlock(struct qede_dev *edev)
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun 	__qede_unlock(edev);
1001*4882a593Smuzhiyun 	rtnl_unlock();
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun 
qede_sp_task(struct work_struct * work)1004*4882a593Smuzhiyun static void qede_sp_task(struct work_struct *work)
1005*4882a593Smuzhiyun {
1006*4882a593Smuzhiyun 	struct qede_dev *edev = container_of(work, struct qede_dev,
1007*4882a593Smuzhiyun 					     sp_task.work);
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 	/* Disable execution of this deferred work once
1010*4882a593Smuzhiyun 	 * qede removal is in progress, this stop any future
1011*4882a593Smuzhiyun 	 * scheduling of sp_task.
1012*4882a593Smuzhiyun 	 */
1013*4882a593Smuzhiyun 	if (test_bit(QEDE_SP_DISABLE, &edev->sp_flags))
1014*4882a593Smuzhiyun 		return;
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	/* The locking scheme depends on the specific flag:
1017*4882a593Smuzhiyun 	 * In case of QEDE_SP_RECOVERY, acquiring the RTNL lock is required to
1018*4882a593Smuzhiyun 	 * ensure that ongoing flows are ended and new ones are not started.
1019*4882a593Smuzhiyun 	 * In other cases - only the internal qede lock should be acquired.
1020*4882a593Smuzhiyun 	 */
1021*4882a593Smuzhiyun 
1022*4882a593Smuzhiyun 	if (test_and_clear_bit(QEDE_SP_RECOVERY, &edev->sp_flags)) {
1023*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
1024*4882a593Smuzhiyun 		/* SRIOV must be disabled outside the lock to avoid a deadlock.
1025*4882a593Smuzhiyun 		 * The recovery of the active VFs is currently not supported.
1026*4882a593Smuzhiyun 		 */
1027*4882a593Smuzhiyun 		if (pci_num_vf(edev->pdev))
1028*4882a593Smuzhiyun 			qede_sriov_configure(edev->pdev, 0);
1029*4882a593Smuzhiyun #endif
1030*4882a593Smuzhiyun 		qede_lock(edev);
1031*4882a593Smuzhiyun 		qede_recovery_handler(edev);
1032*4882a593Smuzhiyun 		qede_unlock(edev);
1033*4882a593Smuzhiyun 	}
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	__qede_lock(edev);
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun 	if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
1038*4882a593Smuzhiyun 		if (edev->state == QEDE_STATE_OPEN)
1039*4882a593Smuzhiyun 			qede_config_rx_mode(edev->ndev);
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
1042*4882a593Smuzhiyun 	if (test_and_clear_bit(QEDE_SP_ARFS_CONFIG, &edev->sp_flags)) {
1043*4882a593Smuzhiyun 		if (edev->state == QEDE_STATE_OPEN)
1044*4882a593Smuzhiyun 			qede_process_arfs_filters(edev, false);
1045*4882a593Smuzhiyun 	}
1046*4882a593Smuzhiyun #endif
1047*4882a593Smuzhiyun 	if (test_and_clear_bit(QEDE_SP_HW_ERR, &edev->sp_flags))
1048*4882a593Smuzhiyun 		qede_generic_hw_err_handler(edev);
1049*4882a593Smuzhiyun 	__qede_unlock(edev);
1050*4882a593Smuzhiyun 
1051*4882a593Smuzhiyun 	if (test_and_clear_bit(QEDE_SP_AER, &edev->sp_flags)) {
1052*4882a593Smuzhiyun #ifdef CONFIG_QED_SRIOV
1053*4882a593Smuzhiyun 		/* SRIOV must be disabled outside the lock to avoid a deadlock.
1054*4882a593Smuzhiyun 		 * The recovery of the active VFs is currently not supported.
1055*4882a593Smuzhiyun 		 */
1056*4882a593Smuzhiyun 		if (pci_num_vf(edev->pdev))
1057*4882a593Smuzhiyun 			qede_sriov_configure(edev->pdev, 0);
1058*4882a593Smuzhiyun #endif
1059*4882a593Smuzhiyun 		edev->ops->common->recovery_process(edev->cdev);
1060*4882a593Smuzhiyun 	}
1061*4882a593Smuzhiyun }
1062*4882a593Smuzhiyun 
qede_update_pf_params(struct qed_dev * cdev)1063*4882a593Smuzhiyun static void qede_update_pf_params(struct qed_dev *cdev)
1064*4882a593Smuzhiyun {
1065*4882a593Smuzhiyun 	struct qed_pf_params pf_params;
1066*4882a593Smuzhiyun 	u16 num_cons;
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	/* 64 rx + 64 tx + 64 XDP */
1069*4882a593Smuzhiyun 	memset(&pf_params, 0, sizeof(struct qed_pf_params));
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 	/* 1 rx + 1 xdp + max tx cos */
1072*4882a593Smuzhiyun 	num_cons = QED_MIN_L2_CONS;
1073*4882a593Smuzhiyun 
1074*4882a593Smuzhiyun 	pf_params.eth_pf_params.num_cons = (MAX_SB_PER_PF_MIMD - 1) * num_cons;
1075*4882a593Smuzhiyun 
1076*4882a593Smuzhiyun 	/* Same for VFs - make sure they'll have sufficient connections
1077*4882a593Smuzhiyun 	 * to support XDP Tx queues.
1078*4882a593Smuzhiyun 	 */
1079*4882a593Smuzhiyun 	pf_params.eth_pf_params.num_vf_cons = 48;
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
1082*4882a593Smuzhiyun 	qed_ops->common->update_pf_params(cdev, &pf_params);
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun #define QEDE_FW_VER_STR_SIZE	80
1086*4882a593Smuzhiyun 
qede_log_probe(struct qede_dev * edev)1087*4882a593Smuzhiyun static void qede_log_probe(struct qede_dev *edev)
1088*4882a593Smuzhiyun {
1089*4882a593Smuzhiyun 	struct qed_dev_info *p_dev_info = &edev->dev_info.common;
1090*4882a593Smuzhiyun 	u8 buf[QEDE_FW_VER_STR_SIZE];
1091*4882a593Smuzhiyun 	size_t left_size;
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun 	snprintf(buf, QEDE_FW_VER_STR_SIZE,
1094*4882a593Smuzhiyun 		 "Storm FW %d.%d.%d.%d, Management FW %d.%d.%d.%d",
1095*4882a593Smuzhiyun 		 p_dev_info->fw_major, p_dev_info->fw_minor, p_dev_info->fw_rev,
1096*4882a593Smuzhiyun 		 p_dev_info->fw_eng,
1097*4882a593Smuzhiyun 		 (p_dev_info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
1098*4882a593Smuzhiyun 		 QED_MFW_VERSION_3_OFFSET,
1099*4882a593Smuzhiyun 		 (p_dev_info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
1100*4882a593Smuzhiyun 		 QED_MFW_VERSION_2_OFFSET,
1101*4882a593Smuzhiyun 		 (p_dev_info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
1102*4882a593Smuzhiyun 		 QED_MFW_VERSION_1_OFFSET,
1103*4882a593Smuzhiyun 		 (p_dev_info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
1104*4882a593Smuzhiyun 		 QED_MFW_VERSION_0_OFFSET);
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	left_size = QEDE_FW_VER_STR_SIZE - strlen(buf);
1107*4882a593Smuzhiyun 	if (p_dev_info->mbi_version && left_size)
1108*4882a593Smuzhiyun 		snprintf(buf + strlen(buf), left_size,
1109*4882a593Smuzhiyun 			 " [MBI %d.%d.%d]",
1110*4882a593Smuzhiyun 			 (p_dev_info->mbi_version & QED_MBI_VERSION_2_MASK) >>
1111*4882a593Smuzhiyun 			 QED_MBI_VERSION_2_OFFSET,
1112*4882a593Smuzhiyun 			 (p_dev_info->mbi_version & QED_MBI_VERSION_1_MASK) >>
1113*4882a593Smuzhiyun 			 QED_MBI_VERSION_1_OFFSET,
1114*4882a593Smuzhiyun 			 (p_dev_info->mbi_version & QED_MBI_VERSION_0_MASK) >>
1115*4882a593Smuzhiyun 			 QED_MBI_VERSION_0_OFFSET);
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	pr_info("qede %02x:%02x.%02x: %s [%s]\n", edev->pdev->bus->number,
1118*4882a593Smuzhiyun 		PCI_SLOT(edev->pdev->devfn), PCI_FUNC(edev->pdev->devfn),
1119*4882a593Smuzhiyun 		buf, edev->ndev->name);
1120*4882a593Smuzhiyun }
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun enum qede_probe_mode {
1123*4882a593Smuzhiyun 	QEDE_PROBE_NORMAL,
1124*4882a593Smuzhiyun 	QEDE_PROBE_RECOVERY,
1125*4882a593Smuzhiyun };
1126*4882a593Smuzhiyun 
__qede_probe(struct pci_dev * pdev,u32 dp_module,u8 dp_level,bool is_vf,enum qede_probe_mode mode)1127*4882a593Smuzhiyun static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1128*4882a593Smuzhiyun 			bool is_vf, enum qede_probe_mode mode)
1129*4882a593Smuzhiyun {
1130*4882a593Smuzhiyun 	struct qed_probe_params probe_params;
1131*4882a593Smuzhiyun 	struct qed_slowpath_params sp_params;
1132*4882a593Smuzhiyun 	struct qed_dev_eth_info dev_info;
1133*4882a593Smuzhiyun 	struct qede_dev *edev;
1134*4882a593Smuzhiyun 	struct qed_dev *cdev;
1135*4882a593Smuzhiyun 	int rc;
1136*4882a593Smuzhiyun 
1137*4882a593Smuzhiyun 	if (unlikely(dp_level & QED_LEVEL_INFO))
1138*4882a593Smuzhiyun 		pr_notice("Starting qede probe\n");
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 	memset(&probe_params, 0, sizeof(probe_params));
1141*4882a593Smuzhiyun 	probe_params.protocol = QED_PROTOCOL_ETH;
1142*4882a593Smuzhiyun 	probe_params.dp_module = dp_module;
1143*4882a593Smuzhiyun 	probe_params.dp_level = dp_level;
1144*4882a593Smuzhiyun 	probe_params.is_vf = is_vf;
1145*4882a593Smuzhiyun 	probe_params.recov_in_prog = (mode == QEDE_PROBE_RECOVERY);
1146*4882a593Smuzhiyun 	cdev = qed_ops->common->probe(pdev, &probe_params);
1147*4882a593Smuzhiyun 	if (!cdev) {
1148*4882a593Smuzhiyun 		rc = -ENODEV;
1149*4882a593Smuzhiyun 		goto err0;
1150*4882a593Smuzhiyun 	}
1151*4882a593Smuzhiyun 
1152*4882a593Smuzhiyun 	qede_update_pf_params(cdev);
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun 	/* Start the Slowpath-process */
1155*4882a593Smuzhiyun 	memset(&sp_params, 0, sizeof(sp_params));
1156*4882a593Smuzhiyun 	sp_params.int_mode = QED_INT_MODE_MSIX;
1157*4882a593Smuzhiyun 	sp_params.drv_major = QEDE_MAJOR_VERSION;
1158*4882a593Smuzhiyun 	sp_params.drv_minor = QEDE_MINOR_VERSION;
1159*4882a593Smuzhiyun 	sp_params.drv_rev = QEDE_REVISION_VERSION;
1160*4882a593Smuzhiyun 	sp_params.drv_eng = QEDE_ENGINEERING_VERSION;
1161*4882a593Smuzhiyun 	strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
1162*4882a593Smuzhiyun 	rc = qed_ops->common->slowpath_start(cdev, &sp_params);
1163*4882a593Smuzhiyun 	if (rc) {
1164*4882a593Smuzhiyun 		pr_notice("Cannot start slowpath\n");
1165*4882a593Smuzhiyun 		goto err1;
1166*4882a593Smuzhiyun 	}
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun 	/* Learn information crucial for qede to progress */
1169*4882a593Smuzhiyun 	rc = qed_ops->fill_dev_info(cdev, &dev_info);
1170*4882a593Smuzhiyun 	if (rc)
1171*4882a593Smuzhiyun 		goto err2;
1172*4882a593Smuzhiyun 
1173*4882a593Smuzhiyun 	if (mode != QEDE_PROBE_RECOVERY) {
1174*4882a593Smuzhiyun 		edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
1175*4882a593Smuzhiyun 					   dp_level);
1176*4882a593Smuzhiyun 		if (!edev) {
1177*4882a593Smuzhiyun 			rc = -ENOMEM;
1178*4882a593Smuzhiyun 			goto err2;
1179*4882a593Smuzhiyun 		}
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 		edev->devlink = qed_ops->common->devlink_register(cdev);
1182*4882a593Smuzhiyun 		if (IS_ERR(edev->devlink)) {
1183*4882a593Smuzhiyun 			DP_NOTICE(edev, "Cannot register devlink\n");
1184*4882a593Smuzhiyun 			edev->devlink = NULL;
1185*4882a593Smuzhiyun 			/* Go on, we can live without devlink */
1186*4882a593Smuzhiyun 		}
1187*4882a593Smuzhiyun 	} else {
1188*4882a593Smuzhiyun 		struct net_device *ndev = pci_get_drvdata(pdev);
1189*4882a593Smuzhiyun 
1190*4882a593Smuzhiyun 		edev = netdev_priv(ndev);
1191*4882a593Smuzhiyun 
1192*4882a593Smuzhiyun 		if (edev->devlink) {
1193*4882a593Smuzhiyun 			struct qed_devlink *qdl = devlink_priv(edev->devlink);
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun 			qdl->cdev = cdev;
1196*4882a593Smuzhiyun 		}
1197*4882a593Smuzhiyun 		edev->cdev = cdev;
1198*4882a593Smuzhiyun 		memset(&edev->stats, 0, sizeof(edev->stats));
1199*4882a593Smuzhiyun 		memcpy(&edev->dev_info, &dev_info, sizeof(dev_info));
1200*4882a593Smuzhiyun 	}
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun 	if (is_vf)
1203*4882a593Smuzhiyun 		set_bit(QEDE_FLAGS_IS_VF, &edev->flags);
1204*4882a593Smuzhiyun 
1205*4882a593Smuzhiyun 	qede_init_ndev(edev);
1206*4882a593Smuzhiyun 
1207*4882a593Smuzhiyun 	rc = qede_rdma_dev_add(edev, (mode == QEDE_PROBE_RECOVERY));
1208*4882a593Smuzhiyun 	if (rc)
1209*4882a593Smuzhiyun 		goto err3;
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun 	if (mode != QEDE_PROBE_RECOVERY) {
1212*4882a593Smuzhiyun 		/* Prepare the lock prior to the registration of the netdev,
1213*4882a593Smuzhiyun 		 * as once it's registered we might reach flows requiring it
1214*4882a593Smuzhiyun 		 * [it's even possible to reach a flow needing it directly
1215*4882a593Smuzhiyun 		 * from there, although it's unlikely].
1216*4882a593Smuzhiyun 		 */
1217*4882a593Smuzhiyun 		INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
1218*4882a593Smuzhiyun 		mutex_init(&edev->qede_lock);
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun 		rc = register_netdev(edev->ndev);
1221*4882a593Smuzhiyun 		if (rc) {
1222*4882a593Smuzhiyun 			DP_NOTICE(edev, "Cannot register net-device\n");
1223*4882a593Smuzhiyun 			goto err4;
1224*4882a593Smuzhiyun 		}
1225*4882a593Smuzhiyun 	}
1226*4882a593Smuzhiyun 
1227*4882a593Smuzhiyun 	edev->ops->common->set_name(cdev, edev->ndev->name);
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun 	/* PTP not supported on VFs */
1230*4882a593Smuzhiyun 	if (!is_vf)
1231*4882a593Smuzhiyun 		qede_ptp_enable(edev);
1232*4882a593Smuzhiyun 
1233*4882a593Smuzhiyun 	edev->ops->register_ops(cdev, &qede_ll_ops, edev);
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun #ifdef CONFIG_DCB
1236*4882a593Smuzhiyun 	if (!IS_VF(edev))
1237*4882a593Smuzhiyun 		qede_set_dcbnl_ops(edev->ndev);
1238*4882a593Smuzhiyun #endif
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 	edev->rx_copybreak = QEDE_RX_HDR_SIZE;
1241*4882a593Smuzhiyun 
1242*4882a593Smuzhiyun 	qede_log_probe(edev);
1243*4882a593Smuzhiyun 	return 0;
1244*4882a593Smuzhiyun 
1245*4882a593Smuzhiyun err4:
1246*4882a593Smuzhiyun 	qede_rdma_dev_remove(edev, (mode == QEDE_PROBE_RECOVERY));
1247*4882a593Smuzhiyun err3:
1248*4882a593Smuzhiyun 	if (mode != QEDE_PROBE_RECOVERY)
1249*4882a593Smuzhiyun 		free_netdev(edev->ndev);
1250*4882a593Smuzhiyun 	else
1251*4882a593Smuzhiyun 		edev->cdev = NULL;
1252*4882a593Smuzhiyun err2:
1253*4882a593Smuzhiyun 	qed_ops->common->slowpath_stop(cdev);
1254*4882a593Smuzhiyun err1:
1255*4882a593Smuzhiyun 	qed_ops->common->remove(cdev);
1256*4882a593Smuzhiyun err0:
1257*4882a593Smuzhiyun 	return rc;
1258*4882a593Smuzhiyun }
1259*4882a593Smuzhiyun 
qede_probe(struct pci_dev * pdev,const struct pci_device_id * id)1260*4882a593Smuzhiyun static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1261*4882a593Smuzhiyun {
1262*4882a593Smuzhiyun 	bool is_vf = false;
1263*4882a593Smuzhiyun 	u32 dp_module = 0;
1264*4882a593Smuzhiyun 	u8 dp_level = 0;
1265*4882a593Smuzhiyun 
1266*4882a593Smuzhiyun 	switch ((enum qede_pci_private)id->driver_data) {
1267*4882a593Smuzhiyun 	case QEDE_PRIVATE_VF:
1268*4882a593Smuzhiyun 		if (debug & QED_LOG_VERBOSE_MASK)
1269*4882a593Smuzhiyun 			dev_err(&pdev->dev, "Probing a VF\n");
1270*4882a593Smuzhiyun 		is_vf = true;
1271*4882a593Smuzhiyun 		break;
1272*4882a593Smuzhiyun 	default:
1273*4882a593Smuzhiyun 		if (debug & QED_LOG_VERBOSE_MASK)
1274*4882a593Smuzhiyun 			dev_err(&pdev->dev, "Probing a PF\n");
1275*4882a593Smuzhiyun 	}
1276*4882a593Smuzhiyun 
1277*4882a593Smuzhiyun 	qede_config_debug(debug, &dp_module, &dp_level);
1278*4882a593Smuzhiyun 
1279*4882a593Smuzhiyun 	return __qede_probe(pdev, dp_module, dp_level, is_vf,
1280*4882a593Smuzhiyun 			    QEDE_PROBE_NORMAL);
1281*4882a593Smuzhiyun }
1282*4882a593Smuzhiyun 
1283*4882a593Smuzhiyun enum qede_remove_mode {
1284*4882a593Smuzhiyun 	QEDE_REMOVE_NORMAL,
1285*4882a593Smuzhiyun 	QEDE_REMOVE_RECOVERY,
1286*4882a593Smuzhiyun };
1287*4882a593Smuzhiyun 
__qede_remove(struct pci_dev * pdev,enum qede_remove_mode mode)1288*4882a593Smuzhiyun static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
1289*4882a593Smuzhiyun {
1290*4882a593Smuzhiyun 	struct net_device *ndev = pci_get_drvdata(pdev);
1291*4882a593Smuzhiyun 	struct qede_dev *edev;
1292*4882a593Smuzhiyun 	struct qed_dev *cdev;
1293*4882a593Smuzhiyun 
1294*4882a593Smuzhiyun 	if (!ndev) {
1295*4882a593Smuzhiyun 		dev_info(&pdev->dev, "Device has already been removed\n");
1296*4882a593Smuzhiyun 		return;
1297*4882a593Smuzhiyun 	}
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 	edev = netdev_priv(ndev);
1300*4882a593Smuzhiyun 	cdev = edev->cdev;
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	DP_INFO(edev, "Starting qede_remove\n");
1303*4882a593Smuzhiyun 
1304*4882a593Smuzhiyun 	qede_rdma_dev_remove(edev, (mode == QEDE_REMOVE_RECOVERY));
1305*4882a593Smuzhiyun 
1306*4882a593Smuzhiyun 	if (mode != QEDE_REMOVE_RECOVERY) {
1307*4882a593Smuzhiyun 		set_bit(QEDE_SP_DISABLE, &edev->sp_flags);
1308*4882a593Smuzhiyun 		unregister_netdev(ndev);
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun 		cancel_delayed_work_sync(&edev->sp_task);
1311*4882a593Smuzhiyun 
1312*4882a593Smuzhiyun 		edev->ops->common->set_power_state(cdev, PCI_D0);
1313*4882a593Smuzhiyun 
1314*4882a593Smuzhiyun 		pci_set_drvdata(pdev, NULL);
1315*4882a593Smuzhiyun 	}
1316*4882a593Smuzhiyun 
1317*4882a593Smuzhiyun 	qede_ptp_disable(edev);
1318*4882a593Smuzhiyun 
1319*4882a593Smuzhiyun 	/* Use global ops since we've freed edev */
1320*4882a593Smuzhiyun 	qed_ops->common->slowpath_stop(cdev);
1321*4882a593Smuzhiyun 	if (system_state == SYSTEM_POWER_OFF)
1322*4882a593Smuzhiyun 		return;
1323*4882a593Smuzhiyun 
1324*4882a593Smuzhiyun 	if (mode != QEDE_REMOVE_RECOVERY && edev->devlink) {
1325*4882a593Smuzhiyun 		qed_ops->common->devlink_unregister(edev->devlink);
1326*4882a593Smuzhiyun 		edev->devlink = NULL;
1327*4882a593Smuzhiyun 	}
1328*4882a593Smuzhiyun 	qed_ops->common->remove(cdev);
1329*4882a593Smuzhiyun 	edev->cdev = NULL;
1330*4882a593Smuzhiyun 
1331*4882a593Smuzhiyun 	/* Since this can happen out-of-sync with other flows,
1332*4882a593Smuzhiyun 	 * don't release the netdevice until after slowpath stop
1333*4882a593Smuzhiyun 	 * has been called to guarantee various other contexts
1334*4882a593Smuzhiyun 	 * [e.g., QED register callbacks] won't break anything when
1335*4882a593Smuzhiyun 	 * accessing the netdevice.
1336*4882a593Smuzhiyun 	 */
1337*4882a593Smuzhiyun 	if (mode != QEDE_REMOVE_RECOVERY)
1338*4882a593Smuzhiyun 		free_netdev(ndev);
1339*4882a593Smuzhiyun 
1340*4882a593Smuzhiyun 	dev_info(&pdev->dev, "Ending qede_remove successfully\n");
1341*4882a593Smuzhiyun }
1342*4882a593Smuzhiyun 
qede_remove(struct pci_dev * pdev)1343*4882a593Smuzhiyun static void qede_remove(struct pci_dev *pdev)
1344*4882a593Smuzhiyun {
1345*4882a593Smuzhiyun 	__qede_remove(pdev, QEDE_REMOVE_NORMAL);
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun 
qede_shutdown(struct pci_dev * pdev)1348*4882a593Smuzhiyun static void qede_shutdown(struct pci_dev *pdev)
1349*4882a593Smuzhiyun {
1350*4882a593Smuzhiyun 	__qede_remove(pdev, QEDE_REMOVE_NORMAL);
1351*4882a593Smuzhiyun }
1352*4882a593Smuzhiyun 
1353*4882a593Smuzhiyun /* -------------------------------------------------------------------------
1354*4882a593Smuzhiyun  * START OF LOAD / UNLOAD
1355*4882a593Smuzhiyun  * -------------------------------------------------------------------------
1356*4882a593Smuzhiyun  */
1357*4882a593Smuzhiyun 
qede_set_num_queues(struct qede_dev * edev)1358*4882a593Smuzhiyun static int qede_set_num_queues(struct qede_dev *edev)
1359*4882a593Smuzhiyun {
1360*4882a593Smuzhiyun 	int rc;
1361*4882a593Smuzhiyun 	u16 rss_num;
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun 	/* Setup queues according to possible resources*/
1364*4882a593Smuzhiyun 	if (edev->req_queues)
1365*4882a593Smuzhiyun 		rss_num = edev->req_queues;
1366*4882a593Smuzhiyun 	else
1367*4882a593Smuzhiyun 		rss_num = netif_get_num_default_rss_queues() *
1368*4882a593Smuzhiyun 			  edev->dev_info.common.num_hwfns;
1369*4882a593Smuzhiyun 
1370*4882a593Smuzhiyun 	rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
1371*4882a593Smuzhiyun 
1372*4882a593Smuzhiyun 	rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
1373*4882a593Smuzhiyun 	if (rc > 0) {
1374*4882a593Smuzhiyun 		/* Managed to request interrupts for our queues */
1375*4882a593Smuzhiyun 		edev->num_queues = rc;
1376*4882a593Smuzhiyun 		DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
1377*4882a593Smuzhiyun 			QEDE_QUEUE_CNT(edev), rss_num);
1378*4882a593Smuzhiyun 		rc = 0;
1379*4882a593Smuzhiyun 	}
1380*4882a593Smuzhiyun 
1381*4882a593Smuzhiyun 	edev->fp_num_tx = edev->req_num_tx;
1382*4882a593Smuzhiyun 	edev->fp_num_rx = edev->req_num_rx;
1383*4882a593Smuzhiyun 
1384*4882a593Smuzhiyun 	return rc;
1385*4882a593Smuzhiyun }
1386*4882a593Smuzhiyun 
qede_free_mem_sb(struct qede_dev * edev,struct qed_sb_info * sb_info,u16 sb_id)1387*4882a593Smuzhiyun static void qede_free_mem_sb(struct qede_dev *edev, struct qed_sb_info *sb_info,
1388*4882a593Smuzhiyun 			     u16 sb_id)
1389*4882a593Smuzhiyun {
1390*4882a593Smuzhiyun 	if (sb_info->sb_virt) {
1391*4882a593Smuzhiyun 		edev->ops->common->sb_release(edev->cdev, sb_info, sb_id,
1392*4882a593Smuzhiyun 					      QED_SB_TYPE_L2_QUEUE);
1393*4882a593Smuzhiyun 		dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
1394*4882a593Smuzhiyun 				  (void *)sb_info->sb_virt, sb_info->sb_phys);
1395*4882a593Smuzhiyun 		memset(sb_info, 0, sizeof(*sb_info));
1396*4882a593Smuzhiyun 	}
1397*4882a593Smuzhiyun }
1398*4882a593Smuzhiyun 
1399*4882a593Smuzhiyun /* This function allocates fast-path status block memory */
qede_alloc_mem_sb(struct qede_dev * edev,struct qed_sb_info * sb_info,u16 sb_id)1400*4882a593Smuzhiyun static int qede_alloc_mem_sb(struct qede_dev *edev,
1401*4882a593Smuzhiyun 			     struct qed_sb_info *sb_info, u16 sb_id)
1402*4882a593Smuzhiyun {
1403*4882a593Smuzhiyun 	struct status_block_e4 *sb_virt;
1404*4882a593Smuzhiyun 	dma_addr_t sb_phys;
1405*4882a593Smuzhiyun 	int rc;
1406*4882a593Smuzhiyun 
1407*4882a593Smuzhiyun 	sb_virt = dma_alloc_coherent(&edev->pdev->dev,
1408*4882a593Smuzhiyun 				     sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
1409*4882a593Smuzhiyun 	if (!sb_virt) {
1410*4882a593Smuzhiyun 		DP_ERR(edev, "Status block allocation failed\n");
1411*4882a593Smuzhiyun 		return -ENOMEM;
1412*4882a593Smuzhiyun 	}
1413*4882a593Smuzhiyun 
1414*4882a593Smuzhiyun 	rc = edev->ops->common->sb_init(edev->cdev, sb_info,
1415*4882a593Smuzhiyun 					sb_virt, sb_phys, sb_id,
1416*4882a593Smuzhiyun 					QED_SB_TYPE_L2_QUEUE);
1417*4882a593Smuzhiyun 	if (rc) {
1418*4882a593Smuzhiyun 		DP_ERR(edev, "Status block initialization failed\n");
1419*4882a593Smuzhiyun 		dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
1420*4882a593Smuzhiyun 				  sb_virt, sb_phys);
1421*4882a593Smuzhiyun 		return rc;
1422*4882a593Smuzhiyun 	}
1423*4882a593Smuzhiyun 
1424*4882a593Smuzhiyun 	return 0;
1425*4882a593Smuzhiyun }
1426*4882a593Smuzhiyun 
qede_free_rx_buffers(struct qede_dev * edev,struct qede_rx_queue * rxq)1427*4882a593Smuzhiyun static void qede_free_rx_buffers(struct qede_dev *edev,
1428*4882a593Smuzhiyun 				 struct qede_rx_queue *rxq)
1429*4882a593Smuzhiyun {
1430*4882a593Smuzhiyun 	u16 i;
1431*4882a593Smuzhiyun 
1432*4882a593Smuzhiyun 	for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
1433*4882a593Smuzhiyun 		struct sw_rx_data *rx_buf;
1434*4882a593Smuzhiyun 		struct page *data;
1435*4882a593Smuzhiyun 
1436*4882a593Smuzhiyun 		rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
1437*4882a593Smuzhiyun 		data = rx_buf->data;
1438*4882a593Smuzhiyun 
1439*4882a593Smuzhiyun 		dma_unmap_page(&edev->pdev->dev,
1440*4882a593Smuzhiyun 			       rx_buf->mapping, PAGE_SIZE, rxq->data_direction);
1441*4882a593Smuzhiyun 
1442*4882a593Smuzhiyun 		rx_buf->data = NULL;
1443*4882a593Smuzhiyun 		__free_page(data);
1444*4882a593Smuzhiyun 	}
1445*4882a593Smuzhiyun }
1446*4882a593Smuzhiyun 
qede_free_mem_rxq(struct qede_dev * edev,struct qede_rx_queue * rxq)1447*4882a593Smuzhiyun static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
1448*4882a593Smuzhiyun {
1449*4882a593Smuzhiyun 	/* Free rx buffers */
1450*4882a593Smuzhiyun 	qede_free_rx_buffers(edev, rxq);
1451*4882a593Smuzhiyun 
1452*4882a593Smuzhiyun 	/* Free the parallel SW ring */
1453*4882a593Smuzhiyun 	kfree(rxq->sw_rx_ring);
1454*4882a593Smuzhiyun 
1455*4882a593Smuzhiyun 	/* Free the real RQ ring used by FW */
1456*4882a593Smuzhiyun 	edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
1457*4882a593Smuzhiyun 	edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
1458*4882a593Smuzhiyun }
1459*4882a593Smuzhiyun 
qede_set_tpa_param(struct qede_rx_queue * rxq)1460*4882a593Smuzhiyun static void qede_set_tpa_param(struct qede_rx_queue *rxq)
1461*4882a593Smuzhiyun {
1462*4882a593Smuzhiyun 	int i;
1463*4882a593Smuzhiyun 
1464*4882a593Smuzhiyun 	for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
1465*4882a593Smuzhiyun 		struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
1466*4882a593Smuzhiyun 
1467*4882a593Smuzhiyun 		tpa_info->state = QEDE_AGG_STATE_NONE;
1468*4882a593Smuzhiyun 	}
1469*4882a593Smuzhiyun }
1470*4882a593Smuzhiyun 
1471*4882a593Smuzhiyun /* This function allocates all memory needed per Rx queue */
qede_alloc_mem_rxq(struct qede_dev * edev,struct qede_rx_queue * rxq)1472*4882a593Smuzhiyun static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
1473*4882a593Smuzhiyun {
1474*4882a593Smuzhiyun 	struct qed_chain_init_params params = {
1475*4882a593Smuzhiyun 		.cnt_type	= QED_CHAIN_CNT_TYPE_U16,
1476*4882a593Smuzhiyun 		.num_elems	= RX_RING_SIZE,
1477*4882a593Smuzhiyun 	};
1478*4882a593Smuzhiyun 	struct qed_dev *cdev = edev->cdev;
1479*4882a593Smuzhiyun 	int i, rc, size;
1480*4882a593Smuzhiyun 
1481*4882a593Smuzhiyun 	rxq->num_rx_buffers = edev->q_num_rx_buffers;
1482*4882a593Smuzhiyun 
1483*4882a593Smuzhiyun 	rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	rxq->rx_headroom = edev->xdp_prog ? XDP_PACKET_HEADROOM : NET_SKB_PAD;
1486*4882a593Smuzhiyun 	size = rxq->rx_headroom +
1487*4882a593Smuzhiyun 	       SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1488*4882a593Smuzhiyun 
1489*4882a593Smuzhiyun 	/* Make sure that the headroom and  payload fit in a single page */
1490*4882a593Smuzhiyun 	if (rxq->rx_buf_size + size > PAGE_SIZE)
1491*4882a593Smuzhiyun 		rxq->rx_buf_size = PAGE_SIZE - size;
1492*4882a593Smuzhiyun 
1493*4882a593Smuzhiyun 	/* Segment size to split a page in multiple equal parts,
1494*4882a593Smuzhiyun 	 * unless XDP is used in which case we'd use the entire page.
1495*4882a593Smuzhiyun 	 */
1496*4882a593Smuzhiyun 	if (!edev->xdp_prog) {
1497*4882a593Smuzhiyun 		size = size + rxq->rx_buf_size;
1498*4882a593Smuzhiyun 		rxq->rx_buf_seg_size = roundup_pow_of_two(size);
1499*4882a593Smuzhiyun 	} else {
1500*4882a593Smuzhiyun 		rxq->rx_buf_seg_size = PAGE_SIZE;
1501*4882a593Smuzhiyun 		edev->ndev->features &= ~NETIF_F_GRO_HW;
1502*4882a593Smuzhiyun 	}
1503*4882a593Smuzhiyun 
1504*4882a593Smuzhiyun 	/* Allocate the parallel driver ring for Rx buffers */
1505*4882a593Smuzhiyun 	size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
1506*4882a593Smuzhiyun 	rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
1507*4882a593Smuzhiyun 	if (!rxq->sw_rx_ring) {
1508*4882a593Smuzhiyun 		DP_ERR(edev, "Rx buffers ring allocation failed\n");
1509*4882a593Smuzhiyun 		rc = -ENOMEM;
1510*4882a593Smuzhiyun 		goto err;
1511*4882a593Smuzhiyun 	}
1512*4882a593Smuzhiyun 
1513*4882a593Smuzhiyun 	/* Allocate FW Rx ring  */
1514*4882a593Smuzhiyun 	params.mode = QED_CHAIN_MODE_NEXT_PTR;
1515*4882a593Smuzhiyun 	params.intended_use = QED_CHAIN_USE_TO_CONSUME_PRODUCE;
1516*4882a593Smuzhiyun 	params.elem_size = sizeof(struct eth_rx_bd);
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun 	rc = edev->ops->common->chain_alloc(cdev, &rxq->rx_bd_ring, &params);
1519*4882a593Smuzhiyun 	if (rc)
1520*4882a593Smuzhiyun 		goto err;
1521*4882a593Smuzhiyun 
1522*4882a593Smuzhiyun 	/* Allocate FW completion ring */
1523*4882a593Smuzhiyun 	params.mode = QED_CHAIN_MODE_PBL;
1524*4882a593Smuzhiyun 	params.intended_use = QED_CHAIN_USE_TO_CONSUME;
1525*4882a593Smuzhiyun 	params.elem_size = sizeof(union eth_rx_cqe);
1526*4882a593Smuzhiyun 
1527*4882a593Smuzhiyun 	rc = edev->ops->common->chain_alloc(cdev, &rxq->rx_comp_ring, &params);
1528*4882a593Smuzhiyun 	if (rc)
1529*4882a593Smuzhiyun 		goto err;
1530*4882a593Smuzhiyun 
1531*4882a593Smuzhiyun 	/* Allocate buffers for the Rx ring */
1532*4882a593Smuzhiyun 	rxq->filled_buffers = 0;
1533*4882a593Smuzhiyun 	for (i = 0; i < rxq->num_rx_buffers; i++) {
1534*4882a593Smuzhiyun 		rc = qede_alloc_rx_buffer(rxq, false);
1535*4882a593Smuzhiyun 		if (rc) {
1536*4882a593Smuzhiyun 			DP_ERR(edev,
1537*4882a593Smuzhiyun 			       "Rx buffers allocation failed at index %d\n", i);
1538*4882a593Smuzhiyun 			goto err;
1539*4882a593Smuzhiyun 		}
1540*4882a593Smuzhiyun 	}
1541*4882a593Smuzhiyun 
1542*4882a593Smuzhiyun 	edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO_HW);
1543*4882a593Smuzhiyun 	if (!edev->gro_disable)
1544*4882a593Smuzhiyun 		qede_set_tpa_param(rxq);
1545*4882a593Smuzhiyun err:
1546*4882a593Smuzhiyun 	return rc;
1547*4882a593Smuzhiyun }
1548*4882a593Smuzhiyun 
qede_free_mem_txq(struct qede_dev * edev,struct qede_tx_queue * txq)1549*4882a593Smuzhiyun static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
1550*4882a593Smuzhiyun {
1551*4882a593Smuzhiyun 	/* Free the parallel SW ring */
1552*4882a593Smuzhiyun 	if (txq->is_xdp)
1553*4882a593Smuzhiyun 		kfree(txq->sw_tx_ring.xdp);
1554*4882a593Smuzhiyun 	else
1555*4882a593Smuzhiyun 		kfree(txq->sw_tx_ring.skbs);
1556*4882a593Smuzhiyun 
1557*4882a593Smuzhiyun 	/* Free the real RQ ring used by FW */
1558*4882a593Smuzhiyun 	edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
1559*4882a593Smuzhiyun }
1560*4882a593Smuzhiyun 
1561*4882a593Smuzhiyun /* This function allocates all memory needed per Tx queue */
qede_alloc_mem_txq(struct qede_dev * edev,struct qede_tx_queue * txq)1562*4882a593Smuzhiyun static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
1563*4882a593Smuzhiyun {
1564*4882a593Smuzhiyun 	struct qed_chain_init_params params = {
1565*4882a593Smuzhiyun 		.mode		= QED_CHAIN_MODE_PBL,
1566*4882a593Smuzhiyun 		.intended_use	= QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1567*4882a593Smuzhiyun 		.cnt_type	= QED_CHAIN_CNT_TYPE_U16,
1568*4882a593Smuzhiyun 		.num_elems	= edev->q_num_tx_buffers,
1569*4882a593Smuzhiyun 		.elem_size	= sizeof(union eth_tx_bd_types),
1570*4882a593Smuzhiyun 	};
1571*4882a593Smuzhiyun 	int size, rc;
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun 	txq->num_tx_buffers = edev->q_num_tx_buffers;
1574*4882a593Smuzhiyun 
1575*4882a593Smuzhiyun 	/* Allocate the parallel driver ring for Tx buffers */
1576*4882a593Smuzhiyun 	if (txq->is_xdp) {
1577*4882a593Smuzhiyun 		size = sizeof(*txq->sw_tx_ring.xdp) * txq->num_tx_buffers;
1578*4882a593Smuzhiyun 		txq->sw_tx_ring.xdp = kzalloc(size, GFP_KERNEL);
1579*4882a593Smuzhiyun 		if (!txq->sw_tx_ring.xdp)
1580*4882a593Smuzhiyun 			goto err;
1581*4882a593Smuzhiyun 	} else {
1582*4882a593Smuzhiyun 		size = sizeof(*txq->sw_tx_ring.skbs) * txq->num_tx_buffers;
1583*4882a593Smuzhiyun 		txq->sw_tx_ring.skbs = kzalloc(size, GFP_KERNEL);
1584*4882a593Smuzhiyun 		if (!txq->sw_tx_ring.skbs)
1585*4882a593Smuzhiyun 			goto err;
1586*4882a593Smuzhiyun 	}
1587*4882a593Smuzhiyun 
1588*4882a593Smuzhiyun 	rc = edev->ops->common->chain_alloc(edev->cdev, &txq->tx_pbl, &params);
1589*4882a593Smuzhiyun 	if (rc)
1590*4882a593Smuzhiyun 		goto err;
1591*4882a593Smuzhiyun 
1592*4882a593Smuzhiyun 	return 0;
1593*4882a593Smuzhiyun 
1594*4882a593Smuzhiyun err:
1595*4882a593Smuzhiyun 	qede_free_mem_txq(edev, txq);
1596*4882a593Smuzhiyun 	return -ENOMEM;
1597*4882a593Smuzhiyun }
1598*4882a593Smuzhiyun 
1599*4882a593Smuzhiyun /* This function frees all memory of a single fp */
qede_free_mem_fp(struct qede_dev * edev,struct qede_fastpath * fp)1600*4882a593Smuzhiyun static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
1601*4882a593Smuzhiyun {
1602*4882a593Smuzhiyun 	qede_free_mem_sb(edev, fp->sb_info, fp->id);
1603*4882a593Smuzhiyun 
1604*4882a593Smuzhiyun 	if (fp->type & QEDE_FASTPATH_RX)
1605*4882a593Smuzhiyun 		qede_free_mem_rxq(edev, fp->rxq);
1606*4882a593Smuzhiyun 
1607*4882a593Smuzhiyun 	if (fp->type & QEDE_FASTPATH_XDP)
1608*4882a593Smuzhiyun 		qede_free_mem_txq(edev, fp->xdp_tx);
1609*4882a593Smuzhiyun 
1610*4882a593Smuzhiyun 	if (fp->type & QEDE_FASTPATH_TX) {
1611*4882a593Smuzhiyun 		int cos;
1612*4882a593Smuzhiyun 
1613*4882a593Smuzhiyun 		for_each_cos_in_txq(edev, cos)
1614*4882a593Smuzhiyun 			qede_free_mem_txq(edev, &fp->txq[cos]);
1615*4882a593Smuzhiyun 	}
1616*4882a593Smuzhiyun }
1617*4882a593Smuzhiyun 
1618*4882a593Smuzhiyun /* This function allocates all memory needed for a single fp (i.e. an entity
1619*4882a593Smuzhiyun  * which contains status block, one rx queue and/or multiple per-TC tx queues.
1620*4882a593Smuzhiyun  */
qede_alloc_mem_fp(struct qede_dev * edev,struct qede_fastpath * fp)1621*4882a593Smuzhiyun static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
1622*4882a593Smuzhiyun {
1623*4882a593Smuzhiyun 	int rc = 0;
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun 	rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->id);
1626*4882a593Smuzhiyun 	if (rc)
1627*4882a593Smuzhiyun 		goto out;
1628*4882a593Smuzhiyun 
1629*4882a593Smuzhiyun 	if (fp->type & QEDE_FASTPATH_RX) {
1630*4882a593Smuzhiyun 		rc = qede_alloc_mem_rxq(edev, fp->rxq);
1631*4882a593Smuzhiyun 		if (rc)
1632*4882a593Smuzhiyun 			goto out;
1633*4882a593Smuzhiyun 	}
1634*4882a593Smuzhiyun 
1635*4882a593Smuzhiyun 	if (fp->type & QEDE_FASTPATH_XDP) {
1636*4882a593Smuzhiyun 		rc = qede_alloc_mem_txq(edev, fp->xdp_tx);
1637*4882a593Smuzhiyun 		if (rc)
1638*4882a593Smuzhiyun 			goto out;
1639*4882a593Smuzhiyun 	}
1640*4882a593Smuzhiyun 
1641*4882a593Smuzhiyun 	if (fp->type & QEDE_FASTPATH_TX) {
1642*4882a593Smuzhiyun 		int cos;
1643*4882a593Smuzhiyun 
1644*4882a593Smuzhiyun 		for_each_cos_in_txq(edev, cos) {
1645*4882a593Smuzhiyun 			rc = qede_alloc_mem_txq(edev, &fp->txq[cos]);
1646*4882a593Smuzhiyun 			if (rc)
1647*4882a593Smuzhiyun 				goto out;
1648*4882a593Smuzhiyun 		}
1649*4882a593Smuzhiyun 	}
1650*4882a593Smuzhiyun 
1651*4882a593Smuzhiyun out:
1652*4882a593Smuzhiyun 	return rc;
1653*4882a593Smuzhiyun }
1654*4882a593Smuzhiyun 
qede_free_mem_load(struct qede_dev * edev)1655*4882a593Smuzhiyun static void qede_free_mem_load(struct qede_dev *edev)
1656*4882a593Smuzhiyun {
1657*4882a593Smuzhiyun 	int i;
1658*4882a593Smuzhiyun 
1659*4882a593Smuzhiyun 	for_each_queue(i) {
1660*4882a593Smuzhiyun 		struct qede_fastpath *fp = &edev->fp_array[i];
1661*4882a593Smuzhiyun 
1662*4882a593Smuzhiyun 		qede_free_mem_fp(edev, fp);
1663*4882a593Smuzhiyun 	}
1664*4882a593Smuzhiyun }
1665*4882a593Smuzhiyun 
1666*4882a593Smuzhiyun /* This function allocates all qede memory at NIC load. */
qede_alloc_mem_load(struct qede_dev * edev)1667*4882a593Smuzhiyun static int qede_alloc_mem_load(struct qede_dev *edev)
1668*4882a593Smuzhiyun {
1669*4882a593Smuzhiyun 	int rc = 0, queue_id;
1670*4882a593Smuzhiyun 
1671*4882a593Smuzhiyun 	for (queue_id = 0; queue_id < QEDE_QUEUE_CNT(edev); queue_id++) {
1672*4882a593Smuzhiyun 		struct qede_fastpath *fp = &edev->fp_array[queue_id];
1673*4882a593Smuzhiyun 
1674*4882a593Smuzhiyun 		rc = qede_alloc_mem_fp(edev, fp);
1675*4882a593Smuzhiyun 		if (rc) {
1676*4882a593Smuzhiyun 			DP_ERR(edev,
1677*4882a593Smuzhiyun 			       "Failed to allocate memory for fastpath - rss id = %d\n",
1678*4882a593Smuzhiyun 			       queue_id);
1679*4882a593Smuzhiyun 			qede_free_mem_load(edev);
1680*4882a593Smuzhiyun 			return rc;
1681*4882a593Smuzhiyun 		}
1682*4882a593Smuzhiyun 	}
1683*4882a593Smuzhiyun 
1684*4882a593Smuzhiyun 	return 0;
1685*4882a593Smuzhiyun }
1686*4882a593Smuzhiyun 
qede_empty_tx_queue(struct qede_dev * edev,struct qede_tx_queue * txq)1687*4882a593Smuzhiyun static void qede_empty_tx_queue(struct qede_dev *edev,
1688*4882a593Smuzhiyun 				struct qede_tx_queue *txq)
1689*4882a593Smuzhiyun {
1690*4882a593Smuzhiyun 	unsigned int pkts_compl = 0, bytes_compl = 0;
1691*4882a593Smuzhiyun 	struct netdev_queue *netdev_txq;
1692*4882a593Smuzhiyun 	int rc, len = 0;
1693*4882a593Smuzhiyun 
1694*4882a593Smuzhiyun 	netdev_txq = netdev_get_tx_queue(edev->ndev, txq->ndev_txq_id);
1695*4882a593Smuzhiyun 
1696*4882a593Smuzhiyun 	while (qed_chain_get_cons_idx(&txq->tx_pbl) !=
1697*4882a593Smuzhiyun 	       qed_chain_get_prod_idx(&txq->tx_pbl)) {
1698*4882a593Smuzhiyun 		DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1699*4882a593Smuzhiyun 			   "Freeing a packet on tx queue[%d]: chain_cons 0x%x, chain_prod 0x%x\n",
1700*4882a593Smuzhiyun 			   txq->index, qed_chain_get_cons_idx(&txq->tx_pbl),
1701*4882a593Smuzhiyun 			   qed_chain_get_prod_idx(&txq->tx_pbl));
1702*4882a593Smuzhiyun 
1703*4882a593Smuzhiyun 		rc = qede_free_tx_pkt(edev, txq, &len);
1704*4882a593Smuzhiyun 		if (rc) {
1705*4882a593Smuzhiyun 			DP_NOTICE(edev,
1706*4882a593Smuzhiyun 				  "Failed to free a packet on tx queue[%d]: chain_cons 0x%x, chain_prod 0x%x\n",
1707*4882a593Smuzhiyun 				  txq->index,
1708*4882a593Smuzhiyun 				  qed_chain_get_cons_idx(&txq->tx_pbl),
1709*4882a593Smuzhiyun 				  qed_chain_get_prod_idx(&txq->tx_pbl));
1710*4882a593Smuzhiyun 			break;
1711*4882a593Smuzhiyun 		}
1712*4882a593Smuzhiyun 
1713*4882a593Smuzhiyun 		bytes_compl += len;
1714*4882a593Smuzhiyun 		pkts_compl++;
1715*4882a593Smuzhiyun 		txq->sw_tx_cons++;
1716*4882a593Smuzhiyun 	}
1717*4882a593Smuzhiyun 
1718*4882a593Smuzhiyun 	netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
1719*4882a593Smuzhiyun }
1720*4882a593Smuzhiyun 
qede_empty_tx_queues(struct qede_dev * edev)1721*4882a593Smuzhiyun static void qede_empty_tx_queues(struct qede_dev *edev)
1722*4882a593Smuzhiyun {
1723*4882a593Smuzhiyun 	int i;
1724*4882a593Smuzhiyun 
1725*4882a593Smuzhiyun 	for_each_queue(i)
1726*4882a593Smuzhiyun 		if (edev->fp_array[i].type & QEDE_FASTPATH_TX) {
1727*4882a593Smuzhiyun 			int cos;
1728*4882a593Smuzhiyun 
1729*4882a593Smuzhiyun 			for_each_cos_in_txq(edev, cos) {
1730*4882a593Smuzhiyun 				struct qede_fastpath *fp;
1731*4882a593Smuzhiyun 
1732*4882a593Smuzhiyun 				fp = &edev->fp_array[i];
1733*4882a593Smuzhiyun 				qede_empty_tx_queue(edev,
1734*4882a593Smuzhiyun 						    &fp->txq[cos]);
1735*4882a593Smuzhiyun 			}
1736*4882a593Smuzhiyun 		}
1737*4882a593Smuzhiyun }
1738*4882a593Smuzhiyun 
1739*4882a593Smuzhiyun /* This function inits fp content and resets the SB, RXQ and TXQ structures */
qede_init_fp(struct qede_dev * edev)1740*4882a593Smuzhiyun static void qede_init_fp(struct qede_dev *edev)
1741*4882a593Smuzhiyun {
1742*4882a593Smuzhiyun 	int queue_id, rxq_index = 0, txq_index = 0;
1743*4882a593Smuzhiyun 	struct qede_fastpath *fp;
1744*4882a593Smuzhiyun 	bool init_xdp = false;
1745*4882a593Smuzhiyun 
1746*4882a593Smuzhiyun 	for_each_queue(queue_id) {
1747*4882a593Smuzhiyun 		fp = &edev->fp_array[queue_id];
1748*4882a593Smuzhiyun 
1749*4882a593Smuzhiyun 		fp->edev = edev;
1750*4882a593Smuzhiyun 		fp->id = queue_id;
1751*4882a593Smuzhiyun 
1752*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_XDP) {
1753*4882a593Smuzhiyun 			fp->xdp_tx->index = QEDE_TXQ_IDX_TO_XDP(edev,
1754*4882a593Smuzhiyun 								rxq_index);
1755*4882a593Smuzhiyun 			fp->xdp_tx->is_xdp = 1;
1756*4882a593Smuzhiyun 
1757*4882a593Smuzhiyun 			spin_lock_init(&fp->xdp_tx->xdp_tx_lock);
1758*4882a593Smuzhiyun 			init_xdp = true;
1759*4882a593Smuzhiyun 		}
1760*4882a593Smuzhiyun 
1761*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_RX) {
1762*4882a593Smuzhiyun 			fp->rxq->rxq_id = rxq_index++;
1763*4882a593Smuzhiyun 
1764*4882a593Smuzhiyun 			/* Determine how to map buffers for this queue */
1765*4882a593Smuzhiyun 			if (fp->type & QEDE_FASTPATH_XDP)
1766*4882a593Smuzhiyun 				fp->rxq->data_direction = DMA_BIDIRECTIONAL;
1767*4882a593Smuzhiyun 			else
1768*4882a593Smuzhiyun 				fp->rxq->data_direction = DMA_FROM_DEVICE;
1769*4882a593Smuzhiyun 			fp->rxq->dev = &edev->pdev->dev;
1770*4882a593Smuzhiyun 
1771*4882a593Smuzhiyun 			/* Driver have no error path from here */
1772*4882a593Smuzhiyun 			WARN_ON(xdp_rxq_info_reg(&fp->rxq->xdp_rxq, edev->ndev,
1773*4882a593Smuzhiyun 						 fp->rxq->rxq_id) < 0);
1774*4882a593Smuzhiyun 
1775*4882a593Smuzhiyun 			if (xdp_rxq_info_reg_mem_model(&fp->rxq->xdp_rxq,
1776*4882a593Smuzhiyun 						       MEM_TYPE_PAGE_ORDER0,
1777*4882a593Smuzhiyun 						       NULL)) {
1778*4882a593Smuzhiyun 				DP_NOTICE(edev,
1779*4882a593Smuzhiyun 					  "Failed to register XDP memory model\n");
1780*4882a593Smuzhiyun 			}
1781*4882a593Smuzhiyun 		}
1782*4882a593Smuzhiyun 
1783*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_TX) {
1784*4882a593Smuzhiyun 			int cos;
1785*4882a593Smuzhiyun 
1786*4882a593Smuzhiyun 			for_each_cos_in_txq(edev, cos) {
1787*4882a593Smuzhiyun 				struct qede_tx_queue *txq = &fp->txq[cos];
1788*4882a593Smuzhiyun 				u16 ndev_tx_id;
1789*4882a593Smuzhiyun 
1790*4882a593Smuzhiyun 				txq->cos = cos;
1791*4882a593Smuzhiyun 				txq->index = txq_index;
1792*4882a593Smuzhiyun 				ndev_tx_id = QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq);
1793*4882a593Smuzhiyun 				txq->ndev_txq_id = ndev_tx_id;
1794*4882a593Smuzhiyun 
1795*4882a593Smuzhiyun 				if (edev->dev_info.is_legacy)
1796*4882a593Smuzhiyun 					txq->is_legacy = true;
1797*4882a593Smuzhiyun 				txq->dev = &edev->pdev->dev;
1798*4882a593Smuzhiyun 			}
1799*4882a593Smuzhiyun 
1800*4882a593Smuzhiyun 			txq_index++;
1801*4882a593Smuzhiyun 		}
1802*4882a593Smuzhiyun 
1803*4882a593Smuzhiyun 		snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1804*4882a593Smuzhiyun 			 edev->ndev->name, queue_id);
1805*4882a593Smuzhiyun 	}
1806*4882a593Smuzhiyun 
1807*4882a593Smuzhiyun 	if (init_xdp) {
1808*4882a593Smuzhiyun 		edev->total_xdp_queues = QEDE_RSS_COUNT(edev);
1809*4882a593Smuzhiyun 		DP_INFO(edev, "Total XDP queues: %u\n", edev->total_xdp_queues);
1810*4882a593Smuzhiyun 	}
1811*4882a593Smuzhiyun }
1812*4882a593Smuzhiyun 
qede_set_real_num_queues(struct qede_dev * edev)1813*4882a593Smuzhiyun static int qede_set_real_num_queues(struct qede_dev *edev)
1814*4882a593Smuzhiyun {
1815*4882a593Smuzhiyun 	int rc = 0;
1816*4882a593Smuzhiyun 
1817*4882a593Smuzhiyun 	rc = netif_set_real_num_tx_queues(edev->ndev,
1818*4882a593Smuzhiyun 					  QEDE_TSS_COUNT(edev) *
1819*4882a593Smuzhiyun 					  edev->dev_info.num_tc);
1820*4882a593Smuzhiyun 	if (rc) {
1821*4882a593Smuzhiyun 		DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
1822*4882a593Smuzhiyun 		return rc;
1823*4882a593Smuzhiyun 	}
1824*4882a593Smuzhiyun 
1825*4882a593Smuzhiyun 	rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_COUNT(edev));
1826*4882a593Smuzhiyun 	if (rc) {
1827*4882a593Smuzhiyun 		DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
1828*4882a593Smuzhiyun 		return rc;
1829*4882a593Smuzhiyun 	}
1830*4882a593Smuzhiyun 
1831*4882a593Smuzhiyun 	return 0;
1832*4882a593Smuzhiyun }
1833*4882a593Smuzhiyun 
qede_napi_disable_remove(struct qede_dev * edev)1834*4882a593Smuzhiyun static void qede_napi_disable_remove(struct qede_dev *edev)
1835*4882a593Smuzhiyun {
1836*4882a593Smuzhiyun 	int i;
1837*4882a593Smuzhiyun 
1838*4882a593Smuzhiyun 	for_each_queue(i) {
1839*4882a593Smuzhiyun 		napi_disable(&edev->fp_array[i].napi);
1840*4882a593Smuzhiyun 
1841*4882a593Smuzhiyun 		netif_napi_del(&edev->fp_array[i].napi);
1842*4882a593Smuzhiyun 	}
1843*4882a593Smuzhiyun }
1844*4882a593Smuzhiyun 
qede_napi_add_enable(struct qede_dev * edev)1845*4882a593Smuzhiyun static void qede_napi_add_enable(struct qede_dev *edev)
1846*4882a593Smuzhiyun {
1847*4882a593Smuzhiyun 	int i;
1848*4882a593Smuzhiyun 
1849*4882a593Smuzhiyun 	/* Add NAPI objects */
1850*4882a593Smuzhiyun 	for_each_queue(i) {
1851*4882a593Smuzhiyun 		netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
1852*4882a593Smuzhiyun 			       qede_poll, NAPI_POLL_WEIGHT);
1853*4882a593Smuzhiyun 		napi_enable(&edev->fp_array[i].napi);
1854*4882a593Smuzhiyun 	}
1855*4882a593Smuzhiyun }
1856*4882a593Smuzhiyun 
qede_sync_free_irqs(struct qede_dev * edev)1857*4882a593Smuzhiyun static void qede_sync_free_irqs(struct qede_dev *edev)
1858*4882a593Smuzhiyun {
1859*4882a593Smuzhiyun 	int i;
1860*4882a593Smuzhiyun 
1861*4882a593Smuzhiyun 	for (i = 0; i < edev->int_info.used_cnt; i++) {
1862*4882a593Smuzhiyun 		if (edev->int_info.msix_cnt) {
1863*4882a593Smuzhiyun 			synchronize_irq(edev->int_info.msix[i].vector);
1864*4882a593Smuzhiyun 			free_irq(edev->int_info.msix[i].vector,
1865*4882a593Smuzhiyun 				 &edev->fp_array[i]);
1866*4882a593Smuzhiyun 		} else {
1867*4882a593Smuzhiyun 			edev->ops->common->simd_handler_clean(edev->cdev, i);
1868*4882a593Smuzhiyun 		}
1869*4882a593Smuzhiyun 	}
1870*4882a593Smuzhiyun 
1871*4882a593Smuzhiyun 	edev->int_info.used_cnt = 0;
1872*4882a593Smuzhiyun 	edev->int_info.msix_cnt = 0;
1873*4882a593Smuzhiyun }
1874*4882a593Smuzhiyun 
qede_req_msix_irqs(struct qede_dev * edev)1875*4882a593Smuzhiyun static int qede_req_msix_irqs(struct qede_dev *edev)
1876*4882a593Smuzhiyun {
1877*4882a593Smuzhiyun 	int i, rc;
1878*4882a593Smuzhiyun 
1879*4882a593Smuzhiyun 	/* Sanitize number of interrupts == number of prepared RSS queues */
1880*4882a593Smuzhiyun 	if (QEDE_QUEUE_CNT(edev) > edev->int_info.msix_cnt) {
1881*4882a593Smuzhiyun 		DP_ERR(edev,
1882*4882a593Smuzhiyun 		       "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
1883*4882a593Smuzhiyun 		       QEDE_QUEUE_CNT(edev), edev->int_info.msix_cnt);
1884*4882a593Smuzhiyun 		return -EINVAL;
1885*4882a593Smuzhiyun 	}
1886*4882a593Smuzhiyun 
1887*4882a593Smuzhiyun 	for (i = 0; i < QEDE_QUEUE_CNT(edev); i++) {
1888*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
1889*4882a593Smuzhiyun 		struct qede_fastpath *fp = &edev->fp_array[i];
1890*4882a593Smuzhiyun 
1891*4882a593Smuzhiyun 		if (edev->ndev->rx_cpu_rmap && (fp->type & QEDE_FASTPATH_RX)) {
1892*4882a593Smuzhiyun 			rc = irq_cpu_rmap_add(edev->ndev->rx_cpu_rmap,
1893*4882a593Smuzhiyun 					      edev->int_info.msix[i].vector);
1894*4882a593Smuzhiyun 			if (rc) {
1895*4882a593Smuzhiyun 				DP_ERR(edev, "Failed to add CPU rmap\n");
1896*4882a593Smuzhiyun 				qede_free_arfs(edev);
1897*4882a593Smuzhiyun 			}
1898*4882a593Smuzhiyun 		}
1899*4882a593Smuzhiyun #endif
1900*4882a593Smuzhiyun 		rc = request_irq(edev->int_info.msix[i].vector,
1901*4882a593Smuzhiyun 				 qede_msix_fp_int, 0, edev->fp_array[i].name,
1902*4882a593Smuzhiyun 				 &edev->fp_array[i]);
1903*4882a593Smuzhiyun 		if (rc) {
1904*4882a593Smuzhiyun 			DP_ERR(edev, "Request fp %d irq failed\n", i);
1905*4882a593Smuzhiyun 			qede_sync_free_irqs(edev);
1906*4882a593Smuzhiyun 			return rc;
1907*4882a593Smuzhiyun 		}
1908*4882a593Smuzhiyun 		DP_VERBOSE(edev, NETIF_MSG_INTR,
1909*4882a593Smuzhiyun 			   "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
1910*4882a593Smuzhiyun 			   edev->fp_array[i].name, i,
1911*4882a593Smuzhiyun 			   &edev->fp_array[i]);
1912*4882a593Smuzhiyun 		edev->int_info.used_cnt++;
1913*4882a593Smuzhiyun 	}
1914*4882a593Smuzhiyun 
1915*4882a593Smuzhiyun 	return 0;
1916*4882a593Smuzhiyun }
1917*4882a593Smuzhiyun 
qede_simd_fp_handler(void * cookie)1918*4882a593Smuzhiyun static void qede_simd_fp_handler(void *cookie)
1919*4882a593Smuzhiyun {
1920*4882a593Smuzhiyun 	struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
1921*4882a593Smuzhiyun 
1922*4882a593Smuzhiyun 	napi_schedule_irqoff(&fp->napi);
1923*4882a593Smuzhiyun }
1924*4882a593Smuzhiyun 
qede_setup_irqs(struct qede_dev * edev)1925*4882a593Smuzhiyun static int qede_setup_irqs(struct qede_dev *edev)
1926*4882a593Smuzhiyun {
1927*4882a593Smuzhiyun 	int i, rc = 0;
1928*4882a593Smuzhiyun 
1929*4882a593Smuzhiyun 	/* Learn Interrupt configuration */
1930*4882a593Smuzhiyun 	rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
1931*4882a593Smuzhiyun 	if (rc)
1932*4882a593Smuzhiyun 		return rc;
1933*4882a593Smuzhiyun 
1934*4882a593Smuzhiyun 	if (edev->int_info.msix_cnt) {
1935*4882a593Smuzhiyun 		rc = qede_req_msix_irqs(edev);
1936*4882a593Smuzhiyun 		if (rc)
1937*4882a593Smuzhiyun 			return rc;
1938*4882a593Smuzhiyun 		edev->ndev->irq = edev->int_info.msix[0].vector;
1939*4882a593Smuzhiyun 	} else {
1940*4882a593Smuzhiyun 		const struct qed_common_ops *ops;
1941*4882a593Smuzhiyun 
1942*4882a593Smuzhiyun 		/* qed should learn receive the RSS ids and callbacks */
1943*4882a593Smuzhiyun 		ops = edev->ops->common;
1944*4882a593Smuzhiyun 		for (i = 0; i < QEDE_QUEUE_CNT(edev); i++)
1945*4882a593Smuzhiyun 			ops->simd_handler_config(edev->cdev,
1946*4882a593Smuzhiyun 						 &edev->fp_array[i], i,
1947*4882a593Smuzhiyun 						 qede_simd_fp_handler);
1948*4882a593Smuzhiyun 		edev->int_info.used_cnt = QEDE_QUEUE_CNT(edev);
1949*4882a593Smuzhiyun 	}
1950*4882a593Smuzhiyun 	return 0;
1951*4882a593Smuzhiyun }
1952*4882a593Smuzhiyun 
qede_drain_txq(struct qede_dev * edev,struct qede_tx_queue * txq,bool allow_drain)1953*4882a593Smuzhiyun static int qede_drain_txq(struct qede_dev *edev,
1954*4882a593Smuzhiyun 			  struct qede_tx_queue *txq, bool allow_drain)
1955*4882a593Smuzhiyun {
1956*4882a593Smuzhiyun 	int rc, cnt = 1000;
1957*4882a593Smuzhiyun 
1958*4882a593Smuzhiyun 	while (txq->sw_tx_cons != txq->sw_tx_prod) {
1959*4882a593Smuzhiyun 		if (!cnt) {
1960*4882a593Smuzhiyun 			if (allow_drain) {
1961*4882a593Smuzhiyun 				DP_NOTICE(edev,
1962*4882a593Smuzhiyun 					  "Tx queue[%d] is stuck, requesting MCP to drain\n",
1963*4882a593Smuzhiyun 					  txq->index);
1964*4882a593Smuzhiyun 				rc = edev->ops->common->drain(edev->cdev);
1965*4882a593Smuzhiyun 				if (rc)
1966*4882a593Smuzhiyun 					return rc;
1967*4882a593Smuzhiyun 				return qede_drain_txq(edev, txq, false);
1968*4882a593Smuzhiyun 			}
1969*4882a593Smuzhiyun 			DP_NOTICE(edev,
1970*4882a593Smuzhiyun 				  "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
1971*4882a593Smuzhiyun 				  txq->index, txq->sw_tx_prod,
1972*4882a593Smuzhiyun 				  txq->sw_tx_cons);
1973*4882a593Smuzhiyun 			return -ENODEV;
1974*4882a593Smuzhiyun 		}
1975*4882a593Smuzhiyun 		cnt--;
1976*4882a593Smuzhiyun 		usleep_range(1000, 2000);
1977*4882a593Smuzhiyun 		barrier();
1978*4882a593Smuzhiyun 	}
1979*4882a593Smuzhiyun 
1980*4882a593Smuzhiyun 	/* FW finished processing, wait for HW to transmit all tx packets */
1981*4882a593Smuzhiyun 	usleep_range(1000, 2000);
1982*4882a593Smuzhiyun 
1983*4882a593Smuzhiyun 	return 0;
1984*4882a593Smuzhiyun }
1985*4882a593Smuzhiyun 
qede_stop_txq(struct qede_dev * edev,struct qede_tx_queue * txq,int rss_id)1986*4882a593Smuzhiyun static int qede_stop_txq(struct qede_dev *edev,
1987*4882a593Smuzhiyun 			 struct qede_tx_queue *txq, int rss_id)
1988*4882a593Smuzhiyun {
1989*4882a593Smuzhiyun 	/* delete doorbell from doorbell recovery mechanism */
1990*4882a593Smuzhiyun 	edev->ops->common->db_recovery_del(edev->cdev, txq->doorbell_addr,
1991*4882a593Smuzhiyun 					   &txq->tx_db);
1992*4882a593Smuzhiyun 
1993*4882a593Smuzhiyun 	return edev->ops->q_tx_stop(edev->cdev, rss_id, txq->handle);
1994*4882a593Smuzhiyun }
1995*4882a593Smuzhiyun 
qede_stop_queues(struct qede_dev * edev)1996*4882a593Smuzhiyun static int qede_stop_queues(struct qede_dev *edev)
1997*4882a593Smuzhiyun {
1998*4882a593Smuzhiyun 	struct qed_update_vport_params *vport_update_params;
1999*4882a593Smuzhiyun 	struct qed_dev *cdev = edev->cdev;
2000*4882a593Smuzhiyun 	struct qede_fastpath *fp;
2001*4882a593Smuzhiyun 	int rc, i;
2002*4882a593Smuzhiyun 
2003*4882a593Smuzhiyun 	/* Disable the vport */
2004*4882a593Smuzhiyun 	vport_update_params = vzalloc(sizeof(*vport_update_params));
2005*4882a593Smuzhiyun 	if (!vport_update_params)
2006*4882a593Smuzhiyun 		return -ENOMEM;
2007*4882a593Smuzhiyun 
2008*4882a593Smuzhiyun 	vport_update_params->vport_id = 0;
2009*4882a593Smuzhiyun 	vport_update_params->update_vport_active_flg = 1;
2010*4882a593Smuzhiyun 	vport_update_params->vport_active_flg = 0;
2011*4882a593Smuzhiyun 	vport_update_params->update_rss_flg = 0;
2012*4882a593Smuzhiyun 
2013*4882a593Smuzhiyun 	rc = edev->ops->vport_update(cdev, vport_update_params);
2014*4882a593Smuzhiyun 	vfree(vport_update_params);
2015*4882a593Smuzhiyun 
2016*4882a593Smuzhiyun 	if (rc) {
2017*4882a593Smuzhiyun 		DP_ERR(edev, "Failed to update vport\n");
2018*4882a593Smuzhiyun 		return rc;
2019*4882a593Smuzhiyun 	}
2020*4882a593Smuzhiyun 
2021*4882a593Smuzhiyun 	/* Flush Tx queues. If needed, request drain from MCP */
2022*4882a593Smuzhiyun 	for_each_queue(i) {
2023*4882a593Smuzhiyun 		fp = &edev->fp_array[i];
2024*4882a593Smuzhiyun 
2025*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_TX) {
2026*4882a593Smuzhiyun 			int cos;
2027*4882a593Smuzhiyun 
2028*4882a593Smuzhiyun 			for_each_cos_in_txq(edev, cos) {
2029*4882a593Smuzhiyun 				rc = qede_drain_txq(edev, &fp->txq[cos], true);
2030*4882a593Smuzhiyun 				if (rc)
2031*4882a593Smuzhiyun 					return rc;
2032*4882a593Smuzhiyun 			}
2033*4882a593Smuzhiyun 		}
2034*4882a593Smuzhiyun 
2035*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_XDP) {
2036*4882a593Smuzhiyun 			rc = qede_drain_txq(edev, fp->xdp_tx, true);
2037*4882a593Smuzhiyun 			if (rc)
2038*4882a593Smuzhiyun 				return rc;
2039*4882a593Smuzhiyun 		}
2040*4882a593Smuzhiyun 	}
2041*4882a593Smuzhiyun 
2042*4882a593Smuzhiyun 	/* Stop all Queues in reverse order */
2043*4882a593Smuzhiyun 	for (i = QEDE_QUEUE_CNT(edev) - 1; i >= 0; i--) {
2044*4882a593Smuzhiyun 		fp = &edev->fp_array[i];
2045*4882a593Smuzhiyun 
2046*4882a593Smuzhiyun 		/* Stop the Tx Queue(s) */
2047*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_TX) {
2048*4882a593Smuzhiyun 			int cos;
2049*4882a593Smuzhiyun 
2050*4882a593Smuzhiyun 			for_each_cos_in_txq(edev, cos) {
2051*4882a593Smuzhiyun 				rc = qede_stop_txq(edev, &fp->txq[cos], i);
2052*4882a593Smuzhiyun 				if (rc)
2053*4882a593Smuzhiyun 					return rc;
2054*4882a593Smuzhiyun 			}
2055*4882a593Smuzhiyun 		}
2056*4882a593Smuzhiyun 
2057*4882a593Smuzhiyun 		/* Stop the Rx Queue */
2058*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_RX) {
2059*4882a593Smuzhiyun 			rc = edev->ops->q_rx_stop(cdev, i, fp->rxq->handle);
2060*4882a593Smuzhiyun 			if (rc) {
2061*4882a593Smuzhiyun 				DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
2062*4882a593Smuzhiyun 				return rc;
2063*4882a593Smuzhiyun 			}
2064*4882a593Smuzhiyun 		}
2065*4882a593Smuzhiyun 
2066*4882a593Smuzhiyun 		/* Stop the XDP forwarding queue */
2067*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_XDP) {
2068*4882a593Smuzhiyun 			rc = qede_stop_txq(edev, fp->xdp_tx, i);
2069*4882a593Smuzhiyun 			if (rc)
2070*4882a593Smuzhiyun 				return rc;
2071*4882a593Smuzhiyun 
2072*4882a593Smuzhiyun 			bpf_prog_put(fp->rxq->xdp_prog);
2073*4882a593Smuzhiyun 		}
2074*4882a593Smuzhiyun 	}
2075*4882a593Smuzhiyun 
2076*4882a593Smuzhiyun 	/* Stop the vport */
2077*4882a593Smuzhiyun 	rc = edev->ops->vport_stop(cdev, 0);
2078*4882a593Smuzhiyun 	if (rc)
2079*4882a593Smuzhiyun 		DP_ERR(edev, "Failed to stop VPORT\n");
2080*4882a593Smuzhiyun 
2081*4882a593Smuzhiyun 	return rc;
2082*4882a593Smuzhiyun }
2083*4882a593Smuzhiyun 
qede_start_txq(struct qede_dev * edev,struct qede_fastpath * fp,struct qede_tx_queue * txq,u8 rss_id,u16 sb_idx)2084*4882a593Smuzhiyun static int qede_start_txq(struct qede_dev *edev,
2085*4882a593Smuzhiyun 			  struct qede_fastpath *fp,
2086*4882a593Smuzhiyun 			  struct qede_tx_queue *txq, u8 rss_id, u16 sb_idx)
2087*4882a593Smuzhiyun {
2088*4882a593Smuzhiyun 	dma_addr_t phys_table = qed_chain_get_pbl_phys(&txq->tx_pbl);
2089*4882a593Smuzhiyun 	u32 page_cnt = qed_chain_get_page_cnt(&txq->tx_pbl);
2090*4882a593Smuzhiyun 	struct qed_queue_start_common_params params;
2091*4882a593Smuzhiyun 	struct qed_txq_start_ret_params ret_params;
2092*4882a593Smuzhiyun 	int rc;
2093*4882a593Smuzhiyun 
2094*4882a593Smuzhiyun 	memset(&params, 0, sizeof(params));
2095*4882a593Smuzhiyun 	memset(&ret_params, 0, sizeof(ret_params));
2096*4882a593Smuzhiyun 
2097*4882a593Smuzhiyun 	/* Let the XDP queue share the queue-zone with one of the regular txq.
2098*4882a593Smuzhiyun 	 * We don't really care about its coalescing.
2099*4882a593Smuzhiyun 	 */
2100*4882a593Smuzhiyun 	if (txq->is_xdp)
2101*4882a593Smuzhiyun 		params.queue_id = QEDE_TXQ_XDP_TO_IDX(edev, txq);
2102*4882a593Smuzhiyun 	else
2103*4882a593Smuzhiyun 		params.queue_id = txq->index;
2104*4882a593Smuzhiyun 
2105*4882a593Smuzhiyun 	params.p_sb = fp->sb_info;
2106*4882a593Smuzhiyun 	params.sb_idx = sb_idx;
2107*4882a593Smuzhiyun 	params.tc = txq->cos;
2108*4882a593Smuzhiyun 
2109*4882a593Smuzhiyun 	rc = edev->ops->q_tx_start(edev->cdev, rss_id, &params, phys_table,
2110*4882a593Smuzhiyun 				   page_cnt, &ret_params);
2111*4882a593Smuzhiyun 	if (rc) {
2112*4882a593Smuzhiyun 		DP_ERR(edev, "Start TXQ #%d failed %d\n", txq->index, rc);
2113*4882a593Smuzhiyun 		return rc;
2114*4882a593Smuzhiyun 	}
2115*4882a593Smuzhiyun 
2116*4882a593Smuzhiyun 	txq->doorbell_addr = ret_params.p_doorbell;
2117*4882a593Smuzhiyun 	txq->handle = ret_params.p_handle;
2118*4882a593Smuzhiyun 
2119*4882a593Smuzhiyun 	/* Determine the FW consumer address associated */
2120*4882a593Smuzhiyun 	txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[sb_idx];
2121*4882a593Smuzhiyun 
2122*4882a593Smuzhiyun 	/* Prepare the doorbell parameters */
2123*4882a593Smuzhiyun 	SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST, DB_DEST_XCM);
2124*4882a593Smuzhiyun 	SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
2125*4882a593Smuzhiyun 	SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_VAL_SEL,
2126*4882a593Smuzhiyun 		  DQ_XCM_ETH_TX_BD_PROD_CMD);
2127*4882a593Smuzhiyun 	txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
2128*4882a593Smuzhiyun 
2129*4882a593Smuzhiyun 	/* register doorbell with doorbell recovery mechanism */
2130*4882a593Smuzhiyun 	rc = edev->ops->common->db_recovery_add(edev->cdev, txq->doorbell_addr,
2131*4882a593Smuzhiyun 						&txq->tx_db, DB_REC_WIDTH_32B,
2132*4882a593Smuzhiyun 						DB_REC_KERNEL);
2133*4882a593Smuzhiyun 
2134*4882a593Smuzhiyun 	return rc;
2135*4882a593Smuzhiyun }
2136*4882a593Smuzhiyun 
qede_start_queues(struct qede_dev * edev,bool clear_stats)2137*4882a593Smuzhiyun static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2138*4882a593Smuzhiyun {
2139*4882a593Smuzhiyun 	int vlan_removal_en = 1;
2140*4882a593Smuzhiyun 	struct qed_dev *cdev = edev->cdev;
2141*4882a593Smuzhiyun 	struct qed_dev_info *qed_info = &edev->dev_info.common;
2142*4882a593Smuzhiyun 	struct qed_update_vport_params *vport_update_params;
2143*4882a593Smuzhiyun 	struct qed_queue_start_common_params q_params;
2144*4882a593Smuzhiyun 	struct qed_start_vport_params start = {0};
2145*4882a593Smuzhiyun 	int rc, i;
2146*4882a593Smuzhiyun 
2147*4882a593Smuzhiyun 	if (!edev->num_queues) {
2148*4882a593Smuzhiyun 		DP_ERR(edev,
2149*4882a593Smuzhiyun 		       "Cannot update V-VPORT as active as there are no Rx queues\n");
2150*4882a593Smuzhiyun 		return -EINVAL;
2151*4882a593Smuzhiyun 	}
2152*4882a593Smuzhiyun 
2153*4882a593Smuzhiyun 	vport_update_params = vzalloc(sizeof(*vport_update_params));
2154*4882a593Smuzhiyun 	if (!vport_update_params)
2155*4882a593Smuzhiyun 		return -ENOMEM;
2156*4882a593Smuzhiyun 
2157*4882a593Smuzhiyun 	start.handle_ptp_pkts = !!(edev->ptp);
2158*4882a593Smuzhiyun 	start.gro_enable = !edev->gro_disable;
2159*4882a593Smuzhiyun 	start.mtu = edev->ndev->mtu;
2160*4882a593Smuzhiyun 	start.vport_id = 0;
2161*4882a593Smuzhiyun 	start.drop_ttl0 = true;
2162*4882a593Smuzhiyun 	start.remove_inner_vlan = vlan_removal_en;
2163*4882a593Smuzhiyun 	start.clear_stats = clear_stats;
2164*4882a593Smuzhiyun 
2165*4882a593Smuzhiyun 	rc = edev->ops->vport_start(cdev, &start);
2166*4882a593Smuzhiyun 
2167*4882a593Smuzhiyun 	if (rc) {
2168*4882a593Smuzhiyun 		DP_ERR(edev, "Start V-PORT failed %d\n", rc);
2169*4882a593Smuzhiyun 		goto out;
2170*4882a593Smuzhiyun 	}
2171*4882a593Smuzhiyun 
2172*4882a593Smuzhiyun 	DP_VERBOSE(edev, NETIF_MSG_IFUP,
2173*4882a593Smuzhiyun 		   "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
2174*4882a593Smuzhiyun 		   start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2175*4882a593Smuzhiyun 
2176*4882a593Smuzhiyun 	for_each_queue(i) {
2177*4882a593Smuzhiyun 		struct qede_fastpath *fp = &edev->fp_array[i];
2178*4882a593Smuzhiyun 		dma_addr_t p_phys_table;
2179*4882a593Smuzhiyun 		u32 page_cnt;
2180*4882a593Smuzhiyun 
2181*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_RX) {
2182*4882a593Smuzhiyun 			struct qed_rxq_start_ret_params ret_params;
2183*4882a593Smuzhiyun 			struct qede_rx_queue *rxq = fp->rxq;
2184*4882a593Smuzhiyun 			__le16 *val;
2185*4882a593Smuzhiyun 
2186*4882a593Smuzhiyun 			memset(&ret_params, 0, sizeof(ret_params));
2187*4882a593Smuzhiyun 			memset(&q_params, 0, sizeof(q_params));
2188*4882a593Smuzhiyun 			q_params.queue_id = rxq->rxq_id;
2189*4882a593Smuzhiyun 			q_params.vport_id = 0;
2190*4882a593Smuzhiyun 			q_params.p_sb = fp->sb_info;
2191*4882a593Smuzhiyun 			q_params.sb_idx = RX_PI;
2192*4882a593Smuzhiyun 
2193*4882a593Smuzhiyun 			p_phys_table =
2194*4882a593Smuzhiyun 			    qed_chain_get_pbl_phys(&rxq->rx_comp_ring);
2195*4882a593Smuzhiyun 			page_cnt = qed_chain_get_page_cnt(&rxq->rx_comp_ring);
2196*4882a593Smuzhiyun 
2197*4882a593Smuzhiyun 			rc = edev->ops->q_rx_start(cdev, i, &q_params,
2198*4882a593Smuzhiyun 						   rxq->rx_buf_size,
2199*4882a593Smuzhiyun 						   rxq->rx_bd_ring.p_phys_addr,
2200*4882a593Smuzhiyun 						   p_phys_table,
2201*4882a593Smuzhiyun 						   page_cnt, &ret_params);
2202*4882a593Smuzhiyun 			if (rc) {
2203*4882a593Smuzhiyun 				DP_ERR(edev, "Start RXQ #%d failed %d\n", i,
2204*4882a593Smuzhiyun 				       rc);
2205*4882a593Smuzhiyun 				goto out;
2206*4882a593Smuzhiyun 			}
2207*4882a593Smuzhiyun 
2208*4882a593Smuzhiyun 			/* Use the return parameters */
2209*4882a593Smuzhiyun 			rxq->hw_rxq_prod_addr = ret_params.p_prod;
2210*4882a593Smuzhiyun 			rxq->handle = ret_params.p_handle;
2211*4882a593Smuzhiyun 
2212*4882a593Smuzhiyun 			val = &fp->sb_info->sb_virt->pi_array[RX_PI];
2213*4882a593Smuzhiyun 			rxq->hw_cons_ptr = val;
2214*4882a593Smuzhiyun 
2215*4882a593Smuzhiyun 			qede_update_rx_prod(edev, rxq);
2216*4882a593Smuzhiyun 		}
2217*4882a593Smuzhiyun 
2218*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_XDP) {
2219*4882a593Smuzhiyun 			rc = qede_start_txq(edev, fp, fp->xdp_tx, i, XDP_PI);
2220*4882a593Smuzhiyun 			if (rc)
2221*4882a593Smuzhiyun 				goto out;
2222*4882a593Smuzhiyun 
2223*4882a593Smuzhiyun 			bpf_prog_add(edev->xdp_prog, 1);
2224*4882a593Smuzhiyun 			fp->rxq->xdp_prog = edev->xdp_prog;
2225*4882a593Smuzhiyun 		}
2226*4882a593Smuzhiyun 
2227*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_TX) {
2228*4882a593Smuzhiyun 			int cos;
2229*4882a593Smuzhiyun 
2230*4882a593Smuzhiyun 			for_each_cos_in_txq(edev, cos) {
2231*4882a593Smuzhiyun 				rc = qede_start_txq(edev, fp, &fp->txq[cos], i,
2232*4882a593Smuzhiyun 						    TX_PI(cos));
2233*4882a593Smuzhiyun 				if (rc)
2234*4882a593Smuzhiyun 					goto out;
2235*4882a593Smuzhiyun 			}
2236*4882a593Smuzhiyun 		}
2237*4882a593Smuzhiyun 	}
2238*4882a593Smuzhiyun 
2239*4882a593Smuzhiyun 	/* Prepare and send the vport enable */
2240*4882a593Smuzhiyun 	vport_update_params->vport_id = start.vport_id;
2241*4882a593Smuzhiyun 	vport_update_params->update_vport_active_flg = 1;
2242*4882a593Smuzhiyun 	vport_update_params->vport_active_flg = 1;
2243*4882a593Smuzhiyun 
2244*4882a593Smuzhiyun 	if ((qed_info->b_inter_pf_switch || pci_num_vf(edev->pdev)) &&
2245*4882a593Smuzhiyun 	    qed_info->tx_switching) {
2246*4882a593Smuzhiyun 		vport_update_params->update_tx_switching_flg = 1;
2247*4882a593Smuzhiyun 		vport_update_params->tx_switching_flg = 1;
2248*4882a593Smuzhiyun 	}
2249*4882a593Smuzhiyun 
2250*4882a593Smuzhiyun 	qede_fill_rss_params(edev, &vport_update_params->rss_params,
2251*4882a593Smuzhiyun 			     &vport_update_params->update_rss_flg);
2252*4882a593Smuzhiyun 
2253*4882a593Smuzhiyun 	rc = edev->ops->vport_update(cdev, vport_update_params);
2254*4882a593Smuzhiyun 	if (rc)
2255*4882a593Smuzhiyun 		DP_ERR(edev, "Update V-PORT failed %d\n", rc);
2256*4882a593Smuzhiyun 
2257*4882a593Smuzhiyun out:
2258*4882a593Smuzhiyun 	vfree(vport_update_params);
2259*4882a593Smuzhiyun 	return rc;
2260*4882a593Smuzhiyun }
2261*4882a593Smuzhiyun 
2262*4882a593Smuzhiyun enum qede_unload_mode {
2263*4882a593Smuzhiyun 	QEDE_UNLOAD_NORMAL,
2264*4882a593Smuzhiyun 	QEDE_UNLOAD_RECOVERY,
2265*4882a593Smuzhiyun };
2266*4882a593Smuzhiyun 
qede_unload(struct qede_dev * edev,enum qede_unload_mode mode,bool is_locked)2267*4882a593Smuzhiyun static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode,
2268*4882a593Smuzhiyun 			bool is_locked)
2269*4882a593Smuzhiyun {
2270*4882a593Smuzhiyun 	struct qed_link_params link_params;
2271*4882a593Smuzhiyun 	int rc;
2272*4882a593Smuzhiyun 
2273*4882a593Smuzhiyun 	DP_INFO(edev, "Starting qede unload\n");
2274*4882a593Smuzhiyun 
2275*4882a593Smuzhiyun 	if (!is_locked)
2276*4882a593Smuzhiyun 		__qede_lock(edev);
2277*4882a593Smuzhiyun 
2278*4882a593Smuzhiyun 	clear_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags);
2279*4882a593Smuzhiyun 
2280*4882a593Smuzhiyun 	if (mode != QEDE_UNLOAD_RECOVERY)
2281*4882a593Smuzhiyun 		edev->state = QEDE_STATE_CLOSED;
2282*4882a593Smuzhiyun 
2283*4882a593Smuzhiyun 	qede_rdma_dev_event_close(edev);
2284*4882a593Smuzhiyun 
2285*4882a593Smuzhiyun 	/* Close OS Tx */
2286*4882a593Smuzhiyun 	netif_tx_disable(edev->ndev);
2287*4882a593Smuzhiyun 	netif_carrier_off(edev->ndev);
2288*4882a593Smuzhiyun 
2289*4882a593Smuzhiyun 	if (mode != QEDE_UNLOAD_RECOVERY) {
2290*4882a593Smuzhiyun 		/* Reset the link */
2291*4882a593Smuzhiyun 		memset(&link_params, 0, sizeof(link_params));
2292*4882a593Smuzhiyun 		link_params.link_up = false;
2293*4882a593Smuzhiyun 		edev->ops->common->set_link(edev->cdev, &link_params);
2294*4882a593Smuzhiyun 
2295*4882a593Smuzhiyun 		rc = qede_stop_queues(edev);
2296*4882a593Smuzhiyun 		if (rc) {
2297*4882a593Smuzhiyun 			qede_sync_free_irqs(edev);
2298*4882a593Smuzhiyun 			goto out;
2299*4882a593Smuzhiyun 		}
2300*4882a593Smuzhiyun 
2301*4882a593Smuzhiyun 		DP_INFO(edev, "Stopped Queues\n");
2302*4882a593Smuzhiyun 	}
2303*4882a593Smuzhiyun 
2304*4882a593Smuzhiyun 	qede_vlan_mark_nonconfigured(edev);
2305*4882a593Smuzhiyun 	edev->ops->fastpath_stop(edev->cdev);
2306*4882a593Smuzhiyun 
2307*4882a593Smuzhiyun 	if (edev->dev_info.common.b_arfs_capable) {
2308*4882a593Smuzhiyun 		qede_poll_for_freeing_arfs_filters(edev);
2309*4882a593Smuzhiyun 		qede_free_arfs(edev);
2310*4882a593Smuzhiyun 	}
2311*4882a593Smuzhiyun 
2312*4882a593Smuzhiyun 	/* Release the interrupts */
2313*4882a593Smuzhiyun 	qede_sync_free_irqs(edev);
2314*4882a593Smuzhiyun 	edev->ops->common->set_fp_int(edev->cdev, 0);
2315*4882a593Smuzhiyun 
2316*4882a593Smuzhiyun 	qede_napi_disable_remove(edev);
2317*4882a593Smuzhiyun 
2318*4882a593Smuzhiyun 	if (mode == QEDE_UNLOAD_RECOVERY)
2319*4882a593Smuzhiyun 		qede_empty_tx_queues(edev);
2320*4882a593Smuzhiyun 
2321*4882a593Smuzhiyun 	qede_free_mem_load(edev);
2322*4882a593Smuzhiyun 	qede_free_fp_array(edev);
2323*4882a593Smuzhiyun 
2324*4882a593Smuzhiyun out:
2325*4882a593Smuzhiyun 	if (!is_locked)
2326*4882a593Smuzhiyun 		__qede_unlock(edev);
2327*4882a593Smuzhiyun 
2328*4882a593Smuzhiyun 	if (mode != QEDE_UNLOAD_RECOVERY)
2329*4882a593Smuzhiyun 		DP_NOTICE(edev, "Link is down\n");
2330*4882a593Smuzhiyun 
2331*4882a593Smuzhiyun 	edev->ptp_skip_txts = 0;
2332*4882a593Smuzhiyun 
2333*4882a593Smuzhiyun 	DP_INFO(edev, "Ending qede unload\n");
2334*4882a593Smuzhiyun }
2335*4882a593Smuzhiyun 
2336*4882a593Smuzhiyun enum qede_load_mode {
2337*4882a593Smuzhiyun 	QEDE_LOAD_NORMAL,
2338*4882a593Smuzhiyun 	QEDE_LOAD_RELOAD,
2339*4882a593Smuzhiyun 	QEDE_LOAD_RECOVERY,
2340*4882a593Smuzhiyun };
2341*4882a593Smuzhiyun 
qede_load(struct qede_dev * edev,enum qede_load_mode mode,bool is_locked)2342*4882a593Smuzhiyun static int qede_load(struct qede_dev *edev, enum qede_load_mode mode,
2343*4882a593Smuzhiyun 		     bool is_locked)
2344*4882a593Smuzhiyun {
2345*4882a593Smuzhiyun 	struct qed_link_params link_params;
2346*4882a593Smuzhiyun 	u8 num_tc;
2347*4882a593Smuzhiyun 	int rc;
2348*4882a593Smuzhiyun 
2349*4882a593Smuzhiyun 	DP_INFO(edev, "Starting qede load\n");
2350*4882a593Smuzhiyun 
2351*4882a593Smuzhiyun 	if (!is_locked)
2352*4882a593Smuzhiyun 		__qede_lock(edev);
2353*4882a593Smuzhiyun 
2354*4882a593Smuzhiyun 	rc = qede_set_num_queues(edev);
2355*4882a593Smuzhiyun 	if (rc)
2356*4882a593Smuzhiyun 		goto out;
2357*4882a593Smuzhiyun 
2358*4882a593Smuzhiyun 	rc = qede_alloc_fp_array(edev);
2359*4882a593Smuzhiyun 	if (rc)
2360*4882a593Smuzhiyun 		goto out;
2361*4882a593Smuzhiyun 
2362*4882a593Smuzhiyun 	qede_init_fp(edev);
2363*4882a593Smuzhiyun 
2364*4882a593Smuzhiyun 	rc = qede_alloc_mem_load(edev);
2365*4882a593Smuzhiyun 	if (rc)
2366*4882a593Smuzhiyun 		goto err1;
2367*4882a593Smuzhiyun 	DP_INFO(edev, "Allocated %d Rx, %d Tx queues\n",
2368*4882a593Smuzhiyun 		QEDE_RSS_COUNT(edev), QEDE_TSS_COUNT(edev));
2369*4882a593Smuzhiyun 
2370*4882a593Smuzhiyun 	rc = qede_set_real_num_queues(edev);
2371*4882a593Smuzhiyun 	if (rc)
2372*4882a593Smuzhiyun 		goto err2;
2373*4882a593Smuzhiyun 
2374*4882a593Smuzhiyun 	if (qede_alloc_arfs(edev)) {
2375*4882a593Smuzhiyun 		edev->ndev->features &= ~NETIF_F_NTUPLE;
2376*4882a593Smuzhiyun 		edev->dev_info.common.b_arfs_capable = false;
2377*4882a593Smuzhiyun 	}
2378*4882a593Smuzhiyun 
2379*4882a593Smuzhiyun 	qede_napi_add_enable(edev);
2380*4882a593Smuzhiyun 	DP_INFO(edev, "Napi added and enabled\n");
2381*4882a593Smuzhiyun 
2382*4882a593Smuzhiyun 	rc = qede_setup_irqs(edev);
2383*4882a593Smuzhiyun 	if (rc)
2384*4882a593Smuzhiyun 		goto err3;
2385*4882a593Smuzhiyun 	DP_INFO(edev, "Setup IRQs succeeded\n");
2386*4882a593Smuzhiyun 
2387*4882a593Smuzhiyun 	rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2388*4882a593Smuzhiyun 	if (rc)
2389*4882a593Smuzhiyun 		goto err4;
2390*4882a593Smuzhiyun 	DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
2391*4882a593Smuzhiyun 
2392*4882a593Smuzhiyun 	num_tc = netdev_get_num_tc(edev->ndev);
2393*4882a593Smuzhiyun 	num_tc = num_tc ? num_tc : edev->dev_info.num_tc;
2394*4882a593Smuzhiyun 	qede_setup_tc(edev->ndev, num_tc);
2395*4882a593Smuzhiyun 
2396*4882a593Smuzhiyun 	/* Program un-configured VLANs */
2397*4882a593Smuzhiyun 	qede_configure_vlan_filters(edev);
2398*4882a593Smuzhiyun 
2399*4882a593Smuzhiyun 	set_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags);
2400*4882a593Smuzhiyun 
2401*4882a593Smuzhiyun 	/* Ask for link-up using current configuration */
2402*4882a593Smuzhiyun 	memset(&link_params, 0, sizeof(link_params));
2403*4882a593Smuzhiyun 	link_params.link_up = true;
2404*4882a593Smuzhiyun 	edev->ops->common->set_link(edev->cdev, &link_params);
2405*4882a593Smuzhiyun 
2406*4882a593Smuzhiyun 	edev->state = QEDE_STATE_OPEN;
2407*4882a593Smuzhiyun 
2408*4882a593Smuzhiyun 	DP_INFO(edev, "Ending successfully qede load\n");
2409*4882a593Smuzhiyun 
2410*4882a593Smuzhiyun 	goto out;
2411*4882a593Smuzhiyun err4:
2412*4882a593Smuzhiyun 	qede_sync_free_irqs(edev);
2413*4882a593Smuzhiyun err3:
2414*4882a593Smuzhiyun 	qede_napi_disable_remove(edev);
2415*4882a593Smuzhiyun err2:
2416*4882a593Smuzhiyun 	qede_free_mem_load(edev);
2417*4882a593Smuzhiyun err1:
2418*4882a593Smuzhiyun 	edev->ops->common->set_fp_int(edev->cdev, 0);
2419*4882a593Smuzhiyun 	qede_free_fp_array(edev);
2420*4882a593Smuzhiyun 	edev->num_queues = 0;
2421*4882a593Smuzhiyun 	edev->fp_num_tx = 0;
2422*4882a593Smuzhiyun 	edev->fp_num_rx = 0;
2423*4882a593Smuzhiyun out:
2424*4882a593Smuzhiyun 	if (!is_locked)
2425*4882a593Smuzhiyun 		__qede_unlock(edev);
2426*4882a593Smuzhiyun 
2427*4882a593Smuzhiyun 	return rc;
2428*4882a593Smuzhiyun }
2429*4882a593Smuzhiyun 
2430*4882a593Smuzhiyun /* 'func' should be able to run between unload and reload assuming interface
2431*4882a593Smuzhiyun  * is actually running, or afterwards in case it's currently DOWN.
2432*4882a593Smuzhiyun  */
qede_reload(struct qede_dev * edev,struct qede_reload_args * args,bool is_locked)2433*4882a593Smuzhiyun void qede_reload(struct qede_dev *edev,
2434*4882a593Smuzhiyun 		 struct qede_reload_args *args, bool is_locked)
2435*4882a593Smuzhiyun {
2436*4882a593Smuzhiyun 	if (!is_locked)
2437*4882a593Smuzhiyun 		__qede_lock(edev);
2438*4882a593Smuzhiyun 
2439*4882a593Smuzhiyun 	/* Since qede_lock is held, internal state wouldn't change even
2440*4882a593Smuzhiyun 	 * if netdev state would start transitioning. Check whether current
2441*4882a593Smuzhiyun 	 * internal configuration indicates device is up, then reload.
2442*4882a593Smuzhiyun 	 */
2443*4882a593Smuzhiyun 	if (edev->state == QEDE_STATE_OPEN) {
2444*4882a593Smuzhiyun 		qede_unload(edev, QEDE_UNLOAD_NORMAL, true);
2445*4882a593Smuzhiyun 		if (args)
2446*4882a593Smuzhiyun 			args->func(edev, args);
2447*4882a593Smuzhiyun 		qede_load(edev, QEDE_LOAD_RELOAD, true);
2448*4882a593Smuzhiyun 
2449*4882a593Smuzhiyun 		/* Since no one is going to do it for us, re-configure */
2450*4882a593Smuzhiyun 		qede_config_rx_mode(edev->ndev);
2451*4882a593Smuzhiyun 	} else if (args) {
2452*4882a593Smuzhiyun 		args->func(edev, args);
2453*4882a593Smuzhiyun 	}
2454*4882a593Smuzhiyun 
2455*4882a593Smuzhiyun 	if (!is_locked)
2456*4882a593Smuzhiyun 		__qede_unlock(edev);
2457*4882a593Smuzhiyun }
2458*4882a593Smuzhiyun 
2459*4882a593Smuzhiyun /* called with rtnl_lock */
qede_open(struct net_device * ndev)2460*4882a593Smuzhiyun static int qede_open(struct net_device *ndev)
2461*4882a593Smuzhiyun {
2462*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(ndev);
2463*4882a593Smuzhiyun 	int rc;
2464*4882a593Smuzhiyun 
2465*4882a593Smuzhiyun 	netif_carrier_off(ndev);
2466*4882a593Smuzhiyun 
2467*4882a593Smuzhiyun 	edev->ops->common->set_power_state(edev->cdev, PCI_D0);
2468*4882a593Smuzhiyun 
2469*4882a593Smuzhiyun 	rc = qede_load(edev, QEDE_LOAD_NORMAL, false);
2470*4882a593Smuzhiyun 	if (rc)
2471*4882a593Smuzhiyun 		return rc;
2472*4882a593Smuzhiyun 
2473*4882a593Smuzhiyun 	udp_tunnel_nic_reset_ntf(ndev);
2474*4882a593Smuzhiyun 
2475*4882a593Smuzhiyun 	edev->ops->common->update_drv_state(edev->cdev, true);
2476*4882a593Smuzhiyun 
2477*4882a593Smuzhiyun 	return 0;
2478*4882a593Smuzhiyun }
2479*4882a593Smuzhiyun 
qede_close(struct net_device * ndev)2480*4882a593Smuzhiyun static int qede_close(struct net_device *ndev)
2481*4882a593Smuzhiyun {
2482*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(ndev);
2483*4882a593Smuzhiyun 
2484*4882a593Smuzhiyun 	qede_unload(edev, QEDE_UNLOAD_NORMAL, false);
2485*4882a593Smuzhiyun 
2486*4882a593Smuzhiyun 	if (edev->cdev)
2487*4882a593Smuzhiyun 		edev->ops->common->update_drv_state(edev->cdev, false);
2488*4882a593Smuzhiyun 
2489*4882a593Smuzhiyun 	return 0;
2490*4882a593Smuzhiyun }
2491*4882a593Smuzhiyun 
qede_link_update(void * dev,struct qed_link_output * link)2492*4882a593Smuzhiyun static void qede_link_update(void *dev, struct qed_link_output *link)
2493*4882a593Smuzhiyun {
2494*4882a593Smuzhiyun 	struct qede_dev *edev = dev;
2495*4882a593Smuzhiyun 
2496*4882a593Smuzhiyun 	if (!test_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags)) {
2497*4882a593Smuzhiyun 		DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not ready\n");
2498*4882a593Smuzhiyun 		return;
2499*4882a593Smuzhiyun 	}
2500*4882a593Smuzhiyun 
2501*4882a593Smuzhiyun 	if (link->link_up) {
2502*4882a593Smuzhiyun 		if (!netif_carrier_ok(edev->ndev)) {
2503*4882a593Smuzhiyun 			DP_NOTICE(edev, "Link is up\n");
2504*4882a593Smuzhiyun 			netif_tx_start_all_queues(edev->ndev);
2505*4882a593Smuzhiyun 			netif_carrier_on(edev->ndev);
2506*4882a593Smuzhiyun 			qede_rdma_dev_event_open(edev);
2507*4882a593Smuzhiyun 		}
2508*4882a593Smuzhiyun 	} else {
2509*4882a593Smuzhiyun 		if (netif_carrier_ok(edev->ndev)) {
2510*4882a593Smuzhiyun 			DP_NOTICE(edev, "Link is down\n");
2511*4882a593Smuzhiyun 			netif_tx_disable(edev->ndev);
2512*4882a593Smuzhiyun 			netif_carrier_off(edev->ndev);
2513*4882a593Smuzhiyun 			qede_rdma_dev_event_close(edev);
2514*4882a593Smuzhiyun 		}
2515*4882a593Smuzhiyun 	}
2516*4882a593Smuzhiyun }
2517*4882a593Smuzhiyun 
qede_schedule_recovery_handler(void * dev)2518*4882a593Smuzhiyun static void qede_schedule_recovery_handler(void *dev)
2519*4882a593Smuzhiyun {
2520*4882a593Smuzhiyun 	struct qede_dev *edev = dev;
2521*4882a593Smuzhiyun 
2522*4882a593Smuzhiyun 	if (edev->state == QEDE_STATE_RECOVERY) {
2523*4882a593Smuzhiyun 		DP_NOTICE(edev,
2524*4882a593Smuzhiyun 			  "Avoid scheduling a recovery handling since already in recovery state\n");
2525*4882a593Smuzhiyun 		return;
2526*4882a593Smuzhiyun 	}
2527*4882a593Smuzhiyun 
2528*4882a593Smuzhiyun 	set_bit(QEDE_SP_RECOVERY, &edev->sp_flags);
2529*4882a593Smuzhiyun 	schedule_delayed_work(&edev->sp_task, 0);
2530*4882a593Smuzhiyun 
2531*4882a593Smuzhiyun 	DP_INFO(edev, "Scheduled a recovery handler\n");
2532*4882a593Smuzhiyun }
2533*4882a593Smuzhiyun 
qede_recovery_failed(struct qede_dev * edev)2534*4882a593Smuzhiyun static void qede_recovery_failed(struct qede_dev *edev)
2535*4882a593Smuzhiyun {
2536*4882a593Smuzhiyun 	netdev_err(edev->ndev, "Recovery handling has failed. Power cycle is needed.\n");
2537*4882a593Smuzhiyun 
2538*4882a593Smuzhiyun 	netif_device_detach(edev->ndev);
2539*4882a593Smuzhiyun 
2540*4882a593Smuzhiyun 	if (edev->cdev)
2541*4882a593Smuzhiyun 		edev->ops->common->set_power_state(edev->cdev, PCI_D3hot);
2542*4882a593Smuzhiyun }
2543*4882a593Smuzhiyun 
qede_recovery_handler(struct qede_dev * edev)2544*4882a593Smuzhiyun static void qede_recovery_handler(struct qede_dev *edev)
2545*4882a593Smuzhiyun {
2546*4882a593Smuzhiyun 	u32 curr_state = edev->state;
2547*4882a593Smuzhiyun 	int rc;
2548*4882a593Smuzhiyun 
2549*4882a593Smuzhiyun 	DP_NOTICE(edev, "Starting a recovery process\n");
2550*4882a593Smuzhiyun 
2551*4882a593Smuzhiyun 	/* No need to acquire first the qede_lock since is done by qede_sp_task
2552*4882a593Smuzhiyun 	 * before calling this function.
2553*4882a593Smuzhiyun 	 */
2554*4882a593Smuzhiyun 	edev->state = QEDE_STATE_RECOVERY;
2555*4882a593Smuzhiyun 
2556*4882a593Smuzhiyun 	edev->ops->common->recovery_prolog(edev->cdev);
2557*4882a593Smuzhiyun 
2558*4882a593Smuzhiyun 	if (curr_state == QEDE_STATE_OPEN)
2559*4882a593Smuzhiyun 		qede_unload(edev, QEDE_UNLOAD_RECOVERY, true);
2560*4882a593Smuzhiyun 
2561*4882a593Smuzhiyun 	__qede_remove(edev->pdev, QEDE_REMOVE_RECOVERY);
2562*4882a593Smuzhiyun 
2563*4882a593Smuzhiyun 	rc = __qede_probe(edev->pdev, edev->dp_module, edev->dp_level,
2564*4882a593Smuzhiyun 			  IS_VF(edev), QEDE_PROBE_RECOVERY);
2565*4882a593Smuzhiyun 	if (rc) {
2566*4882a593Smuzhiyun 		edev->cdev = NULL;
2567*4882a593Smuzhiyun 		goto err;
2568*4882a593Smuzhiyun 	}
2569*4882a593Smuzhiyun 
2570*4882a593Smuzhiyun 	if (curr_state == QEDE_STATE_OPEN) {
2571*4882a593Smuzhiyun 		rc = qede_load(edev, QEDE_LOAD_RECOVERY, true);
2572*4882a593Smuzhiyun 		if (rc)
2573*4882a593Smuzhiyun 			goto err;
2574*4882a593Smuzhiyun 
2575*4882a593Smuzhiyun 		qede_config_rx_mode(edev->ndev);
2576*4882a593Smuzhiyun 		udp_tunnel_nic_reset_ntf(edev->ndev);
2577*4882a593Smuzhiyun 	}
2578*4882a593Smuzhiyun 
2579*4882a593Smuzhiyun 	edev->state = curr_state;
2580*4882a593Smuzhiyun 
2581*4882a593Smuzhiyun 	DP_NOTICE(edev, "Recovery handling is done\n");
2582*4882a593Smuzhiyun 
2583*4882a593Smuzhiyun 	return;
2584*4882a593Smuzhiyun 
2585*4882a593Smuzhiyun err:
2586*4882a593Smuzhiyun 	qede_recovery_failed(edev);
2587*4882a593Smuzhiyun }
2588*4882a593Smuzhiyun 
qede_atomic_hw_err_handler(struct qede_dev * edev)2589*4882a593Smuzhiyun static void qede_atomic_hw_err_handler(struct qede_dev *edev)
2590*4882a593Smuzhiyun {
2591*4882a593Smuzhiyun 	struct qed_dev *cdev = edev->cdev;
2592*4882a593Smuzhiyun 
2593*4882a593Smuzhiyun 	DP_NOTICE(edev,
2594*4882a593Smuzhiyun 		  "Generic non-sleepable HW error handling started - err_flags 0x%lx\n",
2595*4882a593Smuzhiyun 		  edev->err_flags);
2596*4882a593Smuzhiyun 
2597*4882a593Smuzhiyun 	/* Get a call trace of the flow that led to the error */
2598*4882a593Smuzhiyun 	WARN_ON(test_bit(QEDE_ERR_WARN, &edev->err_flags));
2599*4882a593Smuzhiyun 
2600*4882a593Smuzhiyun 	/* Prevent HW attentions from being reasserted */
2601*4882a593Smuzhiyun 	if (test_bit(QEDE_ERR_ATTN_CLR_EN, &edev->err_flags))
2602*4882a593Smuzhiyun 		edev->ops->common->attn_clr_enable(cdev, true);
2603*4882a593Smuzhiyun 
2604*4882a593Smuzhiyun 	DP_NOTICE(edev, "Generic non-sleepable HW error handling is done\n");
2605*4882a593Smuzhiyun }
2606*4882a593Smuzhiyun 
qede_generic_hw_err_handler(struct qede_dev * edev)2607*4882a593Smuzhiyun static void qede_generic_hw_err_handler(struct qede_dev *edev)
2608*4882a593Smuzhiyun {
2609*4882a593Smuzhiyun 	DP_NOTICE(edev,
2610*4882a593Smuzhiyun 		  "Generic sleepable HW error handling started - err_flags 0x%lx\n",
2611*4882a593Smuzhiyun 		  edev->err_flags);
2612*4882a593Smuzhiyun 
2613*4882a593Smuzhiyun 	if (edev->devlink)
2614*4882a593Smuzhiyun 		edev->ops->common->report_fatal_error(edev->devlink, edev->last_err_type);
2615*4882a593Smuzhiyun 
2616*4882a593Smuzhiyun 	clear_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags);
2617*4882a593Smuzhiyun 
2618*4882a593Smuzhiyun 	DP_NOTICE(edev, "Generic sleepable HW error handling is done\n");
2619*4882a593Smuzhiyun }
2620*4882a593Smuzhiyun 
qede_set_hw_err_flags(struct qede_dev * edev,enum qed_hw_err_type err_type)2621*4882a593Smuzhiyun static void qede_set_hw_err_flags(struct qede_dev *edev,
2622*4882a593Smuzhiyun 				  enum qed_hw_err_type err_type)
2623*4882a593Smuzhiyun {
2624*4882a593Smuzhiyun 	unsigned long err_flags = 0;
2625*4882a593Smuzhiyun 
2626*4882a593Smuzhiyun 	switch (err_type) {
2627*4882a593Smuzhiyun 	case QED_HW_ERR_DMAE_FAIL:
2628*4882a593Smuzhiyun 		set_bit(QEDE_ERR_WARN, &err_flags);
2629*4882a593Smuzhiyun 		fallthrough;
2630*4882a593Smuzhiyun 	case QED_HW_ERR_MFW_RESP_FAIL:
2631*4882a593Smuzhiyun 	case QED_HW_ERR_HW_ATTN:
2632*4882a593Smuzhiyun 	case QED_HW_ERR_RAMROD_FAIL:
2633*4882a593Smuzhiyun 	case QED_HW_ERR_FW_ASSERT:
2634*4882a593Smuzhiyun 		set_bit(QEDE_ERR_ATTN_CLR_EN, &err_flags);
2635*4882a593Smuzhiyun 		set_bit(QEDE_ERR_GET_DBG_INFO, &err_flags);
2636*4882a593Smuzhiyun 		break;
2637*4882a593Smuzhiyun 
2638*4882a593Smuzhiyun 	default:
2639*4882a593Smuzhiyun 		DP_NOTICE(edev, "Unexpected HW error [%d]\n", err_type);
2640*4882a593Smuzhiyun 		break;
2641*4882a593Smuzhiyun 	}
2642*4882a593Smuzhiyun 
2643*4882a593Smuzhiyun 	edev->err_flags |= err_flags;
2644*4882a593Smuzhiyun }
2645*4882a593Smuzhiyun 
qede_schedule_hw_err_handler(void * dev,enum qed_hw_err_type err_type)2646*4882a593Smuzhiyun static void qede_schedule_hw_err_handler(void *dev,
2647*4882a593Smuzhiyun 					 enum qed_hw_err_type err_type)
2648*4882a593Smuzhiyun {
2649*4882a593Smuzhiyun 	struct qede_dev *edev = dev;
2650*4882a593Smuzhiyun 
2651*4882a593Smuzhiyun 	/* Fan failure cannot be masked by handling of another HW error or by a
2652*4882a593Smuzhiyun 	 * concurrent recovery process.
2653*4882a593Smuzhiyun 	 */
2654*4882a593Smuzhiyun 	if ((test_and_set_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags) ||
2655*4882a593Smuzhiyun 	     edev->state == QEDE_STATE_RECOVERY) &&
2656*4882a593Smuzhiyun 	     err_type != QED_HW_ERR_FAN_FAIL) {
2657*4882a593Smuzhiyun 		DP_INFO(edev,
2658*4882a593Smuzhiyun 			"Avoid scheduling an error handling while another HW error is being handled\n");
2659*4882a593Smuzhiyun 		return;
2660*4882a593Smuzhiyun 	}
2661*4882a593Smuzhiyun 
2662*4882a593Smuzhiyun 	if (err_type >= QED_HW_ERR_LAST) {
2663*4882a593Smuzhiyun 		DP_NOTICE(edev, "Unknown HW error [%d]\n", err_type);
2664*4882a593Smuzhiyun 		clear_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags);
2665*4882a593Smuzhiyun 		return;
2666*4882a593Smuzhiyun 	}
2667*4882a593Smuzhiyun 
2668*4882a593Smuzhiyun 	edev->last_err_type = err_type;
2669*4882a593Smuzhiyun 	qede_set_hw_err_flags(edev, err_type);
2670*4882a593Smuzhiyun 	qede_atomic_hw_err_handler(edev);
2671*4882a593Smuzhiyun 	set_bit(QEDE_SP_HW_ERR, &edev->sp_flags);
2672*4882a593Smuzhiyun 	schedule_delayed_work(&edev->sp_task, 0);
2673*4882a593Smuzhiyun 
2674*4882a593Smuzhiyun 	DP_INFO(edev, "Scheduled a error handler [err_type %d]\n", err_type);
2675*4882a593Smuzhiyun }
2676*4882a593Smuzhiyun 
qede_is_txq_full(struct qede_dev * edev,struct qede_tx_queue * txq)2677*4882a593Smuzhiyun static bool qede_is_txq_full(struct qede_dev *edev, struct qede_tx_queue *txq)
2678*4882a593Smuzhiyun {
2679*4882a593Smuzhiyun 	struct netdev_queue *netdev_txq;
2680*4882a593Smuzhiyun 
2681*4882a593Smuzhiyun 	netdev_txq = netdev_get_tx_queue(edev->ndev, txq->ndev_txq_id);
2682*4882a593Smuzhiyun 	if (netif_xmit_stopped(netdev_txq))
2683*4882a593Smuzhiyun 		return true;
2684*4882a593Smuzhiyun 
2685*4882a593Smuzhiyun 	return false;
2686*4882a593Smuzhiyun }
2687*4882a593Smuzhiyun 
qede_get_generic_tlv_data(void * dev,struct qed_generic_tlvs * data)2688*4882a593Smuzhiyun static void qede_get_generic_tlv_data(void *dev, struct qed_generic_tlvs *data)
2689*4882a593Smuzhiyun {
2690*4882a593Smuzhiyun 	struct qede_dev *edev = dev;
2691*4882a593Smuzhiyun 	struct netdev_hw_addr *ha;
2692*4882a593Smuzhiyun 	int i;
2693*4882a593Smuzhiyun 
2694*4882a593Smuzhiyun 	if (edev->ndev->features & NETIF_F_IP_CSUM)
2695*4882a593Smuzhiyun 		data->feat_flags |= QED_TLV_IP_CSUM;
2696*4882a593Smuzhiyun 	if (edev->ndev->features & NETIF_F_TSO)
2697*4882a593Smuzhiyun 		data->feat_flags |= QED_TLV_LSO;
2698*4882a593Smuzhiyun 
2699*4882a593Smuzhiyun 	ether_addr_copy(data->mac[0], edev->ndev->dev_addr);
2700*4882a593Smuzhiyun 	eth_zero_addr(data->mac[1]);
2701*4882a593Smuzhiyun 	eth_zero_addr(data->mac[2]);
2702*4882a593Smuzhiyun 	/* Copy the first two UC macs */
2703*4882a593Smuzhiyun 	netif_addr_lock_bh(edev->ndev);
2704*4882a593Smuzhiyun 	i = 1;
2705*4882a593Smuzhiyun 	netdev_for_each_uc_addr(ha, edev->ndev) {
2706*4882a593Smuzhiyun 		ether_addr_copy(data->mac[i++], ha->addr);
2707*4882a593Smuzhiyun 		if (i == QED_TLV_MAC_COUNT)
2708*4882a593Smuzhiyun 			break;
2709*4882a593Smuzhiyun 	}
2710*4882a593Smuzhiyun 
2711*4882a593Smuzhiyun 	netif_addr_unlock_bh(edev->ndev);
2712*4882a593Smuzhiyun }
2713*4882a593Smuzhiyun 
qede_get_eth_tlv_data(void * dev,void * data)2714*4882a593Smuzhiyun static void qede_get_eth_tlv_data(void *dev, void *data)
2715*4882a593Smuzhiyun {
2716*4882a593Smuzhiyun 	struct qed_mfw_tlv_eth *etlv = data;
2717*4882a593Smuzhiyun 	struct qede_dev *edev = dev;
2718*4882a593Smuzhiyun 	struct qede_fastpath *fp;
2719*4882a593Smuzhiyun 	int i;
2720*4882a593Smuzhiyun 
2721*4882a593Smuzhiyun 	etlv->lso_maxoff_size = 0XFFFF;
2722*4882a593Smuzhiyun 	etlv->lso_maxoff_size_set = true;
2723*4882a593Smuzhiyun 	etlv->lso_minseg_size = (u16)ETH_TX_LSO_WINDOW_MIN_LEN;
2724*4882a593Smuzhiyun 	etlv->lso_minseg_size_set = true;
2725*4882a593Smuzhiyun 	etlv->prom_mode = !!(edev->ndev->flags & IFF_PROMISC);
2726*4882a593Smuzhiyun 	etlv->prom_mode_set = true;
2727*4882a593Smuzhiyun 	etlv->tx_descr_size = QEDE_TSS_COUNT(edev);
2728*4882a593Smuzhiyun 	etlv->tx_descr_size_set = true;
2729*4882a593Smuzhiyun 	etlv->rx_descr_size = QEDE_RSS_COUNT(edev);
2730*4882a593Smuzhiyun 	etlv->rx_descr_size_set = true;
2731*4882a593Smuzhiyun 	etlv->iov_offload = QED_MFW_TLV_IOV_OFFLOAD_VEB;
2732*4882a593Smuzhiyun 	etlv->iov_offload_set = true;
2733*4882a593Smuzhiyun 
2734*4882a593Smuzhiyun 	/* Fill information regarding queues; Should be done under the qede
2735*4882a593Smuzhiyun 	 * lock to guarantee those don't change beneath our feet.
2736*4882a593Smuzhiyun 	 */
2737*4882a593Smuzhiyun 	etlv->txqs_empty = true;
2738*4882a593Smuzhiyun 	etlv->rxqs_empty = true;
2739*4882a593Smuzhiyun 	etlv->num_txqs_full = 0;
2740*4882a593Smuzhiyun 	etlv->num_rxqs_full = 0;
2741*4882a593Smuzhiyun 
2742*4882a593Smuzhiyun 	__qede_lock(edev);
2743*4882a593Smuzhiyun 	for_each_queue(i) {
2744*4882a593Smuzhiyun 		fp = &edev->fp_array[i];
2745*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_TX) {
2746*4882a593Smuzhiyun 			struct qede_tx_queue *txq = QEDE_FP_TC0_TXQ(fp);
2747*4882a593Smuzhiyun 
2748*4882a593Smuzhiyun 			if (txq->sw_tx_cons != txq->sw_tx_prod)
2749*4882a593Smuzhiyun 				etlv->txqs_empty = false;
2750*4882a593Smuzhiyun 			if (qede_is_txq_full(edev, txq))
2751*4882a593Smuzhiyun 				etlv->num_txqs_full++;
2752*4882a593Smuzhiyun 		}
2753*4882a593Smuzhiyun 		if (fp->type & QEDE_FASTPATH_RX) {
2754*4882a593Smuzhiyun 			if (qede_has_rx_work(fp->rxq))
2755*4882a593Smuzhiyun 				etlv->rxqs_empty = false;
2756*4882a593Smuzhiyun 
2757*4882a593Smuzhiyun 			/* This one is a bit tricky; Firmware might stop
2758*4882a593Smuzhiyun 			 * placing packets if ring is not yet full.
2759*4882a593Smuzhiyun 			 * Give an approximation.
2760*4882a593Smuzhiyun 			 */
2761*4882a593Smuzhiyun 			if (le16_to_cpu(*fp->rxq->hw_cons_ptr) -
2762*4882a593Smuzhiyun 			    qed_chain_get_cons_idx(&fp->rxq->rx_comp_ring) >
2763*4882a593Smuzhiyun 			    RX_RING_SIZE - 100)
2764*4882a593Smuzhiyun 				etlv->num_rxqs_full++;
2765*4882a593Smuzhiyun 		}
2766*4882a593Smuzhiyun 	}
2767*4882a593Smuzhiyun 	__qede_unlock(edev);
2768*4882a593Smuzhiyun 
2769*4882a593Smuzhiyun 	etlv->txqs_empty_set = true;
2770*4882a593Smuzhiyun 	etlv->rxqs_empty_set = true;
2771*4882a593Smuzhiyun 	etlv->num_txqs_full_set = true;
2772*4882a593Smuzhiyun 	etlv->num_rxqs_full_set = true;
2773*4882a593Smuzhiyun }
2774*4882a593Smuzhiyun 
2775*4882a593Smuzhiyun /**
2776*4882a593Smuzhiyun  * qede_io_error_detected - called when PCI error is detected
2777*4882a593Smuzhiyun  * @pdev: Pointer to PCI device
2778*4882a593Smuzhiyun  * @state: The current pci connection state
2779*4882a593Smuzhiyun  *
2780*4882a593Smuzhiyun  * This function is called after a PCI bus error affecting
2781*4882a593Smuzhiyun  * this device has been detected.
2782*4882a593Smuzhiyun  */
2783*4882a593Smuzhiyun static pci_ers_result_t
qede_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)2784*4882a593Smuzhiyun qede_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2785*4882a593Smuzhiyun {
2786*4882a593Smuzhiyun 	struct net_device *dev = pci_get_drvdata(pdev);
2787*4882a593Smuzhiyun 	struct qede_dev *edev = netdev_priv(dev);
2788*4882a593Smuzhiyun 
2789*4882a593Smuzhiyun 	if (!edev)
2790*4882a593Smuzhiyun 		return PCI_ERS_RESULT_NONE;
2791*4882a593Smuzhiyun 
2792*4882a593Smuzhiyun 	DP_NOTICE(edev, "IO error detected [%d]\n", state);
2793*4882a593Smuzhiyun 
2794*4882a593Smuzhiyun 	__qede_lock(edev);
2795*4882a593Smuzhiyun 	if (edev->state == QEDE_STATE_RECOVERY) {
2796*4882a593Smuzhiyun 		DP_NOTICE(edev, "Device already in the recovery state\n");
2797*4882a593Smuzhiyun 		__qede_unlock(edev);
2798*4882a593Smuzhiyun 		return PCI_ERS_RESULT_NONE;
2799*4882a593Smuzhiyun 	}
2800*4882a593Smuzhiyun 
2801*4882a593Smuzhiyun 	/* PF handles the recovery of its VFs */
2802*4882a593Smuzhiyun 	if (IS_VF(edev)) {
2803*4882a593Smuzhiyun 		DP_VERBOSE(edev, QED_MSG_IOV,
2804*4882a593Smuzhiyun 			   "VF recovery is handled by its PF\n");
2805*4882a593Smuzhiyun 		__qede_unlock(edev);
2806*4882a593Smuzhiyun 		return PCI_ERS_RESULT_RECOVERED;
2807*4882a593Smuzhiyun 	}
2808*4882a593Smuzhiyun 
2809*4882a593Smuzhiyun 	/* Close OS Tx */
2810*4882a593Smuzhiyun 	netif_tx_disable(edev->ndev);
2811*4882a593Smuzhiyun 	netif_carrier_off(edev->ndev);
2812*4882a593Smuzhiyun 
2813*4882a593Smuzhiyun 	set_bit(QEDE_SP_AER, &edev->sp_flags);
2814*4882a593Smuzhiyun 	schedule_delayed_work(&edev->sp_task, 0);
2815*4882a593Smuzhiyun 
2816*4882a593Smuzhiyun 	__qede_unlock(edev);
2817*4882a593Smuzhiyun 
2818*4882a593Smuzhiyun 	return PCI_ERS_RESULT_CAN_RECOVER;
2819*4882a593Smuzhiyun }
2820