1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #ifndef _IONIC_DEV_H_
5*4882a593Smuzhiyun #define _IONIC_DEV_H_
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/mutex.h>
8*4882a593Smuzhiyun #include <linux/workqueue.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "ionic_if.h"
11*4882a593Smuzhiyun #include "ionic_regs.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define IONIC_MAX_TX_DESC 8192
14*4882a593Smuzhiyun #define IONIC_MAX_RX_DESC 16384
15*4882a593Smuzhiyun #define IONIC_MIN_TXRX_DESC 16
16*4882a593Smuzhiyun #define IONIC_DEF_TXRX_DESC 4096
17*4882a593Smuzhiyun #define IONIC_LIFS_MAX 1024
18*4882a593Smuzhiyun #define IONIC_WATCHDOG_SECS 5
19*4882a593Smuzhiyun #define IONIC_ITR_COAL_USEC_DEFAULT 64
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define IONIC_DEV_CMD_REG_VERSION 1
22*4882a593Smuzhiyun #define IONIC_DEV_INFO_REG_COUNT 32
23*4882a593Smuzhiyun #define IONIC_DEV_CMD_REG_COUNT 32
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun struct ionic_dev_bar {
26*4882a593Smuzhiyun void __iomem *vaddr;
27*4882a593Smuzhiyun phys_addr_t bus_addr;
28*4882a593Smuzhiyun unsigned long len;
29*4882a593Smuzhiyun int res_index;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #ifndef __CHECKER__
33*4882a593Smuzhiyun /* Registers */
34*4882a593Smuzhiyun static_assert(sizeof(struct ionic_intr) == 32);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static_assert(sizeof(struct ionic_doorbell) == 8);
37*4882a593Smuzhiyun static_assert(sizeof(struct ionic_intr_status) == 8);
38*4882a593Smuzhiyun static_assert(sizeof(union ionic_dev_regs) == 4096);
39*4882a593Smuzhiyun static_assert(sizeof(union ionic_dev_info_regs) == 2048);
40*4882a593Smuzhiyun static_assert(sizeof(union ionic_dev_cmd_regs) == 2048);
41*4882a593Smuzhiyun static_assert(sizeof(struct ionic_lif_stats) == 1024);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static_assert(sizeof(struct ionic_admin_cmd) == 64);
44*4882a593Smuzhiyun static_assert(sizeof(struct ionic_admin_comp) == 16);
45*4882a593Smuzhiyun static_assert(sizeof(struct ionic_nop_cmd) == 64);
46*4882a593Smuzhiyun static_assert(sizeof(struct ionic_nop_comp) == 16);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Device commands */
49*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_identify_cmd) == 64);
50*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_identify_comp) == 16);
51*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_init_cmd) == 64);
52*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_init_comp) == 16);
53*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_reset_cmd) == 64);
54*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_reset_comp) == 16);
55*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64);
56*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_getattr_comp) == 16);
57*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64);
58*4882a593Smuzhiyun static_assert(sizeof(struct ionic_dev_setattr_comp) == 16);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Port commands */
61*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_identify_cmd) == 64);
62*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_identify_comp) == 16);
63*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_init_cmd) == 64);
64*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_init_comp) == 16);
65*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_reset_cmd) == 64);
66*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_reset_comp) == 16);
67*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_getattr_cmd) == 64);
68*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_getattr_comp) == 16);
69*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_setattr_cmd) == 64);
70*4882a593Smuzhiyun static_assert(sizeof(struct ionic_port_setattr_comp) == 16);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* LIF commands */
73*4882a593Smuzhiyun static_assert(sizeof(struct ionic_lif_init_cmd) == 64);
74*4882a593Smuzhiyun static_assert(sizeof(struct ionic_lif_init_comp) == 16);
75*4882a593Smuzhiyun static_assert(sizeof(struct ionic_lif_reset_cmd) == 64);
76*4882a593Smuzhiyun static_assert(sizeof(ionic_lif_reset_comp) == 16);
77*4882a593Smuzhiyun static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64);
78*4882a593Smuzhiyun static_assert(sizeof(struct ionic_lif_getattr_comp) == 16);
79*4882a593Smuzhiyun static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64);
80*4882a593Smuzhiyun static_assert(sizeof(struct ionic_lif_setattr_comp) == 16);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static_assert(sizeof(struct ionic_q_init_cmd) == 64);
83*4882a593Smuzhiyun static_assert(sizeof(struct ionic_q_init_comp) == 16);
84*4882a593Smuzhiyun static_assert(sizeof(struct ionic_q_control_cmd) == 64);
85*4882a593Smuzhiyun static_assert(sizeof(ionic_q_control_comp) == 16);
86*4882a593Smuzhiyun static_assert(sizeof(struct ionic_q_identify_cmd) == 64);
87*4882a593Smuzhiyun static_assert(sizeof(struct ionic_q_identify_comp) == 16);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64);
90*4882a593Smuzhiyun static_assert(sizeof(ionic_rx_mode_set_comp) == 16);
91*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64);
92*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16);
93*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64);
94*4882a593Smuzhiyun static_assert(sizeof(ionic_rx_filter_del_comp) == 16);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* RDMA commands */
97*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64);
98*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Events */
101*4882a593Smuzhiyun static_assert(sizeof(struct ionic_notifyq_cmd) == 4);
102*4882a593Smuzhiyun static_assert(sizeof(union ionic_notifyq_comp) == 64);
103*4882a593Smuzhiyun static_assert(sizeof(struct ionic_notifyq_event) == 64);
104*4882a593Smuzhiyun static_assert(sizeof(struct ionic_link_change_event) == 64);
105*4882a593Smuzhiyun static_assert(sizeof(struct ionic_reset_event) == 64);
106*4882a593Smuzhiyun static_assert(sizeof(struct ionic_heartbeat_event) == 64);
107*4882a593Smuzhiyun static_assert(sizeof(struct ionic_log_event) == 64);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* I/O */
110*4882a593Smuzhiyun static_assert(sizeof(struct ionic_txq_desc) == 16);
111*4882a593Smuzhiyun static_assert(sizeof(struct ionic_txq_sg_desc) == 128);
112*4882a593Smuzhiyun static_assert(sizeof(struct ionic_txq_comp) == 16);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rxq_desc) == 16);
115*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rxq_sg_desc) == 128);
116*4882a593Smuzhiyun static_assert(sizeof(struct ionic_rxq_comp) == 16);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* SR/IOV */
119*4882a593Smuzhiyun static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64);
120*4882a593Smuzhiyun static_assert(sizeof(struct ionic_vf_setattr_comp) == 16);
121*4882a593Smuzhiyun static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64);
122*4882a593Smuzhiyun static_assert(sizeof(struct ionic_vf_getattr_comp) == 16);
123*4882a593Smuzhiyun #endif /* __CHECKER__ */
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun struct ionic_devinfo {
126*4882a593Smuzhiyun u8 asic_type;
127*4882a593Smuzhiyun u8 asic_rev;
128*4882a593Smuzhiyun char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
129*4882a593Smuzhiyun char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun struct ionic_dev {
133*4882a593Smuzhiyun union ionic_dev_info_regs __iomem *dev_info_regs;
134*4882a593Smuzhiyun union ionic_dev_cmd_regs __iomem *dev_cmd_regs;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun unsigned long last_hb_time;
137*4882a593Smuzhiyun u32 last_hb;
138*4882a593Smuzhiyun u8 last_fw_status;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun u64 __iomem *db_pages;
141*4882a593Smuzhiyun dma_addr_t phy_db_pages;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun struct ionic_intr __iomem *intr_ctrl;
144*4882a593Smuzhiyun u64 __iomem *intr_status;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun u32 port_info_sz;
147*4882a593Smuzhiyun struct ionic_port_info *port_info;
148*4882a593Smuzhiyun dma_addr_t port_info_pa;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun struct ionic_devinfo dev_info;
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun struct ionic_cq_info {
154*4882a593Smuzhiyun union {
155*4882a593Smuzhiyun void *cq_desc;
156*4882a593Smuzhiyun struct ionic_txq_comp *txcq;
157*4882a593Smuzhiyun struct ionic_rxq_comp *rxcq;
158*4882a593Smuzhiyun struct ionic_admin_comp *admincq;
159*4882a593Smuzhiyun struct ionic_notifyq_event *notifyq;
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun struct ionic_queue;
164*4882a593Smuzhiyun struct ionic_qcq;
165*4882a593Smuzhiyun struct ionic_desc_info;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun typedef void (*ionic_desc_cb)(struct ionic_queue *q,
168*4882a593Smuzhiyun struct ionic_desc_info *desc_info,
169*4882a593Smuzhiyun struct ionic_cq_info *cq_info, void *cb_arg);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun struct ionic_page_info {
172*4882a593Smuzhiyun struct page *page;
173*4882a593Smuzhiyun dma_addr_t dma_addr;
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun struct ionic_desc_info {
177*4882a593Smuzhiyun union {
178*4882a593Smuzhiyun void *desc;
179*4882a593Smuzhiyun struct ionic_txq_desc *txq_desc;
180*4882a593Smuzhiyun struct ionic_rxq_desc *rxq_desc;
181*4882a593Smuzhiyun struct ionic_admin_cmd *adminq_desc;
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun union {
184*4882a593Smuzhiyun void *sg_desc;
185*4882a593Smuzhiyun struct ionic_txq_sg_desc *txq_sg_desc;
186*4882a593Smuzhiyun struct ionic_rxq_sg_desc *rxq_sgl_desc;
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun unsigned int npages;
189*4882a593Smuzhiyun struct ionic_page_info pages[IONIC_RX_MAX_SG_ELEMS + 1];
190*4882a593Smuzhiyun ionic_desc_cb cb;
191*4882a593Smuzhiyun void *cb_arg;
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun #define IONIC_QUEUE_NAME_MAX_SZ 32
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun struct ionic_queue {
197*4882a593Smuzhiyun struct device *dev;
198*4882a593Smuzhiyun struct ionic_lif *lif;
199*4882a593Smuzhiyun struct ionic_desc_info *info;
200*4882a593Smuzhiyun u16 head_idx;
201*4882a593Smuzhiyun u16 tail_idx;
202*4882a593Smuzhiyun unsigned int index;
203*4882a593Smuzhiyun unsigned int num_descs;
204*4882a593Smuzhiyun u64 dbell_count;
205*4882a593Smuzhiyun u64 stop;
206*4882a593Smuzhiyun u64 wake;
207*4882a593Smuzhiyun u64 drop;
208*4882a593Smuzhiyun struct ionic_dev *idev;
209*4882a593Smuzhiyun unsigned int type;
210*4882a593Smuzhiyun unsigned int hw_index;
211*4882a593Smuzhiyun unsigned int hw_type;
212*4882a593Smuzhiyun u64 dbval;
213*4882a593Smuzhiyun union {
214*4882a593Smuzhiyun void *base;
215*4882a593Smuzhiyun struct ionic_txq_desc *txq;
216*4882a593Smuzhiyun struct ionic_rxq_desc *rxq;
217*4882a593Smuzhiyun struct ionic_admin_cmd *adminq;
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun union {
220*4882a593Smuzhiyun void *sg_base;
221*4882a593Smuzhiyun struct ionic_txq_sg_desc *txq_sgl;
222*4882a593Smuzhiyun struct ionic_rxq_sg_desc *rxq_sgl;
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun dma_addr_t base_pa;
225*4882a593Smuzhiyun dma_addr_t sg_base_pa;
226*4882a593Smuzhiyun unsigned int desc_size;
227*4882a593Smuzhiyun unsigned int sg_desc_size;
228*4882a593Smuzhiyun unsigned int pid;
229*4882a593Smuzhiyun char name[IONIC_QUEUE_NAME_MAX_SZ];
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun #define IONIC_INTR_INDEX_NOT_ASSIGNED -1
233*4882a593Smuzhiyun #define IONIC_INTR_NAME_MAX_SZ 32
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun struct ionic_intr_info {
236*4882a593Smuzhiyun char name[IONIC_INTR_NAME_MAX_SZ];
237*4882a593Smuzhiyun unsigned int index;
238*4882a593Smuzhiyun unsigned int vector;
239*4882a593Smuzhiyun u64 rearm_count;
240*4882a593Smuzhiyun unsigned int cpu;
241*4882a593Smuzhiyun cpumask_t affinity_mask;
242*4882a593Smuzhiyun u32 dim_coal_hw;
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun struct ionic_cq {
246*4882a593Smuzhiyun struct ionic_lif *lif;
247*4882a593Smuzhiyun struct ionic_cq_info *info;
248*4882a593Smuzhiyun struct ionic_queue *bound_q;
249*4882a593Smuzhiyun struct ionic_intr_info *bound_intr;
250*4882a593Smuzhiyun u16 tail_idx;
251*4882a593Smuzhiyun bool done_color;
252*4882a593Smuzhiyun unsigned int num_descs;
253*4882a593Smuzhiyun unsigned int desc_size;
254*4882a593Smuzhiyun u64 compl_count;
255*4882a593Smuzhiyun void *base;
256*4882a593Smuzhiyun dma_addr_t base_pa;
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun struct ionic;
260*4882a593Smuzhiyun
ionic_intr_init(struct ionic_dev * idev,struct ionic_intr_info * intr,unsigned long index)261*4882a593Smuzhiyun static inline void ionic_intr_init(struct ionic_dev *idev,
262*4882a593Smuzhiyun struct ionic_intr_info *intr,
263*4882a593Smuzhiyun unsigned long index)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun ionic_intr_clean(idev->intr_ctrl, index);
266*4882a593Smuzhiyun intr->index = index;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
ionic_q_space_avail(struct ionic_queue * q)269*4882a593Smuzhiyun static inline unsigned int ionic_q_space_avail(struct ionic_queue *q)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun unsigned int avail = q->tail_idx;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun if (q->head_idx >= avail)
274*4882a593Smuzhiyun avail += q->num_descs - q->head_idx - 1;
275*4882a593Smuzhiyun else
276*4882a593Smuzhiyun avail -= q->head_idx + 1;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun return avail;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
ionic_q_has_space(struct ionic_queue * q,unsigned int want)281*4882a593Smuzhiyun static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun return ionic_q_space_avail(q) >= want;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun void ionic_init_devinfo(struct ionic *ionic);
287*4882a593Smuzhiyun int ionic_dev_setup(struct ionic *ionic);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
290*4882a593Smuzhiyun u8 ionic_dev_cmd_status(struct ionic_dev *idev);
291*4882a593Smuzhiyun bool ionic_dev_cmd_done(struct ionic_dev *idev);
292*4882a593Smuzhiyun void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
295*4882a593Smuzhiyun void ionic_dev_cmd_init(struct ionic_dev *idev);
296*4882a593Smuzhiyun void ionic_dev_cmd_reset(struct ionic_dev *idev);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun void ionic_dev_cmd_port_identify(struct ionic_dev *idev);
299*4882a593Smuzhiyun void ionic_dev_cmd_port_init(struct ionic_dev *idev);
300*4882a593Smuzhiyun void ionic_dev_cmd_port_reset(struct ionic_dev *idev);
301*4882a593Smuzhiyun void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state);
302*4882a593Smuzhiyun void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed);
303*4882a593Smuzhiyun void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable);
304*4882a593Smuzhiyun void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type);
305*4882a593Smuzhiyun void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data);
308*4882a593Smuzhiyun void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
309*4882a593Smuzhiyun u16 lif_type, u8 qtype, u8 qver);
310*4882a593Smuzhiyun void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver);
311*4882a593Smuzhiyun void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
312*4882a593Smuzhiyun dma_addr_t addr);
313*4882a593Smuzhiyun void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
314*4882a593Smuzhiyun void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,
315*4882a593Smuzhiyun u16 lif_index, u16 intr_index);
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun int ionic_db_page_num(struct ionic_lif *lif, int pid);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
320*4882a593Smuzhiyun struct ionic_intr_info *intr,
321*4882a593Smuzhiyun unsigned int num_descs, size_t desc_size);
322*4882a593Smuzhiyun void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa);
323*4882a593Smuzhiyun void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q);
324*4882a593Smuzhiyun typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, struct ionic_cq_info *cq_info);
325*4882a593Smuzhiyun typedef void (*ionic_cq_done_cb)(void *done_arg);
326*4882a593Smuzhiyun unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
327*4882a593Smuzhiyun ionic_cq_cb cb, ionic_cq_done_cb done_cb,
328*4882a593Smuzhiyun void *done_arg);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
331*4882a593Smuzhiyun struct ionic_queue *q, unsigned int index, const char *name,
332*4882a593Smuzhiyun unsigned int num_descs, size_t desc_size,
333*4882a593Smuzhiyun size_t sg_desc_size, unsigned int pid);
334*4882a593Smuzhiyun void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa);
335*4882a593Smuzhiyun void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa);
336*4882a593Smuzhiyun void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb,
337*4882a593Smuzhiyun void *cb_arg);
338*4882a593Smuzhiyun void ionic_q_rewind(struct ionic_queue *q, struct ionic_desc_info *start);
339*4882a593Smuzhiyun void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info,
340*4882a593Smuzhiyun unsigned int stop_index);
341*4882a593Smuzhiyun int ionic_heartbeat_check(struct ionic *ionic);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun #endif /* _IONIC_DEV_H_ */
344