1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _IONIC_H_ 5*4882a593Smuzhiyun #define _IONIC_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct ionic_lif; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "ionic_if.h" 10*4882a593Smuzhiyun #include "ionic_dev.h" 11*4882a593Smuzhiyun #include "ionic_devlink.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define IONIC_DRV_NAME "ionic" 14*4882a593Smuzhiyun #define IONIC_DRV_DESCRIPTION "Pensando Ethernet NIC Driver" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define PCI_VENDOR_ID_PENSANDO 0x1dd8 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define PCI_DEVICE_ID_PENSANDO_IONIC_ETH_PF 0x1002 19*4882a593Smuzhiyun #define PCI_DEVICE_ID_PENSANDO_IONIC_ETH_VF 0x1003 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define DEVCMD_TIMEOUT 10 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct ionic_vf { 24*4882a593Smuzhiyun u16 index; 25*4882a593Smuzhiyun u8 macaddr[6]; 26*4882a593Smuzhiyun __le32 maxrate; 27*4882a593Smuzhiyun __le16 vlanid; 28*4882a593Smuzhiyun u8 spoofchk; 29*4882a593Smuzhiyun u8 trusted; 30*4882a593Smuzhiyun u8 linkstate; 31*4882a593Smuzhiyun dma_addr_t stats_pa; 32*4882a593Smuzhiyun struct ionic_lif_stats stats; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct ionic { 36*4882a593Smuzhiyun struct pci_dev *pdev; 37*4882a593Smuzhiyun struct device *dev; 38*4882a593Smuzhiyun struct devlink_port dl_port; 39*4882a593Smuzhiyun struct ionic_dev idev; 40*4882a593Smuzhiyun struct mutex dev_cmd_lock; /* lock for dev_cmd operations */ 41*4882a593Smuzhiyun struct dentry *dentry; 42*4882a593Smuzhiyun struct ionic_dev_bar bars[IONIC_BARS_MAX]; 43*4882a593Smuzhiyun unsigned int num_bars; 44*4882a593Smuzhiyun struct ionic_identity ident; 45*4882a593Smuzhiyun struct ionic_lif *lif; 46*4882a593Smuzhiyun unsigned int nnqs_per_lif; 47*4882a593Smuzhiyun unsigned int neqs_per_lif; 48*4882a593Smuzhiyun unsigned int ntxqs_per_lif; 49*4882a593Smuzhiyun unsigned int nrxqs_per_lif; 50*4882a593Smuzhiyun unsigned int nintrs; 51*4882a593Smuzhiyun DECLARE_BITMAP(intrs, IONIC_INTR_CTRL_REGS_MAX); 52*4882a593Smuzhiyun struct work_struct nb_work; 53*4882a593Smuzhiyun struct notifier_block nb; 54*4882a593Smuzhiyun struct rw_semaphore vf_op_lock; /* lock for VF operations */ 55*4882a593Smuzhiyun struct ionic_vf *vfs; 56*4882a593Smuzhiyun int num_vfs; 57*4882a593Smuzhiyun struct timer_list watchdog_timer; 58*4882a593Smuzhiyun int watchdog_period; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct ionic_admin_ctx { 62*4882a593Smuzhiyun struct completion work; 63*4882a593Smuzhiyun union ionic_adminq_cmd cmd; 64*4882a593Smuzhiyun union ionic_adminq_comp comp; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx); 68*4882a593Smuzhiyun int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_wait); 69*4882a593Smuzhiyun int ionic_set_dma_mask(struct ionic *ionic); 70*4882a593Smuzhiyun int ionic_setup(struct ionic *ionic); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun int ionic_identify(struct ionic *ionic); 73*4882a593Smuzhiyun int ionic_init(struct ionic *ionic); 74*4882a593Smuzhiyun int ionic_reset(struct ionic *ionic); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun int ionic_port_identify(struct ionic *ionic); 77*4882a593Smuzhiyun int ionic_port_init(struct ionic *ionic); 78*4882a593Smuzhiyun int ionic_port_reset(struct ionic *ionic); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #endif /* _IONIC_H_ */ 81