1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Microsemi Ocelot Switch driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017 Microsemi Corporation 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _MSCC_OCELOT_REW_H_ 9*4882a593Smuzhiyun #define _MSCC_OCELOT_REW_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_GSZ 0x80 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16)) 14*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_TPID_M GENMASK(31, 16) 15*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16) 16*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_DEI BIT(15) 17*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12)) 18*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_PCP_M GENMASK(14, 12) 19*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12) 20*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0)) 21*4882a593Smuzhiyun #define REW_PORT_VLAN_CFG_PORT_VID_M GENMASK(11, 0) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define REW_TAG_CFG_GSZ 0x80 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7)) 26*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_CFG_M GENMASK(8, 7) 27*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_CFG_X(x) (((x) & GENMASK(8, 7)) >> 7) 28*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_TPID_CFG(x) (((x) << 5) & GENMASK(6, 5)) 29*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_TPID_CFG_M GENMASK(6, 5) 30*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_TPID_CFG_X(x) (((x) & GENMASK(6, 5)) >> 5) 31*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_VID_CFG BIT(4) 32*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_PCP_CFG(x) (((x) << 2) & GENMASK(3, 2)) 33*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_PCP_CFG_M GENMASK(3, 2) 34*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_PCP_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2) 35*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_DEI_CFG(x) ((x) & GENMASK(1, 0)) 36*4882a593Smuzhiyun #define REW_TAG_CFG_TAG_DEI_CFG_M GENMASK(1, 0) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define REW_PORT_CFG_GSZ 0x80 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define REW_PORT_CFG_ES0_EN BIT(5) 41*4882a593Smuzhiyun #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG(x) (((x) << 3) & GENMASK(4, 3)) 42*4882a593Smuzhiyun #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_M GENMASK(4, 3) 43*4882a593Smuzhiyun #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_X(x) (((x) & GENMASK(4, 3)) >> 3) 44*4882a593Smuzhiyun #define REW_PORT_CFG_FCS_UPDATE_CPU_ENA BIT(2) 45*4882a593Smuzhiyun #define REW_PORT_CFG_FLUSH_ENA BIT(1) 46*4882a593Smuzhiyun #define REW_PORT_CFG_AGE_DIS BIT(0) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define REW_DSCP_CFG_GSZ 0x80 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define REW_PCP_DEI_QOS_MAP_CFG_GSZ 0x80 51*4882a593Smuzhiyun #define REW_PCP_DEI_QOS_MAP_CFG_RSZ 0x4 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define REW_PCP_DEI_QOS_MAP_CFG_DEI_QOS_VAL BIT(3) 54*4882a593Smuzhiyun #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL(x) ((x) & GENMASK(2, 0)) 55*4882a593Smuzhiyun #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL_M GENMASK(2, 0) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define REW_PTP_CFG_GSZ 0x80 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define REW_PTP_CFG_PTP_BACKPLANE_MODE BIT(7) 60*4882a593Smuzhiyun #define REW_PTP_CFG_GP_CFG_UNUSED(x) (((x) << 3) & GENMASK(6, 3)) 61*4882a593Smuzhiyun #define REW_PTP_CFG_GP_CFG_UNUSED_M GENMASK(6, 3) 62*4882a593Smuzhiyun #define REW_PTP_CFG_GP_CFG_UNUSED_X(x) (((x) & GENMASK(6, 3)) >> 3) 63*4882a593Smuzhiyun #define REW_PTP_CFG_PTP_1STEP_DIS BIT(2) 64*4882a593Smuzhiyun #define REW_PTP_CFG_PTP_2STEP_DIS BIT(1) 65*4882a593Smuzhiyun #define REW_PTP_CFG_PTP_UDP_KEEP BIT(0) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define REW_PTP_DLY1_CFG_GSZ 0x80 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define REW_RED_TAG_CFG_GSZ 0x80 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define REW_RED_TAG_CFG_RED_TAG_CFG BIT(0) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define REW_DSCP_REMAP_DP1_CFG_RSZ 0x4 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define REW_DSCP_REMAP_CFG_RSZ 0x4 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define REW_REW_STICKY_ES0_TAGB_PUSH_FAILED BIT(0) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define REW_PPT_RSZ 0x4 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif 82