1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Microsemi Ocelot Switch driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017 Microsemi Corporation 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _MSCC_OCELOT_QS_H_ 9*4882a593Smuzhiyun #define _MSCC_OCELOT_QS_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* TODO handle BE */ 12*4882a593Smuzhiyun #define XTR_EOF_0 0x00000080U 13*4882a593Smuzhiyun #define XTR_EOF_1 0x01000080U 14*4882a593Smuzhiyun #define XTR_EOF_2 0x02000080U 15*4882a593Smuzhiyun #define XTR_EOF_3 0x03000080U 16*4882a593Smuzhiyun #define XTR_PRUNED 0x04000080U 17*4882a593Smuzhiyun #define XTR_ABORT 0x05000080U 18*4882a593Smuzhiyun #define XTR_ESCAPE 0x06000080U 19*4882a593Smuzhiyun #define XTR_NOT_READY 0x07000080U 20*4882a593Smuzhiyun #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3)) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define QS_XTR_GRP_CFG_RSZ 0x4 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) 25*4882a593Smuzhiyun #define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2) 26*4882a593Smuzhiyun #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) 27*4882a593Smuzhiyun #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) 28*4882a593Smuzhiyun #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define QS_XTR_RD_RSZ 0x4 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define QS_XTR_FRM_PRUNING_RSZ 0x4 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5)) 35*4882a593Smuzhiyun #define QS_XTR_CFG_DP_WM_M GENMASK(7, 5) 36*4882a593Smuzhiyun #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5) 37*4882a593Smuzhiyun #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2)) 38*4882a593Smuzhiyun #define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2) 39*4882a593Smuzhiyun #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2) 40*4882a593Smuzhiyun #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0)) 41*4882a593Smuzhiyun #define QS_XTR_CFG_OFLW_ERR_STICKY_M GENMASK(1, 0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define QS_INJ_GRP_CFG_RSZ 0x4 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) 46*4882a593Smuzhiyun #define QS_INJ_GRP_CFG_MODE_M GENMASK(3, 2) 47*4882a593Smuzhiyun #define QS_INJ_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) 48*4882a593Smuzhiyun #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define QS_INJ_WR_RSZ 0x4 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define QS_INJ_CTRL_RSZ 0x4 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define QS_INJ_CTRL_GAP_SIZE(x) (((x) << 21) & GENMASK(24, 21)) 55*4882a593Smuzhiyun #define QS_INJ_CTRL_GAP_SIZE_M GENMASK(24, 21) 56*4882a593Smuzhiyun #define QS_INJ_CTRL_GAP_SIZE_X(x) (((x) & GENMASK(24, 21)) >> 21) 57*4882a593Smuzhiyun #define QS_INJ_CTRL_ABORT BIT(20) 58*4882a593Smuzhiyun #define QS_INJ_CTRL_EOF BIT(19) 59*4882a593Smuzhiyun #define QS_INJ_CTRL_SOF BIT(18) 60*4882a593Smuzhiyun #define QS_INJ_CTRL_VLD_BYTES(x) (((x) << 16) & GENMASK(17, 16)) 61*4882a593Smuzhiyun #define QS_INJ_CTRL_VLD_BYTES_M GENMASK(17, 16) 62*4882a593Smuzhiyun #define QS_INJ_CTRL_VLD_BYTES_X(x) (((x) & GENMASK(17, 16)) >> 16) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define QS_INJ_STATUS_WMARK_REACHED(x) (((x) << 4) & GENMASK(5, 4)) 65*4882a593Smuzhiyun #define QS_INJ_STATUS_WMARK_REACHED_M GENMASK(5, 4) 66*4882a593Smuzhiyun #define QS_INJ_STATUS_WMARK_REACHED_X(x) (((x) & GENMASK(5, 4)) >> 4) 67*4882a593Smuzhiyun #define QS_INJ_STATUS_FIFO_RDY(x) (((x) << 2) & GENMASK(3, 2)) 68*4882a593Smuzhiyun #define QS_INJ_STATUS_FIFO_RDY_M GENMASK(3, 2) 69*4882a593Smuzhiyun #define QS_INJ_STATUS_FIFO_RDY_X(x) (((x) & GENMASK(3, 2)) >> 2) 70*4882a593Smuzhiyun #define QS_INJ_STATUS_INJ_IN_PROGRESS(x) ((x) & GENMASK(1, 0)) 71*4882a593Smuzhiyun #define QS_INJ_STATUS_INJ_IN_PROGRESS_M GENMASK(1, 0) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define QS_INJ_ERR_RSZ 0x4 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define QS_INJ_ERR_ABORT_ERR_STICKY BIT(1) 76*4882a593Smuzhiyun #define QS_INJ_ERR_WR_ERR_STICKY BIT(0) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif 79