1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun /* Microsemi Ocelot Switch driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2019 Microsemi Corporation 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MSCC_OCELOT_POLICE_H_ 8*4882a593Smuzhiyun #define _MSCC_OCELOT_POLICE_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "ocelot.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun enum mscc_qos_rate_mode { 13*4882a593Smuzhiyun MSCC_QOS_RATE_MODE_DISABLED, /* Policer/shaper disabled */ 14*4882a593Smuzhiyun MSCC_QOS_RATE_MODE_LINE, /* Measure line rate in kbps incl. IPG */ 15*4882a593Smuzhiyun MSCC_QOS_RATE_MODE_DATA, /* Measures data rate in kbps excl. IPG */ 16*4882a593Smuzhiyun MSCC_QOS_RATE_MODE_FRAME, /* Measures frame rate in fps */ 17*4882a593Smuzhiyun __MSCC_QOS_RATE_MODE_END, 18*4882a593Smuzhiyun NUM_MSCC_QOS_RATE_MODE = __MSCC_QOS_RATE_MODE_END, 19*4882a593Smuzhiyun MSCC_QOS_RATE_MODE_MAX = __MSCC_QOS_RATE_MODE_END - 1, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct qos_policer_conf { 23*4882a593Smuzhiyun enum mscc_qos_rate_mode mode; 24*4882a593Smuzhiyun bool dlb; /* Enable DLB (dual leaky bucket mode */ 25*4882a593Smuzhiyun bool cf; /* Coupling flag (ignored in SLB mode) */ 26*4882a593Smuzhiyun u32 cir; /* CIR in kbps/fps (ignored in SLB mode) */ 27*4882a593Smuzhiyun u32 cbs; /* CBS in bytes/frames (ignored in SLB mode) */ 28*4882a593Smuzhiyun u32 pir; /* PIR in kbps/fps */ 29*4882a593Smuzhiyun u32 pbs; /* PBS in bytes/frames */ 30*4882a593Smuzhiyun u8 ipg; /* Size of IPG when MSCC_QOS_RATE_MODE_LINE is chosen */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun int qos_policer_conf_set(struct ocelot *ocelot, int port, u32 pol_ix, 34*4882a593Smuzhiyun struct qos_policer_conf *conf); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* _MSCC_OCELOT_POLICE_H_ */ 37