1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun /* Microsemi Ocelot Switch driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2019 Microsemi Corporation
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <soc/mscc/ocelot.h>
8*4882a593Smuzhiyun #include "ocelot_police.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /* Types for ANA:POL[0-192]:POL_MODE_CFG.FRM_MODE */
11*4882a593Smuzhiyun #define POL_MODE_LINERATE 0 /* Incl IPG. Unit: 33 1/3 kbps, 4096 bytes */
12*4882a593Smuzhiyun #define POL_MODE_DATARATE 1 /* Excl IPG. Unit: 33 1/3 kbps, 4096 bytes */
13*4882a593Smuzhiyun #define POL_MODE_FRMRATE_HI 2 /* Unit: 33 1/3 fps, 32.8 frames */
14*4882a593Smuzhiyun #define POL_MODE_FRMRATE_LO 3 /* Unit: 1/3 fps, 0.3 frames */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* Policer indexes */
17*4882a593Smuzhiyun #define POL_IX_PORT 0 /* 0-11 : Port policers */
18*4882a593Smuzhiyun #define POL_IX_QUEUE 32 /* 32-127 : Queue policers */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Default policer order */
21*4882a593Smuzhiyun #define POL_ORDER 0x1d3 /* Ocelot policer order: Serial (QoS -> Port -> VCAP) */
22*4882a593Smuzhiyun
qos_policer_conf_set(struct ocelot * ocelot,int port,u32 pol_ix,struct qos_policer_conf * conf)23*4882a593Smuzhiyun int qos_policer_conf_set(struct ocelot *ocelot, int port, u32 pol_ix,
24*4882a593Smuzhiyun struct qos_policer_conf *conf)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun u32 cf = 0, cir_ena = 0, frm_mode = POL_MODE_LINERATE;
27*4882a593Smuzhiyun u32 cir = 0, cbs = 0, pir = 0, pbs = 0;
28*4882a593Smuzhiyun bool cir_discard = 0, pir_discard = 0;
29*4882a593Smuzhiyun u32 pbs_max = 0, cbs_max = 0;
30*4882a593Smuzhiyun u8 ipg = 20;
31*4882a593Smuzhiyun u32 value;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun pir = conf->pir;
34*4882a593Smuzhiyun pbs = conf->pbs;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun switch (conf->mode) {
37*4882a593Smuzhiyun case MSCC_QOS_RATE_MODE_LINE:
38*4882a593Smuzhiyun case MSCC_QOS_RATE_MODE_DATA:
39*4882a593Smuzhiyun if (conf->mode == MSCC_QOS_RATE_MODE_LINE) {
40*4882a593Smuzhiyun frm_mode = POL_MODE_LINERATE;
41*4882a593Smuzhiyun ipg = min_t(u8, GENMASK(4, 0), conf->ipg);
42*4882a593Smuzhiyun } else {
43*4882a593Smuzhiyun frm_mode = POL_MODE_DATARATE;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun if (conf->dlb) {
46*4882a593Smuzhiyun cir_ena = 1;
47*4882a593Smuzhiyun cir = conf->cir;
48*4882a593Smuzhiyun cbs = conf->cbs;
49*4882a593Smuzhiyun if (cir == 0 && cbs == 0) {
50*4882a593Smuzhiyun /* Discard cir frames */
51*4882a593Smuzhiyun cir_discard = 1;
52*4882a593Smuzhiyun } else {
53*4882a593Smuzhiyun cir = DIV_ROUND_UP(cir, 100);
54*4882a593Smuzhiyun cir *= 3; /* 33 1/3 kbps */
55*4882a593Smuzhiyun cbs = DIV_ROUND_UP(cbs, 4096);
56*4882a593Smuzhiyun cbs = (cbs ? cbs : 1); /* No zero burst size */
57*4882a593Smuzhiyun cbs_max = 60; /* Limit burst size */
58*4882a593Smuzhiyun cf = conf->cf;
59*4882a593Smuzhiyun if (cf)
60*4882a593Smuzhiyun pir += conf->cir;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun if (pir == 0 && pbs == 0) {
64*4882a593Smuzhiyun /* Discard PIR frames */
65*4882a593Smuzhiyun pir_discard = 1;
66*4882a593Smuzhiyun } else {
67*4882a593Smuzhiyun pir = DIV_ROUND_UP(pir, 100);
68*4882a593Smuzhiyun pir *= 3; /* 33 1/3 kbps */
69*4882a593Smuzhiyun pbs = DIV_ROUND_UP(pbs, 4096);
70*4882a593Smuzhiyun pbs = (pbs ? pbs : 1); /* No zero burst size */
71*4882a593Smuzhiyun pbs_max = 60; /* Limit burst size */
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun case MSCC_QOS_RATE_MODE_FRAME:
75*4882a593Smuzhiyun if (pir >= 100) {
76*4882a593Smuzhiyun frm_mode = POL_MODE_FRMRATE_HI;
77*4882a593Smuzhiyun pir = DIV_ROUND_UP(pir, 100);
78*4882a593Smuzhiyun pir *= 3; /* 33 1/3 fps */
79*4882a593Smuzhiyun pbs = (pbs * 10) / 328; /* 32.8 frames */
80*4882a593Smuzhiyun pbs = (pbs ? pbs : 1); /* No zero burst size */
81*4882a593Smuzhiyun pbs_max = GENMASK(6, 0); /* Limit burst size */
82*4882a593Smuzhiyun } else {
83*4882a593Smuzhiyun frm_mode = POL_MODE_FRMRATE_LO;
84*4882a593Smuzhiyun if (pir == 0 && pbs == 0) {
85*4882a593Smuzhiyun /* Discard all frames */
86*4882a593Smuzhiyun pir_discard = 1;
87*4882a593Smuzhiyun cir_discard = 1;
88*4882a593Smuzhiyun } else {
89*4882a593Smuzhiyun pir *= 3; /* 1/3 fps */
90*4882a593Smuzhiyun pbs = (pbs * 10) / 3; /* 0.3 frames */
91*4882a593Smuzhiyun pbs = (pbs ? pbs : 1); /* No zero burst size */
92*4882a593Smuzhiyun pbs_max = 61; /* Limit burst size */
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun break;
96*4882a593Smuzhiyun default: /* MSCC_QOS_RATE_MODE_DISABLED */
97*4882a593Smuzhiyun /* Disable policer using maximum rate and zero burst */
98*4882a593Smuzhiyun pir = GENMASK(15, 0);
99*4882a593Smuzhiyun pbs = 0;
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Check limits */
104*4882a593Smuzhiyun if (pir > GENMASK(15, 0)) {
105*4882a593Smuzhiyun dev_err(ocelot->dev, "Invalid pir for port %d: %u (max %lu)\n",
106*4882a593Smuzhiyun port, pir, GENMASK(15, 0));
107*4882a593Smuzhiyun return -EINVAL;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (cir > GENMASK(15, 0)) {
111*4882a593Smuzhiyun dev_err(ocelot->dev, "Invalid cir for port %d: %u (max %lu)\n",
112*4882a593Smuzhiyun port, cir, GENMASK(15, 0));
113*4882a593Smuzhiyun return -EINVAL;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (pbs > pbs_max) {
117*4882a593Smuzhiyun dev_err(ocelot->dev, "Invalid pbs for port %d: %u (max %u)\n",
118*4882a593Smuzhiyun port, pbs, pbs_max);
119*4882a593Smuzhiyun return -EINVAL;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun if (cbs > cbs_max) {
123*4882a593Smuzhiyun dev_err(ocelot->dev, "Invalid cbs for port %d: %u (max %u)\n",
124*4882a593Smuzhiyun port, cbs, cbs_max);
125*4882a593Smuzhiyun return -EINVAL;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun value = (ANA_POL_MODE_CFG_IPG_SIZE(ipg) |
129*4882a593Smuzhiyun ANA_POL_MODE_CFG_FRM_MODE(frm_mode) |
130*4882a593Smuzhiyun (cf ? ANA_POL_MODE_CFG_DLB_COUPLED : 0) |
131*4882a593Smuzhiyun (cir_ena ? ANA_POL_MODE_CFG_CIR_ENA : 0) |
132*4882a593Smuzhiyun ANA_POL_MODE_CFG_OVERSHOOT_ENA);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun ocelot_write_gix(ocelot, value, ANA_POL_MODE_CFG, pol_ix);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun ocelot_write_gix(ocelot,
137*4882a593Smuzhiyun ANA_POL_PIR_CFG_PIR_RATE(pir) |
138*4882a593Smuzhiyun ANA_POL_PIR_CFG_PIR_BURST(pbs),
139*4882a593Smuzhiyun ANA_POL_PIR_CFG, pol_ix);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun ocelot_write_gix(ocelot,
142*4882a593Smuzhiyun (pir_discard ? GENMASK(22, 0) : 0),
143*4882a593Smuzhiyun ANA_POL_PIR_STATE, pol_ix);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun ocelot_write_gix(ocelot,
146*4882a593Smuzhiyun ANA_POL_CIR_CFG_CIR_RATE(cir) |
147*4882a593Smuzhiyun ANA_POL_CIR_CFG_CIR_BURST(cbs),
148*4882a593Smuzhiyun ANA_POL_CIR_CFG, pol_ix);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun ocelot_write_gix(ocelot,
151*4882a593Smuzhiyun (cir_discard ? GENMASK(22, 0) : 0),
152*4882a593Smuzhiyun ANA_POL_CIR_STATE, pol_ix);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
ocelot_port_policer_add(struct ocelot * ocelot,int port,struct ocelot_policer * pol)157*4882a593Smuzhiyun int ocelot_port_policer_add(struct ocelot *ocelot, int port,
158*4882a593Smuzhiyun struct ocelot_policer *pol)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct qos_policer_conf pp = { 0 };
161*4882a593Smuzhiyun int err;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun if (!pol)
164*4882a593Smuzhiyun return -EINVAL;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun pp.mode = MSCC_QOS_RATE_MODE_DATA;
167*4882a593Smuzhiyun pp.pir = pol->rate;
168*4882a593Smuzhiyun pp.pbs = pol->burst;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun dev_dbg(ocelot->dev, "%s: port %u pir %u kbps, pbs %u bytes\n",
171*4882a593Smuzhiyun __func__, port, pp.pir, pp.pbs);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun err = qos_policer_conf_set(ocelot, port, POL_IX_PORT + port, &pp);
174*4882a593Smuzhiyun if (err)
175*4882a593Smuzhiyun return err;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ocelot_rmw_gix(ocelot,
178*4882a593Smuzhiyun ANA_PORT_POL_CFG_PORT_POL_ENA |
179*4882a593Smuzhiyun ANA_PORT_POL_CFG_POL_ORDER(POL_ORDER),
180*4882a593Smuzhiyun ANA_PORT_POL_CFG_PORT_POL_ENA |
181*4882a593Smuzhiyun ANA_PORT_POL_CFG_POL_ORDER_M,
182*4882a593Smuzhiyun ANA_PORT_POL_CFG, port);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun EXPORT_SYMBOL(ocelot_port_policer_add);
187*4882a593Smuzhiyun
ocelot_port_policer_del(struct ocelot * ocelot,int port)188*4882a593Smuzhiyun int ocelot_port_policer_del(struct ocelot *ocelot, int port)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun struct qos_policer_conf pp = { 0 };
191*4882a593Smuzhiyun int err;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun dev_dbg(ocelot->dev, "%s: port %u\n", __func__, port);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun pp.mode = MSCC_QOS_RATE_MODE_DISABLED;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun err = qos_policer_conf_set(ocelot, port, POL_IX_PORT + port, &pp);
198*4882a593Smuzhiyun if (err)
199*4882a593Smuzhiyun return err;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun ocelot_rmw_gix(ocelot,
202*4882a593Smuzhiyun ANA_PORT_POL_CFG_POL_ORDER(POL_ORDER),
203*4882a593Smuzhiyun ANA_PORT_POL_CFG_PORT_POL_ENA |
204*4882a593Smuzhiyun ANA_PORT_POL_CFG_POL_ORDER_M,
205*4882a593Smuzhiyun ANA_PORT_POL_CFG, port);
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun return 0;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun EXPORT_SYMBOL(ocelot_port_policer_del);
210