1*4882a593Smuzhiyun // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2*4882a593Smuzhiyun /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/kernel.h>
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/types.h>
7*4882a593Smuzhiyun #include <linux/pci.h>
8*4882a593Smuzhiyun #include <linux/netdevice.h>
9*4882a593Smuzhiyun #include <linux/etherdevice.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/skbuff.h>
13*4882a593Smuzhiyun #include <linux/if_vlan.h>
14*4882a593Smuzhiyun #include <net/switchdev.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "pci.h"
17*4882a593Smuzhiyun #include "core.h"
18*4882a593Smuzhiyun #include "reg.h"
19*4882a593Smuzhiyun #include "port.h"
20*4882a593Smuzhiyun #include "trap.h"
21*4882a593Smuzhiyun #include "txheader.h"
22*4882a593Smuzhiyun #include "ib.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static const char mlxsw_sib_driver_name[] = "mlxsw_switchib";
25*4882a593Smuzhiyun static const char mlxsw_sib2_driver_name[] = "mlxsw_switchib2";
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct mlxsw_sib_port;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct mlxsw_sib {
30*4882a593Smuzhiyun struct mlxsw_sib_port **ports;
31*4882a593Smuzhiyun struct mlxsw_core *core;
32*4882a593Smuzhiyun const struct mlxsw_bus_info *bus_info;
33*4882a593Smuzhiyun u8 hw_id[ETH_ALEN];
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct mlxsw_sib_port {
37*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib;
38*4882a593Smuzhiyun u8 local_port;
39*4882a593Smuzhiyun struct {
40*4882a593Smuzhiyun u8 module;
41*4882a593Smuzhiyun } mapping;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* tx_v1_hdr_version
45*4882a593Smuzhiyun * Tx header version.
46*4882a593Smuzhiyun * Must be set to 1.
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun MLXSW_ITEM32(tx_v1, hdr, version, 0x00, 28, 4);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* tx_v1_hdr_ctl
51*4882a593Smuzhiyun * Packet control type.
52*4882a593Smuzhiyun * 0 - Ethernet control (e.g. EMADs, LACP)
53*4882a593Smuzhiyun * 1 - Ethernet data
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun MLXSW_ITEM32(tx_v1, hdr, ctl, 0x00, 26, 2);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* tx_v1_hdr_proto
58*4882a593Smuzhiyun * Packet protocol type. Must be set to 1 (Ethernet).
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun MLXSW_ITEM32(tx_v1, hdr, proto, 0x00, 21, 3);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* tx_v1_hdr_swid
63*4882a593Smuzhiyun * Switch partition ID. Must be set to 0.
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun MLXSW_ITEM32(tx_v1, hdr, swid, 0x00, 12, 3);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* tx_v1_hdr_control_tclass
68*4882a593Smuzhiyun * Indicates if the packet should use the control TClass and not one
69*4882a593Smuzhiyun * of the data TClasses.
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun MLXSW_ITEM32(tx_v1, hdr, control_tclass, 0x00, 6, 1);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* tx_v1_hdr_port_mid
74*4882a593Smuzhiyun * Destination local port for unicast packets.
75*4882a593Smuzhiyun * Destination multicast ID for multicast packets.
76*4882a593Smuzhiyun *
77*4882a593Smuzhiyun * Control packets are directed to a specific egress port, while data
78*4882a593Smuzhiyun * packets are transmitted through the CPU port (0) into the switch partition,
79*4882a593Smuzhiyun * where forwarding rules are applied.
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun MLXSW_ITEM32(tx_v1, hdr, port_mid, 0x04, 16, 16);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* tx_v1_hdr_type
84*4882a593Smuzhiyun * 0 - Data packets
85*4882a593Smuzhiyun * 6 - Control packets
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun MLXSW_ITEM32(tx_v1, hdr, type, 0x0C, 0, 4);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static void
mlxsw_sib_tx_v1_hdr_construct(struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)90*4882a593Smuzhiyun mlxsw_sib_tx_v1_hdr_construct(struct sk_buff *skb,
91*4882a593Smuzhiyun const struct mlxsw_tx_info *tx_info)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun memset(txhdr, 0, MLXSW_TXHDR_LEN);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun mlxsw_tx_v1_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
98*4882a593Smuzhiyun mlxsw_tx_v1_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
99*4882a593Smuzhiyun mlxsw_tx_v1_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
100*4882a593Smuzhiyun mlxsw_tx_v1_hdr_swid_set(txhdr, 0);
101*4882a593Smuzhiyun mlxsw_tx_v1_hdr_control_tclass_set(txhdr, 1);
102*4882a593Smuzhiyun mlxsw_tx_v1_hdr_port_mid_set(txhdr, tx_info->local_port);
103*4882a593Smuzhiyun mlxsw_tx_v1_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
mlxsw_sib_hw_id_get(struct mlxsw_sib * mlxsw_sib)106*4882a593Smuzhiyun static int mlxsw_sib_hw_id_get(struct mlxsw_sib *mlxsw_sib)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
109*4882a593Smuzhiyun int err;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(spad), spad_pl);
112*4882a593Smuzhiyun if (err)
113*4882a593Smuzhiyun return err;
114*4882a593Smuzhiyun mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sib->hw_id);
115*4882a593Smuzhiyun return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static int
mlxsw_sib_port_admin_status_set(struct mlxsw_sib_port * mlxsw_sib_port,bool is_up)119*4882a593Smuzhiyun mlxsw_sib_port_admin_status_set(struct mlxsw_sib_port *mlxsw_sib_port,
120*4882a593Smuzhiyun bool is_up)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
123*4882a593Smuzhiyun char paos_pl[MLXSW_REG_PAOS_LEN];
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun mlxsw_reg_paos_pack(paos_pl, mlxsw_sib_port->local_port,
126*4882a593Smuzhiyun is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
127*4882a593Smuzhiyun MLXSW_PORT_ADMIN_STATUS_DOWN);
128*4882a593Smuzhiyun return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(paos), paos_pl);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
mlxsw_sib_port_mtu_set(struct mlxsw_sib_port * mlxsw_sib_port,u16 mtu)131*4882a593Smuzhiyun static int mlxsw_sib_port_mtu_set(struct mlxsw_sib_port *mlxsw_sib_port,
132*4882a593Smuzhiyun u16 mtu)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
135*4882a593Smuzhiyun char pmtu_pl[MLXSW_REG_PMTU_LEN];
136*4882a593Smuzhiyun int max_mtu;
137*4882a593Smuzhiyun int err;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, 0);
140*4882a593Smuzhiyun err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
141*4882a593Smuzhiyun if (err)
142*4882a593Smuzhiyun return err;
143*4882a593Smuzhiyun max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (mtu > max_mtu)
146*4882a593Smuzhiyun return -EINVAL;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, mtu);
149*4882a593Smuzhiyun return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
mlxsw_sib_port_set(struct mlxsw_sib_port * mlxsw_sib_port,u8 port)152*4882a593Smuzhiyun static int mlxsw_sib_port_set(struct mlxsw_sib_port *mlxsw_sib_port, u8 port)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
155*4882a593Smuzhiyun char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
156*4882a593Smuzhiyun int err;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sib_port->local_port);
159*4882a593Smuzhiyun mlxsw_reg_plib_ib_port_set(plib_pl, port);
160*4882a593Smuzhiyun err = mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(plib), plib_pl);
161*4882a593Smuzhiyun return err;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
mlxsw_sib_port_swid_set(struct mlxsw_sib_port * mlxsw_sib_port,u8 swid)164*4882a593Smuzhiyun static int mlxsw_sib_port_swid_set(struct mlxsw_sib_port *mlxsw_sib_port,
165*4882a593Smuzhiyun u8 swid)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
168*4882a593Smuzhiyun char pspa_pl[MLXSW_REG_PSPA_LEN];
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sib_port->local_port);
171*4882a593Smuzhiyun return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pspa), pspa_pl);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
mlxsw_sib_port_module_info_get(struct mlxsw_sib * mlxsw_sib,u8 local_port,u8 * p_module,u8 * p_width)174*4882a593Smuzhiyun static int mlxsw_sib_port_module_info_get(struct mlxsw_sib *mlxsw_sib,
175*4882a593Smuzhiyun u8 local_port, u8 *p_module,
176*4882a593Smuzhiyun u8 *p_width)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun char pmlp_pl[MLXSW_REG_PMLP_LEN];
179*4882a593Smuzhiyun int err;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
182*4882a593Smuzhiyun err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmlp), pmlp_pl);
183*4882a593Smuzhiyun if (err)
184*4882a593Smuzhiyun return err;
185*4882a593Smuzhiyun *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
186*4882a593Smuzhiyun *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
187*4882a593Smuzhiyun return 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
mlxsw_sib_port_speed_set(struct mlxsw_sib_port * mlxsw_sib_port,u16 speed,u16 width)190*4882a593Smuzhiyun static int mlxsw_sib_port_speed_set(struct mlxsw_sib_port *mlxsw_sib_port,
191*4882a593Smuzhiyun u16 speed, u16 width)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
194*4882a593Smuzhiyun char ptys_pl[MLXSW_REG_PTYS_LEN];
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sib_port->local_port, speed,
197*4882a593Smuzhiyun width);
198*4882a593Smuzhiyun return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(ptys), ptys_pl);
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
mlxsw_sib_port_created(struct mlxsw_sib * mlxsw_sib,u8 local_port)201*4882a593Smuzhiyun static bool mlxsw_sib_port_created(struct mlxsw_sib *mlxsw_sib, u8 local_port)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun return mlxsw_sib->ports[local_port] != NULL;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
__mlxsw_sib_port_create(struct mlxsw_sib * mlxsw_sib,u8 local_port,u8 module,u8 width)206*4882a593Smuzhiyun static int __mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
207*4882a593Smuzhiyun u8 module, u8 width)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun struct mlxsw_sib_port *mlxsw_sib_port;
210*4882a593Smuzhiyun int err;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun mlxsw_sib_port = kzalloc(sizeof(*mlxsw_sib_port), GFP_KERNEL);
213*4882a593Smuzhiyun if (!mlxsw_sib_port)
214*4882a593Smuzhiyun return -ENOMEM;
215*4882a593Smuzhiyun mlxsw_sib_port->mlxsw_sib = mlxsw_sib;
216*4882a593Smuzhiyun mlxsw_sib_port->local_port = local_port;
217*4882a593Smuzhiyun mlxsw_sib_port->mapping.module = module;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun err = mlxsw_sib_port_swid_set(mlxsw_sib_port, 0);
220*4882a593Smuzhiyun if (err) {
221*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set SWID\n",
222*4882a593Smuzhiyun mlxsw_sib_port->local_port);
223*4882a593Smuzhiyun goto err_port_swid_set;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* Expose the IB port number as it's front panel name */
227*4882a593Smuzhiyun err = mlxsw_sib_port_set(mlxsw_sib_port, module + 1);
228*4882a593Smuzhiyun if (err) {
229*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set IB port\n",
230*4882a593Smuzhiyun mlxsw_sib_port->local_port);
231*4882a593Smuzhiyun goto err_port_ib_set;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* Supports all speeds from SDR to FDR (bitmask) and support bus width
235*4882a593Smuzhiyun * of 1x, 2x and 4x (3 bits bitmask)
236*4882a593Smuzhiyun */
237*4882a593Smuzhiyun err = mlxsw_sib_port_speed_set(mlxsw_sib_port,
238*4882a593Smuzhiyun MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
239*4882a593Smuzhiyun BIT(3) - 1);
240*4882a593Smuzhiyun if (err) {
241*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set speed\n",
242*4882a593Smuzhiyun mlxsw_sib_port->local_port);
243*4882a593Smuzhiyun goto err_port_speed_set;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /* Change to the maximum MTU the device supports, the SMA will take
247*4882a593Smuzhiyun * care of the active MTU
248*4882a593Smuzhiyun */
249*4882a593Smuzhiyun err = mlxsw_sib_port_mtu_set(mlxsw_sib_port, MLXSW_IB_DEFAULT_MTU);
250*4882a593Smuzhiyun if (err) {
251*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set MTU\n",
252*4882a593Smuzhiyun mlxsw_sib_port->local_port);
253*4882a593Smuzhiyun goto err_port_mtu_set;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun err = mlxsw_sib_port_admin_status_set(mlxsw_sib_port, true);
257*4882a593Smuzhiyun if (err) {
258*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
259*4882a593Smuzhiyun mlxsw_sib_port->local_port);
260*4882a593Smuzhiyun goto err_port_admin_set;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun mlxsw_core_port_ib_set(mlxsw_sib->core, mlxsw_sib_port->local_port,
264*4882a593Smuzhiyun mlxsw_sib_port);
265*4882a593Smuzhiyun mlxsw_sib->ports[local_port] = mlxsw_sib_port;
266*4882a593Smuzhiyun return 0;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun err_port_admin_set:
269*4882a593Smuzhiyun err_port_mtu_set:
270*4882a593Smuzhiyun err_port_speed_set:
271*4882a593Smuzhiyun err_port_ib_set:
272*4882a593Smuzhiyun mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
273*4882a593Smuzhiyun err_port_swid_set:
274*4882a593Smuzhiyun kfree(mlxsw_sib_port);
275*4882a593Smuzhiyun return err;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
mlxsw_sib_port_create(struct mlxsw_sib * mlxsw_sib,u8 local_port,u8 module,u8 width)278*4882a593Smuzhiyun static int mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
279*4882a593Smuzhiyun u8 module, u8 width)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun int err;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun err = mlxsw_core_port_init(mlxsw_sib->core, local_port,
284*4882a593Smuzhiyun module + 1, false, 0, false, 0,
285*4882a593Smuzhiyun mlxsw_sib->hw_id, sizeof(mlxsw_sib->hw_id));
286*4882a593Smuzhiyun if (err) {
287*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to init core port\n",
288*4882a593Smuzhiyun local_port);
289*4882a593Smuzhiyun return err;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun err = __mlxsw_sib_port_create(mlxsw_sib, local_port, module, width);
292*4882a593Smuzhiyun if (err)
293*4882a593Smuzhiyun goto err_port_create;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun return 0;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun err_port_create:
298*4882a593Smuzhiyun mlxsw_core_port_fini(mlxsw_sib->core, local_port);
299*4882a593Smuzhiyun return err;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
__mlxsw_sib_port_remove(struct mlxsw_sib * mlxsw_sib,u8 local_port)302*4882a593Smuzhiyun static void __mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun struct mlxsw_sib_port *mlxsw_sib_port = mlxsw_sib->ports[local_port];
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun mlxsw_core_port_clear(mlxsw_sib->core, local_port, mlxsw_sib);
307*4882a593Smuzhiyun mlxsw_sib->ports[local_port] = NULL;
308*4882a593Smuzhiyun mlxsw_sib_port_admin_status_set(mlxsw_sib_port, false);
309*4882a593Smuzhiyun mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
310*4882a593Smuzhiyun kfree(mlxsw_sib_port);
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
mlxsw_sib_port_remove(struct mlxsw_sib * mlxsw_sib,u8 local_port)313*4882a593Smuzhiyun static void mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun __mlxsw_sib_port_remove(mlxsw_sib, local_port);
316*4882a593Smuzhiyun mlxsw_core_port_fini(mlxsw_sib->core, local_port);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
mlxsw_sib_ports_remove(struct mlxsw_sib * mlxsw_sib)319*4882a593Smuzhiyun static void mlxsw_sib_ports_remove(struct mlxsw_sib *mlxsw_sib)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun int i;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++)
324*4882a593Smuzhiyun if (mlxsw_sib_port_created(mlxsw_sib, i))
325*4882a593Smuzhiyun mlxsw_sib_port_remove(mlxsw_sib, i);
326*4882a593Smuzhiyun kfree(mlxsw_sib->ports);
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
mlxsw_sib_ports_create(struct mlxsw_sib * mlxsw_sib)329*4882a593Smuzhiyun static int mlxsw_sib_ports_create(struct mlxsw_sib *mlxsw_sib)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun size_t alloc_size;
332*4882a593Smuzhiyun u8 module, width;
333*4882a593Smuzhiyun int i;
334*4882a593Smuzhiyun int err;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun alloc_size = sizeof(struct mlxsw_sib_port *) * MLXSW_PORT_MAX_IB_PORTS;
337*4882a593Smuzhiyun mlxsw_sib->ports = kzalloc(alloc_size, GFP_KERNEL);
338*4882a593Smuzhiyun if (!mlxsw_sib->ports)
339*4882a593Smuzhiyun return -ENOMEM;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++) {
342*4882a593Smuzhiyun err = mlxsw_sib_port_module_info_get(mlxsw_sib, i, &module,
343*4882a593Smuzhiyun &width);
344*4882a593Smuzhiyun if (err)
345*4882a593Smuzhiyun goto err_port_module_info_get;
346*4882a593Smuzhiyun if (!width)
347*4882a593Smuzhiyun continue;
348*4882a593Smuzhiyun err = mlxsw_sib_port_create(mlxsw_sib, i, module, width);
349*4882a593Smuzhiyun if (err)
350*4882a593Smuzhiyun goto err_port_create;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun return 0;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun err_port_create:
355*4882a593Smuzhiyun err_port_module_info_get:
356*4882a593Smuzhiyun for (i--; i >= 1; i--)
357*4882a593Smuzhiyun if (mlxsw_sib_port_created(mlxsw_sib, i))
358*4882a593Smuzhiyun mlxsw_sib_port_remove(mlxsw_sib, i);
359*4882a593Smuzhiyun kfree(mlxsw_sib->ports);
360*4882a593Smuzhiyun return err;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun static void
mlxsw_sib_pude_ib_event_func(struct mlxsw_sib_port * mlxsw_sib_port,enum mlxsw_reg_pude_oper_status status)364*4882a593Smuzhiyun mlxsw_sib_pude_ib_event_func(struct mlxsw_sib_port *mlxsw_sib_port,
365*4882a593Smuzhiyun enum mlxsw_reg_pude_oper_status status)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun if (status == MLXSW_PORT_OPER_STATUS_UP)
368*4882a593Smuzhiyun pr_info("ib link for port %d - up\n",
369*4882a593Smuzhiyun mlxsw_sib_port->mapping.module + 1);
370*4882a593Smuzhiyun else
371*4882a593Smuzhiyun pr_info("ib link for port %d - down\n",
372*4882a593Smuzhiyun mlxsw_sib_port->mapping.module + 1);
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
mlxsw_sib_pude_event_func(const struct mlxsw_reg_info * reg,char * pude_pl,void * priv)375*4882a593Smuzhiyun static void mlxsw_sib_pude_event_func(const struct mlxsw_reg_info *reg,
376*4882a593Smuzhiyun char *pude_pl, void *priv)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib = priv;
379*4882a593Smuzhiyun struct mlxsw_sib_port *mlxsw_sib_port;
380*4882a593Smuzhiyun enum mlxsw_reg_pude_oper_status status;
381*4882a593Smuzhiyun u8 local_port;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun local_port = mlxsw_reg_pude_local_port_get(pude_pl);
384*4882a593Smuzhiyun mlxsw_sib_port = mlxsw_sib->ports[local_port];
385*4882a593Smuzhiyun if (!mlxsw_sib_port) {
386*4882a593Smuzhiyun dev_warn(mlxsw_sib->bus_info->dev, "Port %d: Link event received for non-existent port\n",
387*4882a593Smuzhiyun local_port);
388*4882a593Smuzhiyun return;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun status = mlxsw_reg_pude_oper_status_get(pude_pl);
392*4882a593Smuzhiyun mlxsw_sib_pude_ib_event_func(mlxsw_sib_port, status);
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun static const struct mlxsw_listener mlxsw_sib_listener[] = {
396*4882a593Smuzhiyun MLXSW_EVENTL(mlxsw_sib_pude_event_func, PUDE, EMAD),
397*4882a593Smuzhiyun };
398*4882a593Smuzhiyun
mlxsw_sib_taps_init(struct mlxsw_sib * mlxsw_sib)399*4882a593Smuzhiyun static int mlxsw_sib_taps_init(struct mlxsw_sib *mlxsw_sib)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun int i;
402*4882a593Smuzhiyun int err;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
405*4882a593Smuzhiyun err = mlxsw_core_trap_register(mlxsw_sib->core,
406*4882a593Smuzhiyun &mlxsw_sib_listener[i],
407*4882a593Smuzhiyun mlxsw_sib);
408*4882a593Smuzhiyun if (err)
409*4882a593Smuzhiyun goto err_rx_listener_register;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun return 0;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun err_rx_listener_register:
415*4882a593Smuzhiyun for (i--; i >= 0; i--) {
416*4882a593Smuzhiyun mlxsw_core_trap_unregister(mlxsw_sib->core,
417*4882a593Smuzhiyun &mlxsw_sib_listener[i],
418*4882a593Smuzhiyun mlxsw_sib);
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun return err;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
mlxsw_sib_traps_fini(struct mlxsw_sib * mlxsw_sib)424*4882a593Smuzhiyun static void mlxsw_sib_traps_fini(struct mlxsw_sib *mlxsw_sib)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun int i;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
429*4882a593Smuzhiyun mlxsw_core_trap_unregister(mlxsw_sib->core,
430*4882a593Smuzhiyun &mlxsw_sib_listener[i], mlxsw_sib);
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
mlxsw_sib_basic_trap_groups_set(struct mlxsw_core * mlxsw_core)434*4882a593Smuzhiyun static int mlxsw_sib_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
435*4882a593Smuzhiyun {
436*4882a593Smuzhiyun char htgt_pl[MLXSW_REG_HTGT_LEN];
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
439*4882a593Smuzhiyun MLXSW_REG_HTGT_INVALID_POLICER,
440*4882a593Smuzhiyun MLXSW_REG_HTGT_DEFAULT_PRIORITY,
441*4882a593Smuzhiyun MLXSW_REG_HTGT_DEFAULT_TC);
442*4882a593Smuzhiyun mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
443*4882a593Smuzhiyun mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
444*4882a593Smuzhiyun MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD);
445*4882a593Smuzhiyun return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
mlxsw_sib_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)448*4882a593Smuzhiyun static int mlxsw_sib_init(struct mlxsw_core *mlxsw_core,
449*4882a593Smuzhiyun const struct mlxsw_bus_info *mlxsw_bus_info,
450*4882a593Smuzhiyun struct netlink_ext_ack *extack)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
453*4882a593Smuzhiyun int err;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun mlxsw_sib->core = mlxsw_core;
456*4882a593Smuzhiyun mlxsw_sib->bus_info = mlxsw_bus_info;
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun err = mlxsw_sib_hw_id_get(mlxsw_sib);
459*4882a593Smuzhiyun if (err) {
460*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Failed to get switch HW ID\n");
461*4882a593Smuzhiyun return err;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun err = mlxsw_sib_ports_create(mlxsw_sib);
465*4882a593Smuzhiyun if (err) {
466*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Failed to create ports\n");
467*4882a593Smuzhiyun return err;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun err = mlxsw_sib_taps_init(mlxsw_sib);
471*4882a593Smuzhiyun if (err) {
472*4882a593Smuzhiyun dev_err(mlxsw_sib->bus_info->dev, "Failed to set traps\n");
473*4882a593Smuzhiyun goto err_traps_init_err;
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun return 0;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun err_traps_init_err:
479*4882a593Smuzhiyun mlxsw_sib_ports_remove(mlxsw_sib);
480*4882a593Smuzhiyun return err;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
mlxsw_sib_fini(struct mlxsw_core * mlxsw_core)483*4882a593Smuzhiyun static void mlxsw_sib_fini(struct mlxsw_core *mlxsw_core)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun mlxsw_sib_traps_fini(mlxsw_sib);
488*4882a593Smuzhiyun mlxsw_sib_ports_remove(mlxsw_sib);
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun static const struct mlxsw_config_profile mlxsw_sib_config_profile = {
492*4882a593Smuzhiyun .used_max_system_port = 1,
493*4882a593Smuzhiyun .max_system_port = 48000,
494*4882a593Smuzhiyun .used_max_ib_mc = 1,
495*4882a593Smuzhiyun .max_ib_mc = 27,
496*4882a593Smuzhiyun .used_max_pkey = 1,
497*4882a593Smuzhiyun .max_pkey = 32,
498*4882a593Smuzhiyun .swid_config = {
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun .used_type = 1,
501*4882a593Smuzhiyun .type = MLXSW_PORT_SWID_TYPE_IB,
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun },
504*4882a593Smuzhiyun };
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun static struct mlxsw_driver mlxsw_sib_driver = {
507*4882a593Smuzhiyun .kind = mlxsw_sib_driver_name,
508*4882a593Smuzhiyun .priv_size = sizeof(struct mlxsw_sib),
509*4882a593Smuzhiyun .init = mlxsw_sib_init,
510*4882a593Smuzhiyun .fini = mlxsw_sib_fini,
511*4882a593Smuzhiyun .basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set,
512*4882a593Smuzhiyun .txhdr_construct = mlxsw_sib_tx_v1_hdr_construct,
513*4882a593Smuzhiyun .txhdr_len = MLXSW_TXHDR_LEN,
514*4882a593Smuzhiyun .profile = &mlxsw_sib_config_profile,
515*4882a593Smuzhiyun };
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun static struct mlxsw_driver mlxsw_sib2_driver = {
518*4882a593Smuzhiyun .kind = mlxsw_sib2_driver_name,
519*4882a593Smuzhiyun .priv_size = sizeof(struct mlxsw_sib),
520*4882a593Smuzhiyun .init = mlxsw_sib_init,
521*4882a593Smuzhiyun .fini = mlxsw_sib_fini,
522*4882a593Smuzhiyun .basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set,
523*4882a593Smuzhiyun .txhdr_construct = mlxsw_sib_tx_v1_hdr_construct,
524*4882a593Smuzhiyun .txhdr_len = MLXSW_TXHDR_LEN,
525*4882a593Smuzhiyun .profile = &mlxsw_sib_config_profile,
526*4882a593Smuzhiyun };
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun static const struct pci_device_id mlxsw_sib_pci_id_table[] = {
529*4882a593Smuzhiyun {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB), 0},
530*4882a593Smuzhiyun {0, },
531*4882a593Smuzhiyun };
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun static struct pci_driver mlxsw_sib_pci_driver = {
534*4882a593Smuzhiyun .name = mlxsw_sib_driver_name,
535*4882a593Smuzhiyun .id_table = mlxsw_sib_pci_id_table,
536*4882a593Smuzhiyun };
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun static const struct pci_device_id mlxsw_sib2_pci_id_table[] = {
539*4882a593Smuzhiyun {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB2), 0},
540*4882a593Smuzhiyun {0, },
541*4882a593Smuzhiyun };
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun static struct pci_driver mlxsw_sib2_pci_driver = {
544*4882a593Smuzhiyun .name = mlxsw_sib2_driver_name,
545*4882a593Smuzhiyun .id_table = mlxsw_sib2_pci_id_table,
546*4882a593Smuzhiyun };
547*4882a593Smuzhiyun
mlxsw_sib_module_init(void)548*4882a593Smuzhiyun static int __init mlxsw_sib_module_init(void)
549*4882a593Smuzhiyun {
550*4882a593Smuzhiyun int err;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun err = mlxsw_core_driver_register(&mlxsw_sib_driver);
553*4882a593Smuzhiyun if (err)
554*4882a593Smuzhiyun return err;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun err = mlxsw_core_driver_register(&mlxsw_sib2_driver);
557*4882a593Smuzhiyun if (err)
558*4882a593Smuzhiyun goto err_sib2_driver_register;
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun err = mlxsw_pci_driver_register(&mlxsw_sib_pci_driver);
561*4882a593Smuzhiyun if (err)
562*4882a593Smuzhiyun goto err_sib_pci_driver_register;
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun err = mlxsw_pci_driver_register(&mlxsw_sib2_pci_driver);
565*4882a593Smuzhiyun if (err)
566*4882a593Smuzhiyun goto err_sib2_pci_driver_register;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun return 0;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun err_sib2_pci_driver_register:
571*4882a593Smuzhiyun mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
572*4882a593Smuzhiyun err_sib_pci_driver_register:
573*4882a593Smuzhiyun mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
574*4882a593Smuzhiyun err_sib2_driver_register:
575*4882a593Smuzhiyun mlxsw_core_driver_unregister(&mlxsw_sib_driver);
576*4882a593Smuzhiyun return err;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
mlxsw_sib_module_exit(void)579*4882a593Smuzhiyun static void __exit mlxsw_sib_module_exit(void)
580*4882a593Smuzhiyun {
581*4882a593Smuzhiyun mlxsw_pci_driver_unregister(&mlxsw_sib2_pci_driver);
582*4882a593Smuzhiyun mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
583*4882a593Smuzhiyun mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
584*4882a593Smuzhiyun mlxsw_core_driver_unregister(&mlxsw_sib_driver);
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun module_init(mlxsw_sib_module_init);
588*4882a593Smuzhiyun module_exit(mlxsw_sib_module_exit);
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
591*4882a593Smuzhiyun MODULE_AUTHOR("Elad Raz <eladr@@mellanox.com>");
592*4882a593Smuzhiyun MODULE_DESCRIPTION("Mellanox SwitchIB and SwitchIB-2 driver");
593*4882a593Smuzhiyun MODULE_ALIAS("mlxsw_switchib2");
594*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, mlxsw_sib_pci_id_table);
595*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, mlxsw_sib2_pci_id_table);
596