1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2*4882a593Smuzhiyun /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #ifndef _MLXSW_RESOURCES_H
5*4882a593Smuzhiyun #define _MLXSW_RESOURCES_H
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/types.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun enum mlxsw_res_id {
11*4882a593Smuzhiyun MLXSW_RES_ID_KVD_SIZE,
12*4882a593Smuzhiyun MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
13*4882a593Smuzhiyun MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
14*4882a593Smuzhiyun MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE,
15*4882a593Smuzhiyun MLXSW_RES_ID_MAX_KVD_ACTION_SETS,
16*4882a593Smuzhiyun MLXSW_RES_ID_MAX_TRAP_GROUPS,
17*4882a593Smuzhiyun MLXSW_RES_ID_CQE_V0,
18*4882a593Smuzhiyun MLXSW_RES_ID_CQE_V1,
19*4882a593Smuzhiyun MLXSW_RES_ID_CQE_V2,
20*4882a593Smuzhiyun MLXSW_RES_ID_COUNTER_POOL_SIZE,
21*4882a593Smuzhiyun MLXSW_RES_ID_COUNTER_BANK_SIZE,
22*4882a593Smuzhiyun MLXSW_RES_ID_MAX_SPAN,
23*4882a593Smuzhiyun MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
24*4882a593Smuzhiyun MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
25*4882a593Smuzhiyun MLXSW_RES_ID_MAX_SYSTEM_PORT,
26*4882a593Smuzhiyun MLXSW_RES_ID_MAX_LAG,
27*4882a593Smuzhiyun MLXSW_RES_ID_MAX_LAG_MEMBERS,
28*4882a593Smuzhiyun MLXSW_RES_ID_LOCAL_PORTS_IN_1X,
29*4882a593Smuzhiyun MLXSW_RES_ID_LOCAL_PORTS_IN_2X,
30*4882a593Smuzhiyun MLXSW_RES_ID_LOCAL_PORTS_IN_4X,
31*4882a593Smuzhiyun MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER,
32*4882a593Smuzhiyun MLXSW_RES_ID_CELL_SIZE,
33*4882a593Smuzhiyun MLXSW_RES_ID_MAX_HEADROOM_SIZE,
34*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
35*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
36*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_REGIONS,
37*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_GROUPS,
38*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
39*4882a593Smuzhiyun MLXSW_RES_ID_ACL_FLEX_KEYS,
40*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
41*4882a593Smuzhiyun MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
42*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,
43*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,
44*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
45*4882a593Smuzhiyun MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB,
46*4882a593Smuzhiyun MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB,
47*4882a593Smuzhiyun MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB,
48*4882a593Smuzhiyun MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB,
49*4882a593Smuzhiyun MLXSW_RES_ID_ACL_MAX_BF_LOG,
50*4882a593Smuzhiyun MLXSW_RES_ID_MAX_GLOBAL_POLICERS,
51*4882a593Smuzhiyun MLXSW_RES_ID_MAX_CPU_POLICERS,
52*4882a593Smuzhiyun MLXSW_RES_ID_MAX_VRS,
53*4882a593Smuzhiyun MLXSW_RES_ID_MAX_RIFS,
54*4882a593Smuzhiyun MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES,
55*4882a593Smuzhiyun MLXSW_RES_ID_MAX_LPM_TREES,
56*4882a593Smuzhiyun MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4,
57*4882a593Smuzhiyun MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6,
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Internal resources.
60*4882a593Smuzhiyun * Determined by the SW, not queried from the HW.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun MLXSW_RES_ID_KVD_SINGLE_SIZE,
63*4882a593Smuzhiyun MLXSW_RES_ID_KVD_DOUBLE_SIZE,
64*4882a593Smuzhiyun MLXSW_RES_ID_KVD_LINEAR_SIZE,
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun __MLXSW_RES_ID_MAX,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static u16 mlxsw_res_ids[] = {
70*4882a593Smuzhiyun [MLXSW_RES_ID_KVD_SIZE] = 0x1001,
71*4882a593Smuzhiyun [MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
72*4882a593Smuzhiyun [MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
73*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005,
74*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007,
75*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
76*4882a593Smuzhiyun [MLXSW_RES_ID_CQE_V0] = 0x2210,
77*4882a593Smuzhiyun [MLXSW_RES_ID_CQE_V1] = 0x2211,
78*4882a593Smuzhiyun [MLXSW_RES_ID_CQE_V2] = 0x2212,
79*4882a593Smuzhiyun [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
80*4882a593Smuzhiyun [MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411,
81*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_SPAN] = 0x2420,
82*4882a593Smuzhiyun [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
83*4882a593Smuzhiyun [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
84*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
85*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_LAG] = 0x2520,
86*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
87*4882a593Smuzhiyun [MLXSW_RES_ID_LOCAL_PORTS_IN_1X] = 0x2610,
88*4882a593Smuzhiyun [MLXSW_RES_ID_LOCAL_PORTS_IN_2X] = 0x2611,
89*4882a593Smuzhiyun [MLXSW_RES_ID_LOCAL_PORTS_IN_4X] = 0x2612,
90*4882a593Smuzhiyun [MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805, /* Bytes */
91*4882a593Smuzhiyun [MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */
92*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811, /* Bytes */
93*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
94*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
95*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
96*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
97*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
98*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
99*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
100*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
101*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,
102*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,
103*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,
104*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950,
105*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951,
106*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952,
107*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953,
108*4882a593Smuzhiyun [MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960,
109*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10,
110*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
111*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_VRS] = 0x2C01,
112*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
113*4882a593Smuzhiyun [MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10,
114*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
115*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02,
116*4882a593Smuzhiyun [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03,
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun struct mlxsw_res {
120*4882a593Smuzhiyun bool valid[__MLXSW_RES_ID_MAX];
121*4882a593Smuzhiyun u64 values[__MLXSW_RES_ID_MAX];
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
mlxsw_res_valid(struct mlxsw_res * res,enum mlxsw_res_id res_id)124*4882a593Smuzhiyun static inline bool mlxsw_res_valid(struct mlxsw_res *res,
125*4882a593Smuzhiyun enum mlxsw_res_id res_id)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun return res->valid[res_id];
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun #define MLXSW_RES_VALID(res, short_res_id) \
131*4882a593Smuzhiyun mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
132*4882a593Smuzhiyun
mlxsw_res_get(struct mlxsw_res * res,enum mlxsw_res_id res_id)133*4882a593Smuzhiyun static inline u64 mlxsw_res_get(struct mlxsw_res *res,
134*4882a593Smuzhiyun enum mlxsw_res_id res_id)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun if (WARN_ON(!res->valid[res_id]))
137*4882a593Smuzhiyun return 0;
138*4882a593Smuzhiyun return res->values[res_id];
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #define MLXSW_RES_GET(res, short_res_id) \
142*4882a593Smuzhiyun mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
143*4882a593Smuzhiyun
mlxsw_res_set(struct mlxsw_res * res,enum mlxsw_res_id res_id,u64 value)144*4882a593Smuzhiyun static inline void mlxsw_res_set(struct mlxsw_res *res,
145*4882a593Smuzhiyun enum mlxsw_res_id res_id, u64 value)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun res->valid[res_id] = true;
148*4882a593Smuzhiyun res->values[res_id] = value;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun #define MLXSW_RES_SET(res, short_res_id, value) \
152*4882a593Smuzhiyun mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
153*4882a593Smuzhiyun
mlxsw_res_parse(struct mlxsw_res * res,u16 id,u64 value)154*4882a593Smuzhiyun static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun int i;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
159*4882a593Smuzhiyun if (mlxsw_res_ids[i] == id) {
160*4882a593Smuzhiyun mlxsw_res_set(res, i, value);
161*4882a593Smuzhiyun return;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun #endif
167