1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _MLXSW_PORT_H 5*4882a593Smuzhiyun #define _MLXSW_PORT_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/types.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define MLXSW_PORT_MAX_MTU 10000 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MLXSW_PORT_DEFAULT_VID 1 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MLXSW_PORT_SWID_DISABLED_PORT 255 14*4882a593Smuzhiyun #define MLXSW_PORT_SWID_ALL_SWIDS 254 15*4882a593Smuzhiyun #define MLXSW_PORT_SWID_TYPE_IB 1 16*4882a593Smuzhiyun #define MLXSW_PORT_SWID_TYPE_ETH 2 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MLXSW_PORT_MID 0xd000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MLXSW_PORT_MAX_IB_PHY_PORTS 36 21*4882a593Smuzhiyun #define MLXSW_PORT_MAX_IB_PORTS (MLXSW_PORT_MAX_IB_PHY_PORTS + 1) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MLXSW_PORT_CPU_PORT 0x0 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define MLXSW_PORT_DONT_CARE 0xFF 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun enum mlxsw_port_admin_status { 28*4882a593Smuzhiyun MLXSW_PORT_ADMIN_STATUS_UP = 1, 29*4882a593Smuzhiyun MLXSW_PORT_ADMIN_STATUS_DOWN = 2, 30*4882a593Smuzhiyun MLXSW_PORT_ADMIN_STATUS_UP_ONCE = 3, 31*4882a593Smuzhiyun MLXSW_PORT_ADMIN_STATUS_DISABLED = 4, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun enum mlxsw_reg_pude_oper_status { 35*4882a593Smuzhiyun MLXSW_PORT_OPER_STATUS_UP = 1, 36*4882a593Smuzhiyun MLXSW_PORT_OPER_STATUS_DOWN = 2, 37*4882a593Smuzhiyun MLXSW_PORT_OPER_STATUS_FAILURE = 4, /* Can be set to up again. */ 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* _MLXSW_PORT_H */ 41