1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2*4882a593Smuzhiyun /* Copyright (c) 2017-2019 Mellanox Technologies. All rights reserved */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #ifndef _MLXFW_H
5*4882a593Smuzhiyun #define _MLXFW_H
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/firmware.h>
8*4882a593Smuzhiyun #include <linux/netlink.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <net/devlink.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct mlxfw_dev {
13*4882a593Smuzhiyun const struct mlxfw_dev_ops *ops;
14*4882a593Smuzhiyun const char *psid;
15*4882a593Smuzhiyun u16 psid_size;
16*4882a593Smuzhiyun struct devlink *devlink;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static inline
mlxfw_dev_dev(struct mlxfw_dev * mlxfw_dev)20*4882a593Smuzhiyun struct device *mlxfw_dev_dev(struct mlxfw_dev *mlxfw_dev)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun return mlxfw_dev->devlink->dev;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define MLXFW_PRFX "mlxfw: "
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define mlxfw_info(mlxfw_dev, fmt, ...) \
28*4882a593Smuzhiyun dev_info(mlxfw_dev_dev(mlxfw_dev), MLXFW_PRFX fmt, ## __VA_ARGS__)
29*4882a593Smuzhiyun #define mlxfw_err(mlxfw_dev, fmt, ...) \
30*4882a593Smuzhiyun dev_err(mlxfw_dev_dev(mlxfw_dev), MLXFW_PRFX fmt, ## __VA_ARGS__)
31*4882a593Smuzhiyun #define mlxfw_dbg(mlxfw_dev, fmt, ...) \
32*4882a593Smuzhiyun dev_dbg(mlxfw_dev_dev(mlxfw_dev), MLXFW_PRFX fmt, ## __VA_ARGS__)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun enum mlxfw_fsm_state {
35*4882a593Smuzhiyun MLXFW_FSM_STATE_IDLE,
36*4882a593Smuzhiyun MLXFW_FSM_STATE_LOCKED,
37*4882a593Smuzhiyun MLXFW_FSM_STATE_INITIALIZE,
38*4882a593Smuzhiyun MLXFW_FSM_STATE_DOWNLOAD,
39*4882a593Smuzhiyun MLXFW_FSM_STATE_VERIFY,
40*4882a593Smuzhiyun MLXFW_FSM_STATE_APPLY,
41*4882a593Smuzhiyun MLXFW_FSM_STATE_ACTIVATE,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun enum mlxfw_fsm_state_err {
45*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_OK,
46*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_ERROR,
47*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_REJECTED_DIGEST_ERR,
48*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_REJECTED_NOT_APPLICABLE,
49*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_REJECTED_UNKNOWN_KEY,
50*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_REJECTED_AUTH_FAILED,
51*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_REJECTED_UNSIGNED,
52*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_REJECTED_KEY_NOT_APPLICABLE,
53*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_REJECTED_BAD_FORMAT,
54*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_BLOCKED_PENDING_RESET,
55*4882a593Smuzhiyun MLXFW_FSM_STATE_ERR_MAX,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun enum mlxfw_fsm_reactivate_status {
59*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_OK,
60*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_BUSY,
61*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_PROHIBITED_FW_VER_ERR,
62*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_FIRST_PAGE_COPY_FAILED,
63*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_FIRST_PAGE_ERASE_FAILED,
64*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_FIRST_PAGE_RESTORE_FAILED,
65*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_CANDIDATE_FW_DEACTIVATION_FAILED,
66*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_FW_ALREADY_ACTIVATED,
67*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_ERR_DEVICE_RESET_REQUIRED,
68*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_ERR_FW_PROGRAMMING_NEEDED,
69*4882a593Smuzhiyun MLXFW_FSM_REACTIVATE_STATUS_MAX,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct mlxfw_dev_ops {
73*4882a593Smuzhiyun int (*component_query)(struct mlxfw_dev *mlxfw_dev, u16 component_index,
74*4882a593Smuzhiyun u32 *p_max_size, u8 *p_align_bits,
75*4882a593Smuzhiyun u16 *p_max_write_size);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun int (*fsm_lock)(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun int (*fsm_component_update)(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
80*4882a593Smuzhiyun u16 component_index, u32 component_size);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun int (*fsm_block_download)(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
83*4882a593Smuzhiyun u8 *data, u16 size, u32 offset);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun int (*fsm_component_verify)(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
86*4882a593Smuzhiyun u16 component_index);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun int (*fsm_activate)(struct mlxfw_dev *mlxfw_dev, u32 fwhandle);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun int (*fsm_reactivate)(struct mlxfw_dev *mlxfw_dev, u8 *status);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun int (*fsm_query_state)(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
93*4882a593Smuzhiyun enum mlxfw_fsm_state *fsm_state,
94*4882a593Smuzhiyun enum mlxfw_fsm_state_err *fsm_state_err);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun void (*fsm_cancel)(struct mlxfw_dev *mlxfw_dev, u32 fwhandle);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun void (*fsm_release)(struct mlxfw_dev *mlxfw_dev, u32 fwhandle);
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #if IS_REACHABLE(CONFIG_MLXFW)
102*4882a593Smuzhiyun int mlxfw_firmware_flash(struct mlxfw_dev *mlxfw_dev,
103*4882a593Smuzhiyun const struct firmware *firmware,
104*4882a593Smuzhiyun struct netlink_ext_ack *extack);
105*4882a593Smuzhiyun #else
106*4882a593Smuzhiyun static inline
mlxfw_firmware_flash(struct mlxfw_dev * mlxfw_dev,const struct firmware * firmware,struct netlink_ext_ack * extack)107*4882a593Smuzhiyun int mlxfw_firmware_flash(struct mlxfw_dev *mlxfw_dev,
108*4882a593Smuzhiyun const struct firmware *firmware,
109*4882a593Smuzhiyun struct netlink_ext_ack *extack)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun return -EOPNOTSUPP;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun #endif
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #endif
116