1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <linux/errno.h>
34*4882a593Smuzhiyun #include <linux/if_ether.h>
35*4882a593Smuzhiyun #include <linux/if_vlan.h>
36*4882a593Smuzhiyun #include <linux/export.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include <linux/mlx4/cmd.h>
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #include "mlx4.h"
41*4882a593Smuzhiyun #include "mlx4_stats.h"
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define MLX4_MAC_VALID (1ull << 63)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define MLX4_VLAN_VALID (1u << 31)
46*4882a593Smuzhiyun #define MLX4_VLAN_MASK 0xfff
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
49*4882a593Smuzhiyun #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
50*4882a593Smuzhiyun #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
51*4882a593Smuzhiyun #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define MLX4_FLAG2_V_IGNORE_FCS_MASK BIT(1)
54*4882a593Smuzhiyun #define MLX4_FLAG2_V_USER_MTU_MASK BIT(5)
55*4882a593Smuzhiyun #define MLX4_FLAG2_V_USER_MAC_MASK BIT(6)
56*4882a593Smuzhiyun #define MLX4_FLAG_V_MTU_MASK BIT(0)
57*4882a593Smuzhiyun #define MLX4_FLAG_V_PPRX_MASK BIT(1)
58*4882a593Smuzhiyun #define MLX4_FLAG_V_PPTX_MASK BIT(2)
59*4882a593Smuzhiyun #define MLX4_IGNORE_FCS_MASK 0x1
60*4882a593Smuzhiyun #define MLX4_TC_MAX_NUMBER 8
61*4882a593Smuzhiyun
mlx4_init_mac_table(struct mlx4_dev * dev,struct mlx4_mac_table * table)62*4882a593Smuzhiyun void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun int i;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun mutex_init(&table->mutex);
67*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
68*4882a593Smuzhiyun table->entries[i] = 0;
69*4882a593Smuzhiyun table->refs[i] = 0;
70*4882a593Smuzhiyun table->is_dup[i] = false;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun table->max = 1 << dev->caps.log_num_macs;
73*4882a593Smuzhiyun table->total = 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
mlx4_init_vlan_table(struct mlx4_dev * dev,struct mlx4_vlan_table * table)76*4882a593Smuzhiyun void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun int i;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun mutex_init(&table->mutex);
81*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
82*4882a593Smuzhiyun table->entries[i] = 0;
83*4882a593Smuzhiyun table->refs[i] = 0;
84*4882a593Smuzhiyun table->is_dup[i] = false;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
87*4882a593Smuzhiyun table->total = 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
mlx4_init_roce_gid_table(struct mlx4_dev * dev,struct mlx4_roce_gid_table * table)90*4882a593Smuzhiyun void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
91*4882a593Smuzhiyun struct mlx4_roce_gid_table *table)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun int i;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun mutex_init(&table->mutex);
96*4882a593Smuzhiyun for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++)
97*4882a593Smuzhiyun memset(table->roce_gids[i].raw, 0, MLX4_ROCE_GID_ENTRY_SIZE);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
validate_index(struct mlx4_dev * dev,struct mlx4_mac_table * table,int index)100*4882a593Smuzhiyun static int validate_index(struct mlx4_dev *dev,
101*4882a593Smuzhiyun struct mlx4_mac_table *table, int index)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun int err = 0;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (index < 0 || index >= table->max || !table->entries[index]) {
106*4882a593Smuzhiyun mlx4_warn(dev, "No valid Mac entry for the given index\n");
107*4882a593Smuzhiyun err = -EINVAL;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun return err;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
find_index(struct mlx4_dev * dev,struct mlx4_mac_table * table,u64 mac)112*4882a593Smuzhiyun static int find_index(struct mlx4_dev *dev,
113*4882a593Smuzhiyun struct mlx4_mac_table *table, u64 mac)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun int i;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
118*4882a593Smuzhiyun if (table->refs[i] &&
119*4882a593Smuzhiyun (MLX4_MAC_MASK & mac) ==
120*4882a593Smuzhiyun (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
121*4882a593Smuzhiyun return i;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun /* Mac not found */
124*4882a593Smuzhiyun return -EINVAL;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
mlx4_set_port_mac_table(struct mlx4_dev * dev,u8 port,__be64 * entries)127*4882a593Smuzhiyun static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
128*4882a593Smuzhiyun __be64 *entries)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
131*4882a593Smuzhiyun u32 in_mod;
132*4882a593Smuzhiyun int err;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
135*4882a593Smuzhiyun if (IS_ERR(mailbox))
136*4882a593Smuzhiyun return PTR_ERR(mailbox);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
143*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
144*4882a593Smuzhiyun MLX4_CMD_NATIVE);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
147*4882a593Smuzhiyun return err;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
mlx4_find_cached_mac(struct mlx4_dev * dev,u8 port,u64 mac,int * idx)150*4882a593Smuzhiyun int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
153*4882a593Smuzhiyun struct mlx4_mac_table *table = &info->mac_table;
154*4882a593Smuzhiyun int i;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
157*4882a593Smuzhiyun if (!table->refs[i])
158*4882a593Smuzhiyun continue;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
161*4882a593Smuzhiyun *idx = i;
162*4882a593Smuzhiyun return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun return -ENOENT;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mlx4_find_cached_mac);
169*4882a593Smuzhiyun
mlx4_need_mf_bond(struct mlx4_dev * dev)170*4882a593Smuzhiyun static bool mlx4_need_mf_bond(struct mlx4_dev *dev)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun int i, num_eth_ports = 0;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (!mlx4_is_mfunc(dev))
175*4882a593Smuzhiyun return false;
176*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
177*4882a593Smuzhiyun ++num_eth_ports;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun return (num_eth_ports == 2) ? true : false;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
__mlx4_register_mac(struct mlx4_dev * dev,u8 port,u64 mac)182*4882a593Smuzhiyun int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
185*4882a593Smuzhiyun struct mlx4_mac_table *table = &info->mac_table;
186*4882a593Smuzhiyun int i, err = 0;
187*4882a593Smuzhiyun int free = -1;
188*4882a593Smuzhiyun int free_for_dup = -1;
189*4882a593Smuzhiyun bool dup = mlx4_is_mf_bonded(dev);
190*4882a593Smuzhiyun u8 dup_port = (port == 1) ? 2 : 1;
191*4882a593Smuzhiyun struct mlx4_mac_table *dup_table = &mlx4_priv(dev)->port[dup_port].mac_table;
192*4882a593Smuzhiyun bool need_mf_bond = mlx4_need_mf_bond(dev);
193*4882a593Smuzhiyun bool can_mf_bond = true;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d %s duplicate\n",
196*4882a593Smuzhiyun (unsigned long long)mac, port,
197*4882a593Smuzhiyun dup ? "with" : "without");
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun if (need_mf_bond) {
200*4882a593Smuzhiyun if (port == 1) {
201*4882a593Smuzhiyun mutex_lock(&table->mutex);
202*4882a593Smuzhiyun mutex_lock_nested(&dup_table->mutex, SINGLE_DEPTH_NESTING);
203*4882a593Smuzhiyun } else {
204*4882a593Smuzhiyun mutex_lock(&dup_table->mutex);
205*4882a593Smuzhiyun mutex_lock_nested(&table->mutex, SINGLE_DEPTH_NESTING);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun } else {
208*4882a593Smuzhiyun mutex_lock(&table->mutex);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (need_mf_bond) {
212*4882a593Smuzhiyun int index_at_port = -1;
213*4882a593Smuzhiyun int index_at_dup_port = -1;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
216*4882a593Smuzhiyun if (((MLX4_MAC_MASK & mac) == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))))
217*4882a593Smuzhiyun index_at_port = i;
218*4882a593Smuzhiyun if (((MLX4_MAC_MASK & mac) == (MLX4_MAC_MASK & be64_to_cpu(dup_table->entries[i]))))
219*4882a593Smuzhiyun index_at_dup_port = i;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /* check that same mac is not in the tables at different indices */
223*4882a593Smuzhiyun if ((index_at_port != index_at_dup_port) &&
224*4882a593Smuzhiyun (index_at_port >= 0) &&
225*4882a593Smuzhiyun (index_at_dup_port >= 0))
226*4882a593Smuzhiyun can_mf_bond = false;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /* If the mac is already in the primary table, the slot must be
229*4882a593Smuzhiyun * available in the duplicate table as well.
230*4882a593Smuzhiyun */
231*4882a593Smuzhiyun if (index_at_port >= 0 && index_at_dup_port < 0 &&
232*4882a593Smuzhiyun dup_table->refs[index_at_port]) {
233*4882a593Smuzhiyun can_mf_bond = false;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun /* If the mac is already in the duplicate table, check that the
236*4882a593Smuzhiyun * corresponding index is not occupied in the primary table, or
237*4882a593Smuzhiyun * the primary table already contains the mac at the same index.
238*4882a593Smuzhiyun * Otherwise, you cannot bond (primary contains a different mac
239*4882a593Smuzhiyun * at that index).
240*4882a593Smuzhiyun */
241*4882a593Smuzhiyun if (index_at_dup_port >= 0) {
242*4882a593Smuzhiyun if (!table->refs[index_at_dup_port] ||
243*4882a593Smuzhiyun ((MLX4_MAC_MASK & mac) == (MLX4_MAC_MASK & be64_to_cpu(table->entries[index_at_dup_port]))))
244*4882a593Smuzhiyun free_for_dup = index_at_dup_port;
245*4882a593Smuzhiyun else
246*4882a593Smuzhiyun can_mf_bond = false;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
251*4882a593Smuzhiyun if (!table->refs[i]) {
252*4882a593Smuzhiyun if (free < 0)
253*4882a593Smuzhiyun free = i;
254*4882a593Smuzhiyun if (free_for_dup < 0 && need_mf_bond && can_mf_bond) {
255*4882a593Smuzhiyun if (!dup_table->refs[i])
256*4882a593Smuzhiyun free_for_dup = i;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun continue;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun if ((MLX4_MAC_MASK & mac) ==
262*4882a593Smuzhiyun (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
263*4882a593Smuzhiyun /* MAC already registered, increment ref count */
264*4882a593Smuzhiyun err = i;
265*4882a593Smuzhiyun ++table->refs[i];
266*4882a593Smuzhiyun if (dup) {
267*4882a593Smuzhiyun u64 dup_mac = MLX4_MAC_MASK & be64_to_cpu(dup_table->entries[i]);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun if (dup_mac != mac || !dup_table->is_dup[i]) {
270*4882a593Smuzhiyun mlx4_warn(dev, "register mac: expect duplicate mac 0x%llx on port %d index %d\n",
271*4882a593Smuzhiyun mac, dup_port, i);
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun goto out;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun if (need_mf_bond && (free_for_dup < 0)) {
279*4882a593Smuzhiyun if (dup) {
280*4882a593Smuzhiyun mlx4_warn(dev, "Fail to allocate duplicate MAC table entry\n");
281*4882a593Smuzhiyun mlx4_warn(dev, "High Availability for virtual functions may not work as expected\n");
282*4882a593Smuzhiyun dup = false;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun can_mf_bond = false;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun if (need_mf_bond && can_mf_bond)
288*4882a593Smuzhiyun free = free_for_dup;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun mlx4_dbg(dev, "Free MAC index is %d\n", free);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun if (table->total == table->max) {
293*4882a593Smuzhiyun /* No free mac entries */
294*4882a593Smuzhiyun err = -ENOSPC;
295*4882a593Smuzhiyun goto out;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* Register new MAC */
299*4882a593Smuzhiyun table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun err = mlx4_set_port_mac_table(dev, port, table->entries);
302*4882a593Smuzhiyun if (unlikely(err)) {
303*4882a593Smuzhiyun mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
304*4882a593Smuzhiyun (unsigned long long) mac);
305*4882a593Smuzhiyun table->entries[free] = 0;
306*4882a593Smuzhiyun goto out;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun table->refs[free] = 1;
309*4882a593Smuzhiyun table->is_dup[free] = false;
310*4882a593Smuzhiyun ++table->total;
311*4882a593Smuzhiyun if (dup) {
312*4882a593Smuzhiyun dup_table->refs[free] = 0;
313*4882a593Smuzhiyun dup_table->is_dup[free] = true;
314*4882a593Smuzhiyun dup_table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun err = mlx4_set_port_mac_table(dev, dup_port, dup_table->entries);
317*4882a593Smuzhiyun if (unlikely(err)) {
318*4882a593Smuzhiyun mlx4_warn(dev, "Failed adding duplicate mac: 0x%llx\n", mac);
319*4882a593Smuzhiyun dup_table->is_dup[free] = false;
320*4882a593Smuzhiyun dup_table->entries[free] = 0;
321*4882a593Smuzhiyun goto out;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun ++dup_table->total;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun err = free;
326*4882a593Smuzhiyun out:
327*4882a593Smuzhiyun if (need_mf_bond) {
328*4882a593Smuzhiyun if (port == 2) {
329*4882a593Smuzhiyun mutex_unlock(&table->mutex);
330*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
331*4882a593Smuzhiyun } else {
332*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
333*4882a593Smuzhiyun mutex_unlock(&table->mutex);
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun } else {
336*4882a593Smuzhiyun mutex_unlock(&table->mutex);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun return err;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__mlx4_register_mac);
341*4882a593Smuzhiyun
mlx4_register_mac(struct mlx4_dev * dev,u8 port,u64 mac)342*4882a593Smuzhiyun int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
343*4882a593Smuzhiyun {
344*4882a593Smuzhiyun u64 out_param = 0;
345*4882a593Smuzhiyun int err = -EINVAL;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun if (mlx4_is_mfunc(dev)) {
348*4882a593Smuzhiyun if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
349*4882a593Smuzhiyun err = mlx4_cmd_imm(dev, mac, &out_param,
350*4882a593Smuzhiyun ((u32) port) << 8 | (u32) RES_MAC,
351*4882a593Smuzhiyun RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
352*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun if (err && err == -EINVAL && mlx4_is_slave(dev)) {
355*4882a593Smuzhiyun /* retry using old REG_MAC format */
356*4882a593Smuzhiyun set_param_l(&out_param, port);
357*4882a593Smuzhiyun err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
358*4882a593Smuzhiyun RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
359*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
360*4882a593Smuzhiyun if (!err)
361*4882a593Smuzhiyun dev->flags |= MLX4_FLAG_OLD_REG_MAC;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun if (err)
364*4882a593Smuzhiyun return err;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun return get_param_l(&out_param);
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun return __mlx4_register_mac(dev, port, mac);
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mlx4_register_mac);
371*4882a593Smuzhiyun
mlx4_get_base_qpn(struct mlx4_dev * dev,u8 port)372*4882a593Smuzhiyun int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
375*4882a593Smuzhiyun (port - 1) * (1 << dev->caps.log_num_macs);
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mlx4_get_base_qpn);
378*4882a593Smuzhiyun
__mlx4_unregister_mac(struct mlx4_dev * dev,u8 port,u64 mac)379*4882a593Smuzhiyun void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun struct mlx4_port_info *info;
382*4882a593Smuzhiyun struct mlx4_mac_table *table;
383*4882a593Smuzhiyun int index;
384*4882a593Smuzhiyun bool dup = mlx4_is_mf_bonded(dev);
385*4882a593Smuzhiyun u8 dup_port = (port == 1) ? 2 : 1;
386*4882a593Smuzhiyun struct mlx4_mac_table *dup_table = &mlx4_priv(dev)->port[dup_port].mac_table;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (port < 1 || port > dev->caps.num_ports) {
389*4882a593Smuzhiyun mlx4_warn(dev, "invalid port number (%d), aborting...\n", port);
390*4882a593Smuzhiyun return;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun info = &mlx4_priv(dev)->port[port];
393*4882a593Smuzhiyun table = &info->mac_table;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun if (dup) {
396*4882a593Smuzhiyun if (port == 1) {
397*4882a593Smuzhiyun mutex_lock(&table->mutex);
398*4882a593Smuzhiyun mutex_lock_nested(&dup_table->mutex, SINGLE_DEPTH_NESTING);
399*4882a593Smuzhiyun } else {
400*4882a593Smuzhiyun mutex_lock(&dup_table->mutex);
401*4882a593Smuzhiyun mutex_lock_nested(&table->mutex, SINGLE_DEPTH_NESTING);
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun } else {
404*4882a593Smuzhiyun mutex_lock(&table->mutex);
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun index = find_index(dev, table, mac);
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun if (validate_index(dev, table, index))
410*4882a593Smuzhiyun goto out;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun if (--table->refs[index] || table->is_dup[index]) {
413*4882a593Smuzhiyun mlx4_dbg(dev, "Have more references for index %d, no need to modify mac table\n",
414*4882a593Smuzhiyun index);
415*4882a593Smuzhiyun if (!table->refs[index])
416*4882a593Smuzhiyun dup_table->is_dup[index] = false;
417*4882a593Smuzhiyun goto out;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun table->entries[index] = 0;
421*4882a593Smuzhiyun if (mlx4_set_port_mac_table(dev, port, table->entries))
422*4882a593Smuzhiyun mlx4_warn(dev, "Fail to set mac in port %d during unregister\n", port);
423*4882a593Smuzhiyun --table->total;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (dup) {
426*4882a593Smuzhiyun dup_table->is_dup[index] = false;
427*4882a593Smuzhiyun if (dup_table->refs[index])
428*4882a593Smuzhiyun goto out;
429*4882a593Smuzhiyun dup_table->entries[index] = 0;
430*4882a593Smuzhiyun if (mlx4_set_port_mac_table(dev, dup_port, dup_table->entries))
431*4882a593Smuzhiyun mlx4_warn(dev, "Fail to set mac in duplicate port %d during unregister\n", dup_port);
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun --table->total;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun out:
436*4882a593Smuzhiyun if (dup) {
437*4882a593Smuzhiyun if (port == 2) {
438*4882a593Smuzhiyun mutex_unlock(&table->mutex);
439*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
440*4882a593Smuzhiyun } else {
441*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
442*4882a593Smuzhiyun mutex_unlock(&table->mutex);
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun } else {
445*4882a593Smuzhiyun mutex_unlock(&table->mutex);
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
449*4882a593Smuzhiyun
mlx4_unregister_mac(struct mlx4_dev * dev,u8 port,u64 mac)450*4882a593Smuzhiyun void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun u64 out_param = 0;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (mlx4_is_mfunc(dev)) {
455*4882a593Smuzhiyun if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
456*4882a593Smuzhiyun (void) mlx4_cmd_imm(dev, mac, &out_param,
457*4882a593Smuzhiyun ((u32) port) << 8 | (u32) RES_MAC,
458*4882a593Smuzhiyun RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
459*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
460*4882a593Smuzhiyun } else {
461*4882a593Smuzhiyun /* use old unregister mac format */
462*4882a593Smuzhiyun set_param_l(&out_param, port);
463*4882a593Smuzhiyun (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
464*4882a593Smuzhiyun RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
465*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun return;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun __mlx4_unregister_mac(dev, port, mac);
470*4882a593Smuzhiyun return;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
473*4882a593Smuzhiyun
__mlx4_replace_mac(struct mlx4_dev * dev,u8 port,int qpn,u64 new_mac)474*4882a593Smuzhiyun int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
477*4882a593Smuzhiyun struct mlx4_mac_table *table = &info->mac_table;
478*4882a593Smuzhiyun int index = qpn - info->base_qpn;
479*4882a593Smuzhiyun int err = 0;
480*4882a593Smuzhiyun bool dup = mlx4_is_mf_bonded(dev);
481*4882a593Smuzhiyun u8 dup_port = (port == 1) ? 2 : 1;
482*4882a593Smuzhiyun struct mlx4_mac_table *dup_table = &mlx4_priv(dev)->port[dup_port].mac_table;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun /* CX1 doesn't support multi-functions */
485*4882a593Smuzhiyun if (dup) {
486*4882a593Smuzhiyun if (port == 1) {
487*4882a593Smuzhiyun mutex_lock(&table->mutex);
488*4882a593Smuzhiyun mutex_lock_nested(&dup_table->mutex, SINGLE_DEPTH_NESTING);
489*4882a593Smuzhiyun } else {
490*4882a593Smuzhiyun mutex_lock(&dup_table->mutex);
491*4882a593Smuzhiyun mutex_lock_nested(&table->mutex, SINGLE_DEPTH_NESTING);
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun } else {
494*4882a593Smuzhiyun mutex_lock(&table->mutex);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun err = validate_index(dev, table, index);
498*4882a593Smuzhiyun if (err)
499*4882a593Smuzhiyun goto out;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun err = mlx4_set_port_mac_table(dev, port, table->entries);
504*4882a593Smuzhiyun if (unlikely(err)) {
505*4882a593Smuzhiyun mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
506*4882a593Smuzhiyun (unsigned long long) new_mac);
507*4882a593Smuzhiyun table->entries[index] = 0;
508*4882a593Smuzhiyun } else {
509*4882a593Smuzhiyun if (dup) {
510*4882a593Smuzhiyun dup_table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun err = mlx4_set_port_mac_table(dev, dup_port, dup_table->entries);
513*4882a593Smuzhiyun if (unlikely(err)) {
514*4882a593Smuzhiyun mlx4_err(dev, "Failed adding duplicate MAC: 0x%llx\n",
515*4882a593Smuzhiyun (unsigned long long)new_mac);
516*4882a593Smuzhiyun dup_table->entries[index] = 0;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun out:
521*4882a593Smuzhiyun if (dup) {
522*4882a593Smuzhiyun if (port == 2) {
523*4882a593Smuzhiyun mutex_unlock(&table->mutex);
524*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
525*4882a593Smuzhiyun } else {
526*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
527*4882a593Smuzhiyun mutex_unlock(&table->mutex);
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun } else {
530*4882a593Smuzhiyun mutex_unlock(&table->mutex);
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun return err;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(__mlx4_replace_mac);
535*4882a593Smuzhiyun
mlx4_set_port_vlan_table(struct mlx4_dev * dev,u8 port,__be32 * entries)536*4882a593Smuzhiyun static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
537*4882a593Smuzhiyun __be32 *entries)
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
540*4882a593Smuzhiyun u32 in_mod;
541*4882a593Smuzhiyun int err;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
544*4882a593Smuzhiyun if (IS_ERR(mailbox))
545*4882a593Smuzhiyun return PTR_ERR(mailbox);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
548*4882a593Smuzhiyun in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
549*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
550*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
551*4882a593Smuzhiyun MLX4_CMD_NATIVE);
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun return err;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
mlx4_find_cached_vlan(struct mlx4_dev * dev,u8 port,u16 vid,int * idx)558*4882a593Smuzhiyun int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
561*4882a593Smuzhiyun int i;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
564*4882a593Smuzhiyun if (table->refs[i] &&
565*4882a593Smuzhiyun (vid == (MLX4_VLAN_MASK &
566*4882a593Smuzhiyun be32_to_cpu(table->entries[i])))) {
567*4882a593Smuzhiyun /* VLAN already registered, increase reference count */
568*4882a593Smuzhiyun *idx = i;
569*4882a593Smuzhiyun return 0;
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun return -ENOENT;
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
576*4882a593Smuzhiyun
__mlx4_register_vlan(struct mlx4_dev * dev,u8 port,u16 vlan,int * index)577*4882a593Smuzhiyun int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
578*4882a593Smuzhiyun int *index)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
581*4882a593Smuzhiyun int i, err = 0;
582*4882a593Smuzhiyun int free = -1;
583*4882a593Smuzhiyun int free_for_dup = -1;
584*4882a593Smuzhiyun bool dup = mlx4_is_mf_bonded(dev);
585*4882a593Smuzhiyun u8 dup_port = (port == 1) ? 2 : 1;
586*4882a593Smuzhiyun struct mlx4_vlan_table *dup_table = &mlx4_priv(dev)->port[dup_port].vlan_table;
587*4882a593Smuzhiyun bool need_mf_bond = mlx4_need_mf_bond(dev);
588*4882a593Smuzhiyun bool can_mf_bond = true;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun mlx4_dbg(dev, "Registering VLAN: %d for port %d %s duplicate\n",
591*4882a593Smuzhiyun vlan, port,
592*4882a593Smuzhiyun dup ? "with" : "without");
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun if (need_mf_bond) {
595*4882a593Smuzhiyun if (port == 1) {
596*4882a593Smuzhiyun mutex_lock(&table->mutex);
597*4882a593Smuzhiyun mutex_lock_nested(&dup_table->mutex, SINGLE_DEPTH_NESTING);
598*4882a593Smuzhiyun } else {
599*4882a593Smuzhiyun mutex_lock(&dup_table->mutex);
600*4882a593Smuzhiyun mutex_lock_nested(&table->mutex, SINGLE_DEPTH_NESTING);
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun } else {
603*4882a593Smuzhiyun mutex_lock(&table->mutex);
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun if (table->total == table->max) {
607*4882a593Smuzhiyun /* No free vlan entries */
608*4882a593Smuzhiyun err = -ENOSPC;
609*4882a593Smuzhiyun goto out;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun if (need_mf_bond) {
613*4882a593Smuzhiyun int index_at_port = -1;
614*4882a593Smuzhiyun int index_at_dup_port = -1;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
617*4882a593Smuzhiyun if (vlan == (MLX4_VLAN_MASK & be32_to_cpu(table->entries[i])))
618*4882a593Smuzhiyun index_at_port = i;
619*4882a593Smuzhiyun if (vlan == (MLX4_VLAN_MASK & be32_to_cpu(dup_table->entries[i])))
620*4882a593Smuzhiyun index_at_dup_port = i;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun /* check that same vlan is not in the tables at different indices */
623*4882a593Smuzhiyun if ((index_at_port != index_at_dup_port) &&
624*4882a593Smuzhiyun (index_at_port >= 0) &&
625*4882a593Smuzhiyun (index_at_dup_port >= 0))
626*4882a593Smuzhiyun can_mf_bond = false;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun /* If the vlan is already in the primary table, the slot must be
629*4882a593Smuzhiyun * available in the duplicate table as well.
630*4882a593Smuzhiyun */
631*4882a593Smuzhiyun if (index_at_port >= 0 && index_at_dup_port < 0 &&
632*4882a593Smuzhiyun dup_table->refs[index_at_port]) {
633*4882a593Smuzhiyun can_mf_bond = false;
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun /* If the vlan is already in the duplicate table, check that the
636*4882a593Smuzhiyun * corresponding index is not occupied in the primary table, or
637*4882a593Smuzhiyun * the primary table already contains the vlan at the same index.
638*4882a593Smuzhiyun * Otherwise, you cannot bond (primary contains a different vlan
639*4882a593Smuzhiyun * at that index).
640*4882a593Smuzhiyun */
641*4882a593Smuzhiyun if (index_at_dup_port >= 0) {
642*4882a593Smuzhiyun if (!table->refs[index_at_dup_port] ||
643*4882a593Smuzhiyun (vlan == (MLX4_VLAN_MASK & be32_to_cpu(dup_table->entries[index_at_dup_port]))))
644*4882a593Smuzhiyun free_for_dup = index_at_dup_port;
645*4882a593Smuzhiyun else
646*4882a593Smuzhiyun can_mf_bond = false;
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
651*4882a593Smuzhiyun if (!table->refs[i]) {
652*4882a593Smuzhiyun if (free < 0)
653*4882a593Smuzhiyun free = i;
654*4882a593Smuzhiyun if (free_for_dup < 0 && need_mf_bond && can_mf_bond) {
655*4882a593Smuzhiyun if (!dup_table->refs[i])
656*4882a593Smuzhiyun free_for_dup = i;
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun }
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun if ((table->refs[i] || table->is_dup[i]) &&
661*4882a593Smuzhiyun (vlan == (MLX4_VLAN_MASK &
662*4882a593Smuzhiyun be32_to_cpu(table->entries[i])))) {
663*4882a593Smuzhiyun /* Vlan already registered, increase references count */
664*4882a593Smuzhiyun mlx4_dbg(dev, "vlan %u is already registered.\n", vlan);
665*4882a593Smuzhiyun *index = i;
666*4882a593Smuzhiyun ++table->refs[i];
667*4882a593Smuzhiyun if (dup) {
668*4882a593Smuzhiyun u16 dup_vlan = MLX4_VLAN_MASK & be32_to_cpu(dup_table->entries[i]);
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun if (dup_vlan != vlan || !dup_table->is_dup[i]) {
671*4882a593Smuzhiyun mlx4_warn(dev, "register vlan: expected duplicate vlan %u on port %d index %d\n",
672*4882a593Smuzhiyun vlan, dup_port, i);
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun goto out;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun if (need_mf_bond && (free_for_dup < 0)) {
680*4882a593Smuzhiyun if (dup) {
681*4882a593Smuzhiyun mlx4_warn(dev, "Fail to allocate duplicate VLAN table entry\n");
682*4882a593Smuzhiyun mlx4_warn(dev, "High Availability for virtual functions may not work as expected\n");
683*4882a593Smuzhiyun dup = false;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun can_mf_bond = false;
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun if (need_mf_bond && can_mf_bond)
689*4882a593Smuzhiyun free = free_for_dup;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun if (free < 0) {
692*4882a593Smuzhiyun err = -ENOMEM;
693*4882a593Smuzhiyun goto out;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun /* Register new VLAN */
697*4882a593Smuzhiyun table->refs[free] = 1;
698*4882a593Smuzhiyun table->is_dup[free] = false;
699*4882a593Smuzhiyun table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun err = mlx4_set_port_vlan_table(dev, port, table->entries);
702*4882a593Smuzhiyun if (unlikely(err)) {
703*4882a593Smuzhiyun mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
704*4882a593Smuzhiyun table->refs[free] = 0;
705*4882a593Smuzhiyun table->entries[free] = 0;
706*4882a593Smuzhiyun goto out;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun ++table->total;
709*4882a593Smuzhiyun if (dup) {
710*4882a593Smuzhiyun dup_table->refs[free] = 0;
711*4882a593Smuzhiyun dup_table->is_dup[free] = true;
712*4882a593Smuzhiyun dup_table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun err = mlx4_set_port_vlan_table(dev, dup_port, dup_table->entries);
715*4882a593Smuzhiyun if (unlikely(err)) {
716*4882a593Smuzhiyun mlx4_warn(dev, "Failed adding duplicate vlan: %u\n", vlan);
717*4882a593Smuzhiyun dup_table->is_dup[free] = false;
718*4882a593Smuzhiyun dup_table->entries[free] = 0;
719*4882a593Smuzhiyun goto out;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun ++dup_table->total;
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun *index = free;
725*4882a593Smuzhiyun out:
726*4882a593Smuzhiyun if (need_mf_bond) {
727*4882a593Smuzhiyun if (port == 2) {
728*4882a593Smuzhiyun mutex_unlock(&table->mutex);
729*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
730*4882a593Smuzhiyun } else {
731*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
732*4882a593Smuzhiyun mutex_unlock(&table->mutex);
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun } else {
735*4882a593Smuzhiyun mutex_unlock(&table->mutex);
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun return err;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun
mlx4_register_vlan(struct mlx4_dev * dev,u8 port,u16 vlan,int * index)740*4882a593Smuzhiyun int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
741*4882a593Smuzhiyun {
742*4882a593Smuzhiyun u64 out_param = 0;
743*4882a593Smuzhiyun int err;
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun if (vlan > 4095)
746*4882a593Smuzhiyun return -EINVAL;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun if (mlx4_is_mfunc(dev)) {
749*4882a593Smuzhiyun err = mlx4_cmd_imm(dev, vlan, &out_param,
750*4882a593Smuzhiyun ((u32) port) << 8 | (u32) RES_VLAN,
751*4882a593Smuzhiyun RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
752*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
753*4882a593Smuzhiyun if (!err)
754*4882a593Smuzhiyun *index = get_param_l(&out_param);
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun return err;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun return __mlx4_register_vlan(dev, port, vlan, index);
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mlx4_register_vlan);
761*4882a593Smuzhiyun
__mlx4_unregister_vlan(struct mlx4_dev * dev,u8 port,u16 vlan)762*4882a593Smuzhiyun void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
765*4882a593Smuzhiyun int index;
766*4882a593Smuzhiyun bool dup = mlx4_is_mf_bonded(dev);
767*4882a593Smuzhiyun u8 dup_port = (port == 1) ? 2 : 1;
768*4882a593Smuzhiyun struct mlx4_vlan_table *dup_table = &mlx4_priv(dev)->port[dup_port].vlan_table;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun if (dup) {
771*4882a593Smuzhiyun if (port == 1) {
772*4882a593Smuzhiyun mutex_lock(&table->mutex);
773*4882a593Smuzhiyun mutex_lock_nested(&dup_table->mutex, SINGLE_DEPTH_NESTING);
774*4882a593Smuzhiyun } else {
775*4882a593Smuzhiyun mutex_lock(&dup_table->mutex);
776*4882a593Smuzhiyun mutex_lock_nested(&table->mutex, SINGLE_DEPTH_NESTING);
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun } else {
779*4882a593Smuzhiyun mutex_lock(&table->mutex);
780*4882a593Smuzhiyun }
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun if (mlx4_find_cached_vlan(dev, port, vlan, &index)) {
783*4882a593Smuzhiyun mlx4_warn(dev, "vlan 0x%x is not in the vlan table\n", vlan);
784*4882a593Smuzhiyun goto out;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun if (index < MLX4_VLAN_REGULAR) {
788*4882a593Smuzhiyun mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
789*4882a593Smuzhiyun goto out;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun if (--table->refs[index] || table->is_dup[index]) {
793*4882a593Smuzhiyun mlx4_dbg(dev, "Have %d more references for index %d, no need to modify vlan table\n",
794*4882a593Smuzhiyun table->refs[index], index);
795*4882a593Smuzhiyun if (!table->refs[index])
796*4882a593Smuzhiyun dup_table->is_dup[index] = false;
797*4882a593Smuzhiyun goto out;
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun table->entries[index] = 0;
800*4882a593Smuzhiyun if (mlx4_set_port_vlan_table(dev, port, table->entries))
801*4882a593Smuzhiyun mlx4_warn(dev, "Fail to set vlan in port %d during unregister\n", port);
802*4882a593Smuzhiyun --table->total;
803*4882a593Smuzhiyun if (dup) {
804*4882a593Smuzhiyun dup_table->is_dup[index] = false;
805*4882a593Smuzhiyun if (dup_table->refs[index])
806*4882a593Smuzhiyun goto out;
807*4882a593Smuzhiyun dup_table->entries[index] = 0;
808*4882a593Smuzhiyun if (mlx4_set_port_vlan_table(dev, dup_port, dup_table->entries))
809*4882a593Smuzhiyun mlx4_warn(dev, "Fail to set vlan in duplicate port %d during unregister\n", dup_port);
810*4882a593Smuzhiyun --dup_table->total;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun out:
813*4882a593Smuzhiyun if (dup) {
814*4882a593Smuzhiyun if (port == 2) {
815*4882a593Smuzhiyun mutex_unlock(&table->mutex);
816*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
817*4882a593Smuzhiyun } else {
818*4882a593Smuzhiyun mutex_unlock(&dup_table->mutex);
819*4882a593Smuzhiyun mutex_unlock(&table->mutex);
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun } else {
822*4882a593Smuzhiyun mutex_unlock(&table->mutex);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun
mlx4_unregister_vlan(struct mlx4_dev * dev,u8 port,u16 vlan)826*4882a593Smuzhiyun void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
827*4882a593Smuzhiyun {
828*4882a593Smuzhiyun u64 out_param = 0;
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun if (mlx4_is_mfunc(dev)) {
831*4882a593Smuzhiyun (void) mlx4_cmd_imm(dev, vlan, &out_param,
832*4882a593Smuzhiyun ((u32) port) << 8 | (u32) RES_VLAN,
833*4882a593Smuzhiyun RES_OP_RESERVE_AND_MAP,
834*4882a593Smuzhiyun MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
835*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
836*4882a593Smuzhiyun return;
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun __mlx4_unregister_vlan(dev, port, vlan);
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
841*4882a593Smuzhiyun
mlx4_bond_mac_table(struct mlx4_dev * dev)842*4882a593Smuzhiyun int mlx4_bond_mac_table(struct mlx4_dev *dev)
843*4882a593Smuzhiyun {
844*4882a593Smuzhiyun struct mlx4_mac_table *t1 = &mlx4_priv(dev)->port[1].mac_table;
845*4882a593Smuzhiyun struct mlx4_mac_table *t2 = &mlx4_priv(dev)->port[2].mac_table;
846*4882a593Smuzhiyun int ret = 0;
847*4882a593Smuzhiyun int i;
848*4882a593Smuzhiyun bool update1 = false;
849*4882a593Smuzhiyun bool update2 = false;
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun mutex_lock(&t1->mutex);
852*4882a593Smuzhiyun mutex_lock(&t2->mutex);
853*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
854*4882a593Smuzhiyun if ((t1->entries[i] != t2->entries[i]) &&
855*4882a593Smuzhiyun t1->entries[i] && t2->entries[i]) {
856*4882a593Smuzhiyun mlx4_warn(dev, "can't duplicate entry %d in mac table\n", i);
857*4882a593Smuzhiyun ret = -EINVAL;
858*4882a593Smuzhiyun goto unlock;
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun }
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
863*4882a593Smuzhiyun if (t1->entries[i] && !t2->entries[i]) {
864*4882a593Smuzhiyun t2->entries[i] = t1->entries[i];
865*4882a593Smuzhiyun t2->is_dup[i] = true;
866*4882a593Smuzhiyun update2 = true;
867*4882a593Smuzhiyun } else if (!t1->entries[i] && t2->entries[i]) {
868*4882a593Smuzhiyun t1->entries[i] = t2->entries[i];
869*4882a593Smuzhiyun t1->is_dup[i] = true;
870*4882a593Smuzhiyun update1 = true;
871*4882a593Smuzhiyun } else if (t1->entries[i] && t2->entries[i]) {
872*4882a593Smuzhiyun t1->is_dup[i] = true;
873*4882a593Smuzhiyun t2->is_dup[i] = true;
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun }
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun if (update1) {
878*4882a593Smuzhiyun ret = mlx4_set_port_mac_table(dev, 1, t1->entries);
879*4882a593Smuzhiyun if (ret)
880*4882a593Smuzhiyun mlx4_warn(dev, "failed to set MAC table for port 1 (%d)\n", ret);
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun if (!ret && update2) {
883*4882a593Smuzhiyun ret = mlx4_set_port_mac_table(dev, 2, t2->entries);
884*4882a593Smuzhiyun if (ret)
885*4882a593Smuzhiyun mlx4_warn(dev, "failed to set MAC table for port 2 (%d)\n", ret);
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun if (ret)
889*4882a593Smuzhiyun mlx4_warn(dev, "failed to create mirror MAC tables\n");
890*4882a593Smuzhiyun unlock:
891*4882a593Smuzhiyun mutex_unlock(&t2->mutex);
892*4882a593Smuzhiyun mutex_unlock(&t1->mutex);
893*4882a593Smuzhiyun return ret;
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun
mlx4_unbond_mac_table(struct mlx4_dev * dev)896*4882a593Smuzhiyun int mlx4_unbond_mac_table(struct mlx4_dev *dev)
897*4882a593Smuzhiyun {
898*4882a593Smuzhiyun struct mlx4_mac_table *t1 = &mlx4_priv(dev)->port[1].mac_table;
899*4882a593Smuzhiyun struct mlx4_mac_table *t2 = &mlx4_priv(dev)->port[2].mac_table;
900*4882a593Smuzhiyun int ret = 0;
901*4882a593Smuzhiyun int ret1;
902*4882a593Smuzhiyun int i;
903*4882a593Smuzhiyun bool update1 = false;
904*4882a593Smuzhiyun bool update2 = false;
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun mutex_lock(&t1->mutex);
907*4882a593Smuzhiyun mutex_lock(&t2->mutex);
908*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
909*4882a593Smuzhiyun if (t1->entries[i] != t2->entries[i]) {
910*4882a593Smuzhiyun mlx4_warn(dev, "mac table is in an unexpected state when trying to unbond\n");
911*4882a593Smuzhiyun ret = -EINVAL;
912*4882a593Smuzhiyun goto unlock;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
917*4882a593Smuzhiyun if (!t1->entries[i])
918*4882a593Smuzhiyun continue;
919*4882a593Smuzhiyun t1->is_dup[i] = false;
920*4882a593Smuzhiyun if (!t1->refs[i]) {
921*4882a593Smuzhiyun t1->entries[i] = 0;
922*4882a593Smuzhiyun update1 = true;
923*4882a593Smuzhiyun }
924*4882a593Smuzhiyun t2->is_dup[i] = false;
925*4882a593Smuzhiyun if (!t2->refs[i]) {
926*4882a593Smuzhiyun t2->entries[i] = 0;
927*4882a593Smuzhiyun update2 = true;
928*4882a593Smuzhiyun }
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun if (update1) {
932*4882a593Smuzhiyun ret = mlx4_set_port_mac_table(dev, 1, t1->entries);
933*4882a593Smuzhiyun if (ret)
934*4882a593Smuzhiyun mlx4_warn(dev, "failed to unmirror MAC tables for port 1(%d)\n", ret);
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun if (update2) {
937*4882a593Smuzhiyun ret1 = mlx4_set_port_mac_table(dev, 2, t2->entries);
938*4882a593Smuzhiyun if (ret1) {
939*4882a593Smuzhiyun mlx4_warn(dev, "failed to unmirror MAC tables for port 2(%d)\n", ret1);
940*4882a593Smuzhiyun ret = ret1;
941*4882a593Smuzhiyun }
942*4882a593Smuzhiyun }
943*4882a593Smuzhiyun unlock:
944*4882a593Smuzhiyun mutex_unlock(&t2->mutex);
945*4882a593Smuzhiyun mutex_unlock(&t1->mutex);
946*4882a593Smuzhiyun return ret;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun
mlx4_bond_vlan_table(struct mlx4_dev * dev)949*4882a593Smuzhiyun int mlx4_bond_vlan_table(struct mlx4_dev *dev)
950*4882a593Smuzhiyun {
951*4882a593Smuzhiyun struct mlx4_vlan_table *t1 = &mlx4_priv(dev)->port[1].vlan_table;
952*4882a593Smuzhiyun struct mlx4_vlan_table *t2 = &mlx4_priv(dev)->port[2].vlan_table;
953*4882a593Smuzhiyun int ret = 0;
954*4882a593Smuzhiyun int i;
955*4882a593Smuzhiyun bool update1 = false;
956*4882a593Smuzhiyun bool update2 = false;
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun mutex_lock(&t1->mutex);
959*4882a593Smuzhiyun mutex_lock(&t2->mutex);
960*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
961*4882a593Smuzhiyun if ((t1->entries[i] != t2->entries[i]) &&
962*4882a593Smuzhiyun t1->entries[i] && t2->entries[i]) {
963*4882a593Smuzhiyun mlx4_warn(dev, "can't duplicate entry %d in vlan table\n", i);
964*4882a593Smuzhiyun ret = -EINVAL;
965*4882a593Smuzhiyun goto unlock;
966*4882a593Smuzhiyun }
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
970*4882a593Smuzhiyun if (t1->entries[i] && !t2->entries[i]) {
971*4882a593Smuzhiyun t2->entries[i] = t1->entries[i];
972*4882a593Smuzhiyun t2->is_dup[i] = true;
973*4882a593Smuzhiyun update2 = true;
974*4882a593Smuzhiyun } else if (!t1->entries[i] && t2->entries[i]) {
975*4882a593Smuzhiyun t1->entries[i] = t2->entries[i];
976*4882a593Smuzhiyun t1->is_dup[i] = true;
977*4882a593Smuzhiyun update1 = true;
978*4882a593Smuzhiyun } else if (t1->entries[i] && t2->entries[i]) {
979*4882a593Smuzhiyun t1->is_dup[i] = true;
980*4882a593Smuzhiyun t2->is_dup[i] = true;
981*4882a593Smuzhiyun }
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun if (update1) {
985*4882a593Smuzhiyun ret = mlx4_set_port_vlan_table(dev, 1, t1->entries);
986*4882a593Smuzhiyun if (ret)
987*4882a593Smuzhiyun mlx4_warn(dev, "failed to set VLAN table for port 1 (%d)\n", ret);
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun if (!ret && update2) {
990*4882a593Smuzhiyun ret = mlx4_set_port_vlan_table(dev, 2, t2->entries);
991*4882a593Smuzhiyun if (ret)
992*4882a593Smuzhiyun mlx4_warn(dev, "failed to set VLAN table for port 2 (%d)\n", ret);
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun if (ret)
996*4882a593Smuzhiyun mlx4_warn(dev, "failed to create mirror VLAN tables\n");
997*4882a593Smuzhiyun unlock:
998*4882a593Smuzhiyun mutex_unlock(&t2->mutex);
999*4882a593Smuzhiyun mutex_unlock(&t1->mutex);
1000*4882a593Smuzhiyun return ret;
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun
mlx4_unbond_vlan_table(struct mlx4_dev * dev)1003*4882a593Smuzhiyun int mlx4_unbond_vlan_table(struct mlx4_dev *dev)
1004*4882a593Smuzhiyun {
1005*4882a593Smuzhiyun struct mlx4_vlan_table *t1 = &mlx4_priv(dev)->port[1].vlan_table;
1006*4882a593Smuzhiyun struct mlx4_vlan_table *t2 = &mlx4_priv(dev)->port[2].vlan_table;
1007*4882a593Smuzhiyun int ret = 0;
1008*4882a593Smuzhiyun int ret1;
1009*4882a593Smuzhiyun int i;
1010*4882a593Smuzhiyun bool update1 = false;
1011*4882a593Smuzhiyun bool update2 = false;
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun mutex_lock(&t1->mutex);
1014*4882a593Smuzhiyun mutex_lock(&t2->mutex);
1015*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
1016*4882a593Smuzhiyun if (t1->entries[i] != t2->entries[i]) {
1017*4882a593Smuzhiyun mlx4_warn(dev, "vlan table is in an unexpected state when trying to unbond\n");
1018*4882a593Smuzhiyun ret = -EINVAL;
1019*4882a593Smuzhiyun goto unlock;
1020*4882a593Smuzhiyun }
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
1024*4882a593Smuzhiyun if (!t1->entries[i])
1025*4882a593Smuzhiyun continue;
1026*4882a593Smuzhiyun t1->is_dup[i] = false;
1027*4882a593Smuzhiyun if (!t1->refs[i]) {
1028*4882a593Smuzhiyun t1->entries[i] = 0;
1029*4882a593Smuzhiyun update1 = true;
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun t2->is_dup[i] = false;
1032*4882a593Smuzhiyun if (!t2->refs[i]) {
1033*4882a593Smuzhiyun t2->entries[i] = 0;
1034*4882a593Smuzhiyun update2 = true;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun if (update1) {
1039*4882a593Smuzhiyun ret = mlx4_set_port_vlan_table(dev, 1, t1->entries);
1040*4882a593Smuzhiyun if (ret)
1041*4882a593Smuzhiyun mlx4_warn(dev, "failed to unmirror VLAN tables for port 1(%d)\n", ret);
1042*4882a593Smuzhiyun }
1043*4882a593Smuzhiyun if (update2) {
1044*4882a593Smuzhiyun ret1 = mlx4_set_port_vlan_table(dev, 2, t2->entries);
1045*4882a593Smuzhiyun if (ret1) {
1046*4882a593Smuzhiyun mlx4_warn(dev, "failed to unmirror VLAN tables for port 2(%d)\n", ret1);
1047*4882a593Smuzhiyun ret = ret1;
1048*4882a593Smuzhiyun }
1049*4882a593Smuzhiyun }
1050*4882a593Smuzhiyun unlock:
1051*4882a593Smuzhiyun mutex_unlock(&t2->mutex);
1052*4882a593Smuzhiyun mutex_unlock(&t1->mutex);
1053*4882a593Smuzhiyun return ret;
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun
mlx4_get_port_ib_caps(struct mlx4_dev * dev,u8 port,__be32 * caps)1056*4882a593Smuzhiyun int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
1057*4882a593Smuzhiyun {
1058*4882a593Smuzhiyun struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
1059*4882a593Smuzhiyun u8 *inbuf, *outbuf;
1060*4882a593Smuzhiyun int err;
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun inmailbox = mlx4_alloc_cmd_mailbox(dev);
1063*4882a593Smuzhiyun if (IS_ERR(inmailbox))
1064*4882a593Smuzhiyun return PTR_ERR(inmailbox);
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun outmailbox = mlx4_alloc_cmd_mailbox(dev);
1067*4882a593Smuzhiyun if (IS_ERR(outmailbox)) {
1068*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, inmailbox);
1069*4882a593Smuzhiyun return PTR_ERR(outmailbox);
1070*4882a593Smuzhiyun }
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun inbuf = inmailbox->buf;
1073*4882a593Smuzhiyun outbuf = outmailbox->buf;
1074*4882a593Smuzhiyun inbuf[0] = 1;
1075*4882a593Smuzhiyun inbuf[1] = 1;
1076*4882a593Smuzhiyun inbuf[2] = 1;
1077*4882a593Smuzhiyun inbuf[3] = 1;
1078*4882a593Smuzhiyun *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
1079*4882a593Smuzhiyun *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
1082*4882a593Smuzhiyun MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
1083*4882a593Smuzhiyun MLX4_CMD_NATIVE);
1084*4882a593Smuzhiyun if (!err)
1085*4882a593Smuzhiyun *caps = *(__be32 *) (outbuf + 84);
1086*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, inmailbox);
1087*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, outmailbox);
1088*4882a593Smuzhiyun return err;
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun static struct mlx4_roce_gid_entry zgid_entry;
1091*4882a593Smuzhiyun
mlx4_get_slave_num_gids(struct mlx4_dev * dev,int slave,int port)1092*4882a593Smuzhiyun int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port)
1093*4882a593Smuzhiyun {
1094*4882a593Smuzhiyun int vfs;
1095*4882a593Smuzhiyun int slave_gid = slave;
1096*4882a593Smuzhiyun unsigned i;
1097*4882a593Smuzhiyun struct mlx4_slaves_pport slaves_pport;
1098*4882a593Smuzhiyun struct mlx4_active_ports actv_ports;
1099*4882a593Smuzhiyun unsigned max_port_p_one;
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun if (slave == 0)
1102*4882a593Smuzhiyun return MLX4_ROCE_PF_GIDS;
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun /* Slave is a VF */
1105*4882a593Smuzhiyun slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
1106*4882a593Smuzhiyun actv_ports = mlx4_get_active_ports(dev, slave);
1107*4882a593Smuzhiyun max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) +
1108*4882a593Smuzhiyun bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1;
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun for (i = 1; i < max_port_p_one; i++) {
1111*4882a593Smuzhiyun struct mlx4_active_ports exclusive_ports;
1112*4882a593Smuzhiyun struct mlx4_slaves_pport slaves_pport_actv;
1113*4882a593Smuzhiyun bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
1114*4882a593Smuzhiyun set_bit(i - 1, exclusive_ports.ports);
1115*4882a593Smuzhiyun if (i == port)
1116*4882a593Smuzhiyun continue;
1117*4882a593Smuzhiyun slaves_pport_actv = mlx4_phys_to_slaves_pport_actv(
1118*4882a593Smuzhiyun dev, &exclusive_ports);
1119*4882a593Smuzhiyun slave_gid -= bitmap_weight(slaves_pport_actv.slaves,
1120*4882a593Smuzhiyun dev->persist->num_vfs + 1);
1121*4882a593Smuzhiyun }
1122*4882a593Smuzhiyun vfs = bitmap_weight(slaves_pport.slaves, dev->persist->num_vfs + 1) - 1;
1123*4882a593Smuzhiyun if (slave_gid <= ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) % vfs))
1124*4882a593Smuzhiyun return ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / vfs) + 1;
1125*4882a593Smuzhiyun return (MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / vfs;
1126*4882a593Smuzhiyun }
1127*4882a593Smuzhiyun
mlx4_get_base_gid_ix(struct mlx4_dev * dev,int slave,int port)1128*4882a593Smuzhiyun int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port)
1129*4882a593Smuzhiyun {
1130*4882a593Smuzhiyun int gids;
1131*4882a593Smuzhiyun unsigned i;
1132*4882a593Smuzhiyun int slave_gid = slave;
1133*4882a593Smuzhiyun int vfs;
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun struct mlx4_slaves_pport slaves_pport;
1136*4882a593Smuzhiyun struct mlx4_active_ports actv_ports;
1137*4882a593Smuzhiyun unsigned max_port_p_one;
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun if (slave == 0)
1140*4882a593Smuzhiyun return 0;
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
1143*4882a593Smuzhiyun actv_ports = mlx4_get_active_ports(dev, slave);
1144*4882a593Smuzhiyun max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) +
1145*4882a593Smuzhiyun bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1;
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun for (i = 1; i < max_port_p_one; i++) {
1148*4882a593Smuzhiyun struct mlx4_active_ports exclusive_ports;
1149*4882a593Smuzhiyun struct mlx4_slaves_pport slaves_pport_actv;
1150*4882a593Smuzhiyun bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
1151*4882a593Smuzhiyun set_bit(i - 1, exclusive_ports.ports);
1152*4882a593Smuzhiyun if (i == port)
1153*4882a593Smuzhiyun continue;
1154*4882a593Smuzhiyun slaves_pport_actv = mlx4_phys_to_slaves_pport_actv(
1155*4882a593Smuzhiyun dev, &exclusive_ports);
1156*4882a593Smuzhiyun slave_gid -= bitmap_weight(slaves_pport_actv.slaves,
1157*4882a593Smuzhiyun dev->persist->num_vfs + 1);
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
1160*4882a593Smuzhiyun vfs = bitmap_weight(slaves_pport.slaves, dev->persist->num_vfs + 1) - 1;
1161*4882a593Smuzhiyun if (slave_gid <= gids % vfs)
1162*4882a593Smuzhiyun return MLX4_ROCE_PF_GIDS + ((gids / vfs) + 1) * (slave_gid - 1);
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun return MLX4_ROCE_PF_GIDS + (gids % vfs) +
1165*4882a593Smuzhiyun ((gids / vfs) * (slave_gid - 1));
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mlx4_get_base_gid_ix);
1168*4882a593Smuzhiyun
mlx4_reset_roce_port_gids(struct mlx4_dev * dev,int slave,int port,struct mlx4_cmd_mailbox * mailbox)1169*4882a593Smuzhiyun static int mlx4_reset_roce_port_gids(struct mlx4_dev *dev, int slave,
1170*4882a593Smuzhiyun int port, struct mlx4_cmd_mailbox *mailbox)
1171*4882a593Smuzhiyun {
1172*4882a593Smuzhiyun struct mlx4_roce_gid_entry *gid_entry_mbox;
1173*4882a593Smuzhiyun struct mlx4_priv *priv = mlx4_priv(dev);
1174*4882a593Smuzhiyun int num_gids, base, offset;
1175*4882a593Smuzhiyun int i, err;
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun num_gids = mlx4_get_slave_num_gids(dev, slave, port);
1178*4882a593Smuzhiyun base = mlx4_get_base_gid_ix(dev, slave, port);
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun mutex_lock(&(priv->port[port].gid_table.mutex));
1183*4882a593Smuzhiyun /* Zero-out gids belonging to that slave in the port GID table */
1184*4882a593Smuzhiyun for (i = 0, offset = base; i < num_gids; offset++, i++)
1185*4882a593Smuzhiyun memcpy(priv->port[port].gid_table.roce_gids[offset].raw,
1186*4882a593Smuzhiyun zgid_entry.raw, MLX4_ROCE_GID_ENTRY_SIZE);
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun /* Now, copy roce port gids table to mailbox for passing to FW */
1189*4882a593Smuzhiyun gid_entry_mbox = (struct mlx4_roce_gid_entry *)mailbox->buf;
1190*4882a593Smuzhiyun for (i = 0; i < MLX4_ROCE_MAX_GIDS; gid_entry_mbox++, i++)
1191*4882a593Smuzhiyun memcpy(gid_entry_mbox->raw,
1192*4882a593Smuzhiyun priv->port[port].gid_table.roce_gids[i].raw,
1193*4882a593Smuzhiyun MLX4_ROCE_GID_ENTRY_SIZE);
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma,
1196*4882a593Smuzhiyun ((u32)port) | (MLX4_SET_PORT_GID_TABLE << 8),
1197*4882a593Smuzhiyun MLX4_SET_PORT_ETH_OPCODE, MLX4_CMD_SET_PORT,
1198*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1199*4882a593Smuzhiyun mutex_unlock(&(priv->port[port].gid_table.mutex));
1200*4882a593Smuzhiyun return err;
1201*4882a593Smuzhiyun }
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun
mlx4_reset_roce_gids(struct mlx4_dev * dev,int slave)1204*4882a593Smuzhiyun void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave)
1205*4882a593Smuzhiyun {
1206*4882a593Smuzhiyun struct mlx4_active_ports actv_ports;
1207*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1208*4882a593Smuzhiyun int num_eth_ports, err;
1209*4882a593Smuzhiyun int i;
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun if (slave < 0 || slave > dev->persist->num_vfs)
1212*4882a593Smuzhiyun return;
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun actv_ports = mlx4_get_active_ports(dev, slave);
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun for (i = 0, num_eth_ports = 0; i < dev->caps.num_ports; i++) {
1217*4882a593Smuzhiyun if (test_bit(i, actv_ports.ports)) {
1218*4882a593Smuzhiyun if (dev->caps.port_type[i + 1] != MLX4_PORT_TYPE_ETH)
1219*4882a593Smuzhiyun continue;
1220*4882a593Smuzhiyun num_eth_ports++;
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun }
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun if (!num_eth_ports)
1225*4882a593Smuzhiyun return;
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun /* have ETH ports. Alloc mailbox for SET_PORT command */
1228*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1229*4882a593Smuzhiyun if (IS_ERR(mailbox))
1230*4882a593Smuzhiyun return;
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun for (i = 0; i < dev->caps.num_ports; i++) {
1233*4882a593Smuzhiyun if (test_bit(i, actv_ports.ports)) {
1234*4882a593Smuzhiyun if (dev->caps.port_type[i + 1] != MLX4_PORT_TYPE_ETH)
1235*4882a593Smuzhiyun continue;
1236*4882a593Smuzhiyun err = mlx4_reset_roce_port_gids(dev, slave, i + 1, mailbox);
1237*4882a593Smuzhiyun if (err)
1238*4882a593Smuzhiyun mlx4_warn(dev, "Could not reset ETH port GID table for slave %d, port %d (%d)\n",
1239*4882a593Smuzhiyun slave, i + 1, err);
1240*4882a593Smuzhiyun }
1241*4882a593Smuzhiyun }
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1244*4882a593Smuzhiyun return;
1245*4882a593Smuzhiyun }
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun static void
mlx4_en_set_port_mtu(struct mlx4_dev * dev,int slave,int port,struct mlx4_set_port_general_context * gen_context)1248*4882a593Smuzhiyun mlx4_en_set_port_mtu(struct mlx4_dev *dev, int slave, int port,
1249*4882a593Smuzhiyun struct mlx4_set_port_general_context *gen_context)
1250*4882a593Smuzhiyun {
1251*4882a593Smuzhiyun struct mlx4_priv *priv = mlx4_priv(dev);
1252*4882a593Smuzhiyun struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
1253*4882a593Smuzhiyun struct mlx4_slave_state *slave_st = &master->slave_state[slave];
1254*4882a593Smuzhiyun u16 mtu, prev_mtu;
1255*4882a593Smuzhiyun
1256*4882a593Smuzhiyun /* Mtu is configured as the max USER_MTU among all
1257*4882a593Smuzhiyun * the functions on the port.
1258*4882a593Smuzhiyun */
1259*4882a593Smuzhiyun mtu = be16_to_cpu(gen_context->mtu);
1260*4882a593Smuzhiyun mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] +
1261*4882a593Smuzhiyun ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
1262*4882a593Smuzhiyun prev_mtu = slave_st->mtu[port];
1263*4882a593Smuzhiyun slave_st->mtu[port] = mtu;
1264*4882a593Smuzhiyun if (mtu > master->max_mtu[port])
1265*4882a593Smuzhiyun master->max_mtu[port] = mtu;
1266*4882a593Smuzhiyun if (mtu < prev_mtu && prev_mtu == master->max_mtu[port]) {
1267*4882a593Smuzhiyun int i;
1268*4882a593Smuzhiyun
1269*4882a593Smuzhiyun slave_st->mtu[port] = mtu;
1270*4882a593Smuzhiyun master->max_mtu[port] = mtu;
1271*4882a593Smuzhiyun for (i = 0; i < dev->num_slaves; i++)
1272*4882a593Smuzhiyun master->max_mtu[port] =
1273*4882a593Smuzhiyun max_t(u16, master->max_mtu[port],
1274*4882a593Smuzhiyun master->slave_state[i].mtu[port]);
1275*4882a593Smuzhiyun }
1276*4882a593Smuzhiyun gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
1277*4882a593Smuzhiyun }
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun static void
mlx4_en_set_port_user_mtu(struct mlx4_dev * dev,int slave,int port,struct mlx4_set_port_general_context * gen_context)1280*4882a593Smuzhiyun mlx4_en_set_port_user_mtu(struct mlx4_dev *dev, int slave, int port,
1281*4882a593Smuzhiyun struct mlx4_set_port_general_context *gen_context)
1282*4882a593Smuzhiyun {
1283*4882a593Smuzhiyun struct mlx4_priv *priv = mlx4_priv(dev);
1284*4882a593Smuzhiyun struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
1285*4882a593Smuzhiyun struct mlx4_slave_state *slave_st = &master->slave_state[slave];
1286*4882a593Smuzhiyun u16 user_mtu, prev_user_mtu;
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun /* User Mtu is configured as the max USER_MTU among all
1289*4882a593Smuzhiyun * the functions on the port.
1290*4882a593Smuzhiyun */
1291*4882a593Smuzhiyun user_mtu = be16_to_cpu(gen_context->user_mtu);
1292*4882a593Smuzhiyun user_mtu = min_t(int, user_mtu, dev->caps.eth_mtu_cap[port]);
1293*4882a593Smuzhiyun prev_user_mtu = slave_st->user_mtu[port];
1294*4882a593Smuzhiyun slave_st->user_mtu[port] = user_mtu;
1295*4882a593Smuzhiyun if (user_mtu > master->max_user_mtu[port])
1296*4882a593Smuzhiyun master->max_user_mtu[port] = user_mtu;
1297*4882a593Smuzhiyun if (user_mtu < prev_user_mtu &&
1298*4882a593Smuzhiyun prev_user_mtu == master->max_user_mtu[port]) {
1299*4882a593Smuzhiyun int i;
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun slave_st->user_mtu[port] = user_mtu;
1302*4882a593Smuzhiyun master->max_user_mtu[port] = user_mtu;
1303*4882a593Smuzhiyun for (i = 0; i < dev->num_slaves; i++)
1304*4882a593Smuzhiyun master->max_user_mtu[port] =
1305*4882a593Smuzhiyun max_t(u16, master->max_user_mtu[port],
1306*4882a593Smuzhiyun master->slave_state[i].user_mtu[port]);
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun gen_context->user_mtu = cpu_to_be16(master->max_user_mtu[port]);
1309*4882a593Smuzhiyun }
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun static void
mlx4_en_set_port_global_pause(struct mlx4_dev * dev,int slave,struct mlx4_set_port_general_context * gen_context)1312*4882a593Smuzhiyun mlx4_en_set_port_global_pause(struct mlx4_dev *dev, int slave,
1313*4882a593Smuzhiyun struct mlx4_set_port_general_context *gen_context)
1314*4882a593Smuzhiyun {
1315*4882a593Smuzhiyun struct mlx4_priv *priv = mlx4_priv(dev);
1316*4882a593Smuzhiyun struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun /* Slave cannot change Global Pause configuration */
1319*4882a593Smuzhiyun if (slave != mlx4_master_func_num(dev) &&
1320*4882a593Smuzhiyun (gen_context->pptx != master->pptx ||
1321*4882a593Smuzhiyun gen_context->pprx != master->pprx)) {
1322*4882a593Smuzhiyun gen_context->pptx = master->pptx;
1323*4882a593Smuzhiyun gen_context->pprx = master->pprx;
1324*4882a593Smuzhiyun mlx4_warn(dev, "denying Global Pause change for slave:%d\n",
1325*4882a593Smuzhiyun slave);
1326*4882a593Smuzhiyun } else {
1327*4882a593Smuzhiyun master->pptx = gen_context->pptx;
1328*4882a593Smuzhiyun master->pprx = gen_context->pprx;
1329*4882a593Smuzhiyun }
1330*4882a593Smuzhiyun }
1331*4882a593Smuzhiyun
mlx4_common_set_port(struct mlx4_dev * dev,int slave,u32 in_mod,u8 op_mod,struct mlx4_cmd_mailbox * inbox)1332*4882a593Smuzhiyun static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
1333*4882a593Smuzhiyun u8 op_mod, struct mlx4_cmd_mailbox *inbox)
1334*4882a593Smuzhiyun {
1335*4882a593Smuzhiyun struct mlx4_priv *priv = mlx4_priv(dev);
1336*4882a593Smuzhiyun struct mlx4_port_info *port_info;
1337*4882a593Smuzhiyun struct mlx4_set_port_rqp_calc_context *qpn_context;
1338*4882a593Smuzhiyun struct mlx4_set_port_general_context *gen_context;
1339*4882a593Smuzhiyun struct mlx4_roce_gid_entry *gid_entry_tbl, *gid_entry_mbox, *gid_entry_mb1;
1340*4882a593Smuzhiyun int reset_qkey_viols;
1341*4882a593Smuzhiyun int port;
1342*4882a593Smuzhiyun int is_eth;
1343*4882a593Smuzhiyun int num_gids;
1344*4882a593Smuzhiyun int base;
1345*4882a593Smuzhiyun u32 in_modifier;
1346*4882a593Smuzhiyun u32 promisc;
1347*4882a593Smuzhiyun int err;
1348*4882a593Smuzhiyun int i, j;
1349*4882a593Smuzhiyun int offset;
1350*4882a593Smuzhiyun __be32 agg_cap_mask;
1351*4882a593Smuzhiyun __be32 slave_cap_mask;
1352*4882a593Smuzhiyun __be32 new_cap_mask;
1353*4882a593Smuzhiyun
1354*4882a593Smuzhiyun port = in_mod & 0xff;
1355*4882a593Smuzhiyun in_modifier = in_mod >> 8;
1356*4882a593Smuzhiyun is_eth = op_mod;
1357*4882a593Smuzhiyun port_info = &priv->port[port];
1358*4882a593Smuzhiyun
1359*4882a593Smuzhiyun /* Slaves cannot perform SET_PORT operations,
1360*4882a593Smuzhiyun * except for changing MTU and USER_MTU.
1361*4882a593Smuzhiyun */
1362*4882a593Smuzhiyun if (is_eth) {
1363*4882a593Smuzhiyun if (slave != dev->caps.function &&
1364*4882a593Smuzhiyun in_modifier != MLX4_SET_PORT_GENERAL &&
1365*4882a593Smuzhiyun in_modifier != MLX4_SET_PORT_GID_TABLE) {
1366*4882a593Smuzhiyun mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
1367*4882a593Smuzhiyun slave);
1368*4882a593Smuzhiyun return -EINVAL;
1369*4882a593Smuzhiyun }
1370*4882a593Smuzhiyun switch (in_modifier) {
1371*4882a593Smuzhiyun case MLX4_SET_PORT_RQP_CALC:
1372*4882a593Smuzhiyun qpn_context = inbox->buf;
1373*4882a593Smuzhiyun qpn_context->base_qpn =
1374*4882a593Smuzhiyun cpu_to_be32(port_info->base_qpn);
1375*4882a593Smuzhiyun qpn_context->n_mac = 0x7;
1376*4882a593Smuzhiyun promisc = be32_to_cpu(qpn_context->promisc) >>
1377*4882a593Smuzhiyun SET_PORT_PROMISC_SHIFT;
1378*4882a593Smuzhiyun qpn_context->promisc = cpu_to_be32(
1379*4882a593Smuzhiyun promisc << SET_PORT_PROMISC_SHIFT |
1380*4882a593Smuzhiyun port_info->base_qpn);
1381*4882a593Smuzhiyun promisc = be32_to_cpu(qpn_context->mcast) >>
1382*4882a593Smuzhiyun SET_PORT_MC_PROMISC_SHIFT;
1383*4882a593Smuzhiyun qpn_context->mcast = cpu_to_be32(
1384*4882a593Smuzhiyun promisc << SET_PORT_MC_PROMISC_SHIFT |
1385*4882a593Smuzhiyun port_info->base_qpn);
1386*4882a593Smuzhiyun break;
1387*4882a593Smuzhiyun case MLX4_SET_PORT_GENERAL:
1388*4882a593Smuzhiyun gen_context = inbox->buf;
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun if (gen_context->flags & MLX4_FLAG_V_MTU_MASK)
1391*4882a593Smuzhiyun mlx4_en_set_port_mtu(dev, slave, port,
1392*4882a593Smuzhiyun gen_context);
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun if (gen_context->flags2 & MLX4_FLAG2_V_USER_MTU_MASK)
1395*4882a593Smuzhiyun mlx4_en_set_port_user_mtu(dev, slave, port,
1396*4882a593Smuzhiyun gen_context);
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun if (gen_context->flags &
1399*4882a593Smuzhiyun (MLX4_FLAG_V_PPRX_MASK | MLX4_FLAG_V_PPTX_MASK))
1400*4882a593Smuzhiyun mlx4_en_set_port_global_pause(dev, slave,
1401*4882a593Smuzhiyun gen_context);
1402*4882a593Smuzhiyun
1403*4882a593Smuzhiyun break;
1404*4882a593Smuzhiyun case MLX4_SET_PORT_GID_TABLE:
1405*4882a593Smuzhiyun /* change to MULTIPLE entries: number of guest's gids
1406*4882a593Smuzhiyun * need a FOR-loop here over number of gids the guest has.
1407*4882a593Smuzhiyun * 1. Check no duplicates in gids passed by slave
1408*4882a593Smuzhiyun */
1409*4882a593Smuzhiyun num_gids = mlx4_get_slave_num_gids(dev, slave, port);
1410*4882a593Smuzhiyun base = mlx4_get_base_gid_ix(dev, slave, port);
1411*4882a593Smuzhiyun gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
1412*4882a593Smuzhiyun for (i = 0; i < num_gids; gid_entry_mbox++, i++) {
1413*4882a593Smuzhiyun if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
1414*4882a593Smuzhiyun sizeof(zgid_entry)))
1415*4882a593Smuzhiyun continue;
1416*4882a593Smuzhiyun gid_entry_mb1 = gid_entry_mbox + 1;
1417*4882a593Smuzhiyun for (j = i + 1; j < num_gids; gid_entry_mb1++, j++) {
1418*4882a593Smuzhiyun if (!memcmp(gid_entry_mb1->raw,
1419*4882a593Smuzhiyun zgid_entry.raw, sizeof(zgid_entry)))
1420*4882a593Smuzhiyun continue;
1421*4882a593Smuzhiyun if (!memcmp(gid_entry_mb1->raw, gid_entry_mbox->raw,
1422*4882a593Smuzhiyun sizeof(gid_entry_mbox->raw))) {
1423*4882a593Smuzhiyun /* found duplicate */
1424*4882a593Smuzhiyun return -EINVAL;
1425*4882a593Smuzhiyun }
1426*4882a593Smuzhiyun }
1427*4882a593Smuzhiyun }
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun /* 2. Check that do not have duplicates in OTHER
1430*4882a593Smuzhiyun * entries in the port GID table
1431*4882a593Smuzhiyun */
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun mutex_lock(&(priv->port[port].gid_table.mutex));
1434*4882a593Smuzhiyun for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
1435*4882a593Smuzhiyun if (i >= base && i < base + num_gids)
1436*4882a593Smuzhiyun continue; /* don't compare to slave's current gids */
1437*4882a593Smuzhiyun gid_entry_tbl = &priv->port[port].gid_table.roce_gids[i];
1438*4882a593Smuzhiyun if (!memcmp(gid_entry_tbl->raw, zgid_entry.raw, sizeof(zgid_entry)))
1439*4882a593Smuzhiyun continue;
1440*4882a593Smuzhiyun gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
1441*4882a593Smuzhiyun for (j = 0; j < num_gids; gid_entry_mbox++, j++) {
1442*4882a593Smuzhiyun if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
1443*4882a593Smuzhiyun sizeof(zgid_entry)))
1444*4882a593Smuzhiyun continue;
1445*4882a593Smuzhiyun if (!memcmp(gid_entry_mbox->raw, gid_entry_tbl->raw,
1446*4882a593Smuzhiyun sizeof(gid_entry_tbl->raw))) {
1447*4882a593Smuzhiyun /* found duplicate */
1448*4882a593Smuzhiyun mlx4_warn(dev, "requested gid entry for slave:%d is a duplicate of gid at index %d\n",
1449*4882a593Smuzhiyun slave, i);
1450*4882a593Smuzhiyun mutex_unlock(&(priv->port[port].gid_table.mutex));
1451*4882a593Smuzhiyun return -EINVAL;
1452*4882a593Smuzhiyun }
1453*4882a593Smuzhiyun }
1454*4882a593Smuzhiyun }
1455*4882a593Smuzhiyun
1456*4882a593Smuzhiyun /* insert slave GIDs with memcpy, starting at slave's base index */
1457*4882a593Smuzhiyun gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
1458*4882a593Smuzhiyun for (i = 0, offset = base; i < num_gids; gid_entry_mbox++, offset++, i++)
1459*4882a593Smuzhiyun memcpy(priv->port[port].gid_table.roce_gids[offset].raw,
1460*4882a593Smuzhiyun gid_entry_mbox->raw, MLX4_ROCE_GID_ENTRY_SIZE);
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun /* Now, copy roce port gids table to current mailbox for passing to FW */
1463*4882a593Smuzhiyun gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
1464*4882a593Smuzhiyun for (i = 0; i < MLX4_ROCE_MAX_GIDS; gid_entry_mbox++, i++)
1465*4882a593Smuzhiyun memcpy(gid_entry_mbox->raw,
1466*4882a593Smuzhiyun priv->port[port].gid_table.roce_gids[i].raw,
1467*4882a593Smuzhiyun MLX4_ROCE_GID_ENTRY_SIZE);
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun err = mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
1470*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1471*4882a593Smuzhiyun MLX4_CMD_NATIVE);
1472*4882a593Smuzhiyun mutex_unlock(&(priv->port[port].gid_table.mutex));
1473*4882a593Smuzhiyun return err;
1474*4882a593Smuzhiyun }
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun return mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
1477*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1478*4882a593Smuzhiyun MLX4_CMD_NATIVE);
1479*4882a593Smuzhiyun }
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun /* Slaves are not allowed to SET_PORT beacon (LED) blink */
1482*4882a593Smuzhiyun if (op_mod == MLX4_SET_PORT_BEACON_OPCODE) {
1483*4882a593Smuzhiyun mlx4_warn(dev, "denying SET_PORT Beacon slave:%d\n", slave);
1484*4882a593Smuzhiyun return -EPERM;
1485*4882a593Smuzhiyun }
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun /* For IB, we only consider:
1488*4882a593Smuzhiyun * - The capability mask, which is set to the aggregate of all
1489*4882a593Smuzhiyun * slave function capabilities
1490*4882a593Smuzhiyun * - The QKey violatin counter - reset according to each request.
1491*4882a593Smuzhiyun */
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1494*4882a593Smuzhiyun reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
1495*4882a593Smuzhiyun new_cap_mask = ((__be32 *) inbox->buf)[2];
1496*4882a593Smuzhiyun } else {
1497*4882a593Smuzhiyun reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
1498*4882a593Smuzhiyun new_cap_mask = ((__be32 *) inbox->buf)[1];
1499*4882a593Smuzhiyun }
1500*4882a593Smuzhiyun
1501*4882a593Smuzhiyun /* slave may not set the IS_SM capability for the port */
1502*4882a593Smuzhiyun if (slave != mlx4_master_func_num(dev) &&
1503*4882a593Smuzhiyun (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM))
1504*4882a593Smuzhiyun return -EINVAL;
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun /* No DEV_MGMT in multifunc mode */
1507*4882a593Smuzhiyun if (mlx4_is_mfunc(dev) &&
1508*4882a593Smuzhiyun (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP))
1509*4882a593Smuzhiyun return -EINVAL;
1510*4882a593Smuzhiyun
1511*4882a593Smuzhiyun agg_cap_mask = 0;
1512*4882a593Smuzhiyun slave_cap_mask =
1513*4882a593Smuzhiyun priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
1514*4882a593Smuzhiyun priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
1515*4882a593Smuzhiyun for (i = 0; i < dev->num_slaves; i++)
1516*4882a593Smuzhiyun agg_cap_mask |=
1517*4882a593Smuzhiyun priv->mfunc.master.slave_state[i].ib_cap_mask[port];
1518*4882a593Smuzhiyun
1519*4882a593Smuzhiyun /* only clear mailbox for guests. Master may be setting
1520*4882a593Smuzhiyun * MTU or PKEY table size
1521*4882a593Smuzhiyun */
1522*4882a593Smuzhiyun if (slave != dev->caps.function)
1523*4882a593Smuzhiyun memset(inbox->buf, 0, 256);
1524*4882a593Smuzhiyun if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1525*4882a593Smuzhiyun *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
1526*4882a593Smuzhiyun ((__be32 *) inbox->buf)[2] = agg_cap_mask;
1527*4882a593Smuzhiyun } else {
1528*4882a593Smuzhiyun ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
1529*4882a593Smuzhiyun ((__be32 *) inbox->buf)[1] = agg_cap_mask;
1530*4882a593Smuzhiyun }
1531*4882a593Smuzhiyun
1532*4882a593Smuzhiyun err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
1533*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1534*4882a593Smuzhiyun if (err)
1535*4882a593Smuzhiyun priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
1536*4882a593Smuzhiyun slave_cap_mask;
1537*4882a593Smuzhiyun return err;
1538*4882a593Smuzhiyun }
1539*4882a593Smuzhiyun
mlx4_SET_PORT_wrapper(struct mlx4_dev * dev,int slave,struct mlx4_vhcr * vhcr,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox,struct mlx4_cmd_info * cmd)1540*4882a593Smuzhiyun int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1541*4882a593Smuzhiyun struct mlx4_vhcr *vhcr,
1542*4882a593Smuzhiyun struct mlx4_cmd_mailbox *inbox,
1543*4882a593Smuzhiyun struct mlx4_cmd_mailbox *outbox,
1544*4882a593Smuzhiyun struct mlx4_cmd_info *cmd)
1545*4882a593Smuzhiyun {
1546*4882a593Smuzhiyun int port = mlx4_slave_convert_port(
1547*4882a593Smuzhiyun dev, slave, vhcr->in_modifier & 0xFF);
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun if (port < 0)
1550*4882a593Smuzhiyun return -EINVAL;
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun vhcr->in_modifier = (vhcr->in_modifier & ~0xFF) |
1553*4882a593Smuzhiyun (port & 0xFF);
1554*4882a593Smuzhiyun
1555*4882a593Smuzhiyun return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
1556*4882a593Smuzhiyun vhcr->op_modifier, inbox);
1557*4882a593Smuzhiyun }
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun /* bit locations for set port command with zero op modifier */
1560*4882a593Smuzhiyun enum {
1561*4882a593Smuzhiyun MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
1562*4882a593Smuzhiyun MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
1563*4882a593Smuzhiyun MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
1564*4882a593Smuzhiyun MLX4_CHANGE_PORT_VL_CAP = 21,
1565*4882a593Smuzhiyun MLX4_CHANGE_PORT_MTU_CAP = 22,
1566*4882a593Smuzhiyun };
1567*4882a593Smuzhiyun
mlx4_SET_PORT(struct mlx4_dev * dev,u8 port,int pkey_tbl_sz)1568*4882a593Smuzhiyun int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
1569*4882a593Smuzhiyun {
1570*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1571*4882a593Smuzhiyun int err, vl_cap, pkey_tbl_flag = 0;
1572*4882a593Smuzhiyun
1573*4882a593Smuzhiyun if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1574*4882a593Smuzhiyun return 0;
1575*4882a593Smuzhiyun
1576*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1577*4882a593Smuzhiyun if (IS_ERR(mailbox))
1578*4882a593Smuzhiyun return PTR_ERR(mailbox);
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
1581*4882a593Smuzhiyun
1582*4882a593Smuzhiyun if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
1583*4882a593Smuzhiyun pkey_tbl_flag = 1;
1584*4882a593Smuzhiyun ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
1585*4882a593Smuzhiyun }
1586*4882a593Smuzhiyun
1587*4882a593Smuzhiyun /* IB VL CAP enum isn't used by the firmware, just numerical values */
1588*4882a593Smuzhiyun for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) {
1589*4882a593Smuzhiyun ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
1590*4882a593Smuzhiyun (1 << MLX4_CHANGE_PORT_MTU_CAP) |
1591*4882a593Smuzhiyun (1 << MLX4_CHANGE_PORT_VL_CAP) |
1592*4882a593Smuzhiyun (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
1593*4882a593Smuzhiyun (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
1594*4882a593Smuzhiyun (vl_cap << MLX4_SET_PORT_VL_CAP));
1595*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, port,
1596*4882a593Smuzhiyun MLX4_SET_PORT_IB_OPCODE, MLX4_CMD_SET_PORT,
1597*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
1598*4882a593Smuzhiyun if (err != -ENOMEM)
1599*4882a593Smuzhiyun break;
1600*4882a593Smuzhiyun }
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1603*4882a593Smuzhiyun return err;
1604*4882a593Smuzhiyun }
1605*4882a593Smuzhiyun
1606*4882a593Smuzhiyun #define SET_PORT_ROCE_2_FLAGS 0x10
1607*4882a593Smuzhiyun #define MLX4_SET_PORT_ROCE_V1_V2 0x2
mlx4_SET_PORT_general(struct mlx4_dev * dev,u8 port,int mtu,u8 pptx,u8 pfctx,u8 pprx,u8 pfcrx)1608*4882a593Smuzhiyun int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1609*4882a593Smuzhiyun u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
1610*4882a593Smuzhiyun {
1611*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1612*4882a593Smuzhiyun struct mlx4_set_port_general_context *context;
1613*4882a593Smuzhiyun int err;
1614*4882a593Smuzhiyun u32 in_mod;
1615*4882a593Smuzhiyun
1616*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1617*4882a593Smuzhiyun if (IS_ERR(mailbox))
1618*4882a593Smuzhiyun return PTR_ERR(mailbox);
1619*4882a593Smuzhiyun context = mailbox->buf;
1620*4882a593Smuzhiyun context->flags = SET_PORT_GEN_ALL_VALID;
1621*4882a593Smuzhiyun context->mtu = cpu_to_be16(mtu);
1622*4882a593Smuzhiyun context->pptx = (pptx * (!pfctx)) << 7;
1623*4882a593Smuzhiyun context->pfctx = pfctx;
1624*4882a593Smuzhiyun context->pprx = (pprx * (!pfcrx)) << 7;
1625*4882a593Smuzhiyun context->pfcrx = pfcrx;
1626*4882a593Smuzhiyun
1627*4882a593Smuzhiyun if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1628*4882a593Smuzhiyun context->flags |= SET_PORT_ROCE_2_FLAGS;
1629*4882a593Smuzhiyun context->roce_mode |=
1630*4882a593Smuzhiyun MLX4_SET_PORT_ROCE_V1_V2 << 4;
1631*4882a593Smuzhiyun }
1632*4882a593Smuzhiyun in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
1633*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
1634*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1635*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1638*4882a593Smuzhiyun return err;
1639*4882a593Smuzhiyun }
1640*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_SET_PORT_general);
1641*4882a593Smuzhiyun
mlx4_SET_PORT_qpn_calc(struct mlx4_dev * dev,u8 port,u32 base_qpn,u8 promisc)1642*4882a593Smuzhiyun int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1643*4882a593Smuzhiyun u8 promisc)
1644*4882a593Smuzhiyun {
1645*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1646*4882a593Smuzhiyun struct mlx4_set_port_rqp_calc_context *context;
1647*4882a593Smuzhiyun int err;
1648*4882a593Smuzhiyun u32 in_mod;
1649*4882a593Smuzhiyun u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
1650*4882a593Smuzhiyun MCAST_DIRECT : MCAST_DEFAULT;
1651*4882a593Smuzhiyun
1652*4882a593Smuzhiyun if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
1653*4882a593Smuzhiyun return 0;
1654*4882a593Smuzhiyun
1655*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1656*4882a593Smuzhiyun if (IS_ERR(mailbox))
1657*4882a593Smuzhiyun return PTR_ERR(mailbox);
1658*4882a593Smuzhiyun context = mailbox->buf;
1659*4882a593Smuzhiyun context->base_qpn = cpu_to_be32(base_qpn);
1660*4882a593Smuzhiyun context->n_mac = dev->caps.log_num_macs;
1661*4882a593Smuzhiyun context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
1662*4882a593Smuzhiyun base_qpn);
1663*4882a593Smuzhiyun context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
1664*4882a593Smuzhiyun base_qpn);
1665*4882a593Smuzhiyun context->intra_no_vlan = 0;
1666*4882a593Smuzhiyun context->no_vlan = MLX4_NO_VLAN_IDX;
1667*4882a593Smuzhiyun context->intra_vlan_miss = 0;
1668*4882a593Smuzhiyun context->vlan_miss = MLX4_VLAN_MISS_IDX;
1669*4882a593Smuzhiyun
1670*4882a593Smuzhiyun in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
1671*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
1672*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1673*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1676*4882a593Smuzhiyun return err;
1677*4882a593Smuzhiyun }
1678*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
1679*4882a593Smuzhiyun
mlx4_SET_PORT_user_mtu(struct mlx4_dev * dev,u8 port,u16 user_mtu)1680*4882a593Smuzhiyun int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu)
1681*4882a593Smuzhiyun {
1682*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1683*4882a593Smuzhiyun struct mlx4_set_port_general_context *context;
1684*4882a593Smuzhiyun u32 in_mod;
1685*4882a593Smuzhiyun int err;
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1688*4882a593Smuzhiyun if (IS_ERR(mailbox))
1689*4882a593Smuzhiyun return PTR_ERR(mailbox);
1690*4882a593Smuzhiyun context = mailbox->buf;
1691*4882a593Smuzhiyun context->flags2 |= MLX4_FLAG2_V_USER_MTU_MASK;
1692*4882a593Smuzhiyun context->user_mtu = cpu_to_be16(user_mtu);
1693*4882a593Smuzhiyun
1694*4882a593Smuzhiyun in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
1695*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
1696*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1697*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
1698*4882a593Smuzhiyun
1699*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1700*4882a593Smuzhiyun return err;
1701*4882a593Smuzhiyun }
1702*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_SET_PORT_user_mtu);
1703*4882a593Smuzhiyun
mlx4_SET_PORT_user_mac(struct mlx4_dev * dev,u8 port,u8 * user_mac)1704*4882a593Smuzhiyun int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac)
1705*4882a593Smuzhiyun {
1706*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1707*4882a593Smuzhiyun struct mlx4_set_port_general_context *context;
1708*4882a593Smuzhiyun u32 in_mod;
1709*4882a593Smuzhiyun int err;
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1712*4882a593Smuzhiyun if (IS_ERR(mailbox))
1713*4882a593Smuzhiyun return PTR_ERR(mailbox);
1714*4882a593Smuzhiyun context = mailbox->buf;
1715*4882a593Smuzhiyun context->flags2 |= MLX4_FLAG2_V_USER_MAC_MASK;
1716*4882a593Smuzhiyun memcpy(context->user_mac, user_mac, sizeof(context->user_mac));
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
1719*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
1720*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1721*4882a593Smuzhiyun MLX4_CMD_NATIVE);
1722*4882a593Smuzhiyun
1723*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1724*4882a593Smuzhiyun return err;
1725*4882a593Smuzhiyun }
1726*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_SET_PORT_user_mac);
1727*4882a593Smuzhiyun
mlx4_SET_PORT_fcs_check(struct mlx4_dev * dev,u8 port,u8 ignore_fcs_value)1728*4882a593Smuzhiyun int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, u8 ignore_fcs_value)
1729*4882a593Smuzhiyun {
1730*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1731*4882a593Smuzhiyun struct mlx4_set_port_general_context *context;
1732*4882a593Smuzhiyun u32 in_mod;
1733*4882a593Smuzhiyun int err;
1734*4882a593Smuzhiyun
1735*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1736*4882a593Smuzhiyun if (IS_ERR(mailbox))
1737*4882a593Smuzhiyun return PTR_ERR(mailbox);
1738*4882a593Smuzhiyun context = mailbox->buf;
1739*4882a593Smuzhiyun context->flags2 |= MLX4_FLAG2_V_IGNORE_FCS_MASK;
1740*4882a593Smuzhiyun if (ignore_fcs_value)
1741*4882a593Smuzhiyun context->ignore_fcs |= MLX4_IGNORE_FCS_MASK;
1742*4882a593Smuzhiyun else
1743*4882a593Smuzhiyun context->ignore_fcs &= ~MLX4_IGNORE_FCS_MASK;
1744*4882a593Smuzhiyun
1745*4882a593Smuzhiyun in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
1746*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
1747*4882a593Smuzhiyun MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1748*4882a593Smuzhiyun
1749*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1750*4882a593Smuzhiyun return err;
1751*4882a593Smuzhiyun }
1752*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_SET_PORT_fcs_check);
1753*4882a593Smuzhiyun
1754*4882a593Smuzhiyun enum {
1755*4882a593Smuzhiyun VXLAN_ENABLE_MODIFY = 1 << 7,
1756*4882a593Smuzhiyun VXLAN_STEERING_MODIFY = 1 << 6,
1757*4882a593Smuzhiyun
1758*4882a593Smuzhiyun VXLAN_ENABLE = 1 << 7,
1759*4882a593Smuzhiyun };
1760*4882a593Smuzhiyun
1761*4882a593Smuzhiyun struct mlx4_set_port_vxlan_context {
1762*4882a593Smuzhiyun u32 reserved1;
1763*4882a593Smuzhiyun u8 modify_flags;
1764*4882a593Smuzhiyun u8 reserved2;
1765*4882a593Smuzhiyun u8 enable_flags;
1766*4882a593Smuzhiyun u8 steering;
1767*4882a593Smuzhiyun };
1768*4882a593Smuzhiyun
mlx4_SET_PORT_VXLAN(struct mlx4_dev * dev,u8 port,u8 steering,int enable)1769*4882a593Smuzhiyun int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable)
1770*4882a593Smuzhiyun {
1771*4882a593Smuzhiyun int err;
1772*4882a593Smuzhiyun u32 in_mod;
1773*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1774*4882a593Smuzhiyun struct mlx4_set_port_vxlan_context *context;
1775*4882a593Smuzhiyun
1776*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1777*4882a593Smuzhiyun if (IS_ERR(mailbox))
1778*4882a593Smuzhiyun return PTR_ERR(mailbox);
1779*4882a593Smuzhiyun context = mailbox->buf;
1780*4882a593Smuzhiyun memset(context, 0, sizeof(*context));
1781*4882a593Smuzhiyun
1782*4882a593Smuzhiyun context->modify_flags = VXLAN_ENABLE_MODIFY | VXLAN_STEERING_MODIFY;
1783*4882a593Smuzhiyun if (enable)
1784*4882a593Smuzhiyun context->enable_flags = VXLAN_ENABLE;
1785*4882a593Smuzhiyun context->steering = steering;
1786*4882a593Smuzhiyun
1787*4882a593Smuzhiyun in_mod = MLX4_SET_PORT_VXLAN << 8 | port;
1788*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
1789*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1790*4882a593Smuzhiyun MLX4_CMD_NATIVE);
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1793*4882a593Smuzhiyun return err;
1794*4882a593Smuzhiyun }
1795*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_SET_PORT_VXLAN);
1796*4882a593Smuzhiyun
mlx4_SET_PORT_BEACON(struct mlx4_dev * dev,u8 port,u16 time)1797*4882a593Smuzhiyun int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time)
1798*4882a593Smuzhiyun {
1799*4882a593Smuzhiyun int err;
1800*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
1803*4882a593Smuzhiyun if (IS_ERR(mailbox))
1804*4882a593Smuzhiyun return PTR_ERR(mailbox);
1805*4882a593Smuzhiyun
1806*4882a593Smuzhiyun *((__be32 *)mailbox->buf) = cpu_to_be32(time);
1807*4882a593Smuzhiyun
1808*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma, port, MLX4_SET_PORT_BEACON_OPCODE,
1809*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1810*4882a593Smuzhiyun MLX4_CMD_NATIVE);
1811*4882a593Smuzhiyun
1812*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
1813*4882a593Smuzhiyun return err;
1814*4882a593Smuzhiyun }
1815*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_SET_PORT_BEACON);
1816*4882a593Smuzhiyun
mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev * dev,int slave,struct mlx4_vhcr * vhcr,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox,struct mlx4_cmd_info * cmd)1817*4882a593Smuzhiyun int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1818*4882a593Smuzhiyun struct mlx4_vhcr *vhcr,
1819*4882a593Smuzhiyun struct mlx4_cmd_mailbox *inbox,
1820*4882a593Smuzhiyun struct mlx4_cmd_mailbox *outbox,
1821*4882a593Smuzhiyun struct mlx4_cmd_info *cmd)
1822*4882a593Smuzhiyun {
1823*4882a593Smuzhiyun int err = 0;
1824*4882a593Smuzhiyun
1825*4882a593Smuzhiyun return err;
1826*4882a593Smuzhiyun }
1827*4882a593Smuzhiyun
mlx4_SET_MCAST_FLTR(struct mlx4_dev * dev,u8 port,u64 mac,u64 clear,u8 mode)1828*4882a593Smuzhiyun int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
1829*4882a593Smuzhiyun u64 mac, u64 clear, u8 mode)
1830*4882a593Smuzhiyun {
1831*4882a593Smuzhiyun return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
1832*4882a593Smuzhiyun MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
1833*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
1834*4882a593Smuzhiyun }
1835*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
1836*4882a593Smuzhiyun
mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev * dev,int slave,struct mlx4_vhcr * vhcr,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox,struct mlx4_cmd_info * cmd)1837*4882a593Smuzhiyun int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1838*4882a593Smuzhiyun struct mlx4_vhcr *vhcr,
1839*4882a593Smuzhiyun struct mlx4_cmd_mailbox *inbox,
1840*4882a593Smuzhiyun struct mlx4_cmd_mailbox *outbox,
1841*4882a593Smuzhiyun struct mlx4_cmd_info *cmd)
1842*4882a593Smuzhiyun {
1843*4882a593Smuzhiyun int err = 0;
1844*4882a593Smuzhiyun
1845*4882a593Smuzhiyun return err;
1846*4882a593Smuzhiyun }
1847*4882a593Smuzhiyun
mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev * dev,int slave,struct mlx4_vhcr * vhcr,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox,struct mlx4_cmd_info * cmd)1848*4882a593Smuzhiyun int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1849*4882a593Smuzhiyun struct mlx4_vhcr *vhcr,
1850*4882a593Smuzhiyun struct mlx4_cmd_mailbox *inbox,
1851*4882a593Smuzhiyun struct mlx4_cmd_mailbox *outbox,
1852*4882a593Smuzhiyun struct mlx4_cmd_info *cmd)
1853*4882a593Smuzhiyun {
1854*4882a593Smuzhiyun return 0;
1855*4882a593Smuzhiyun }
1856*4882a593Smuzhiyun
mlx4_get_slave_from_roce_gid(struct mlx4_dev * dev,int port,u8 * gid,int * slave_id)1857*4882a593Smuzhiyun int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1858*4882a593Smuzhiyun int *slave_id)
1859*4882a593Smuzhiyun {
1860*4882a593Smuzhiyun struct mlx4_priv *priv = mlx4_priv(dev);
1861*4882a593Smuzhiyun int i, found_ix = -1;
1862*4882a593Smuzhiyun int vf_gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
1863*4882a593Smuzhiyun struct mlx4_slaves_pport slaves_pport;
1864*4882a593Smuzhiyun unsigned num_vfs;
1865*4882a593Smuzhiyun int slave_gid;
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun if (!mlx4_is_mfunc(dev))
1868*4882a593Smuzhiyun return -EINVAL;
1869*4882a593Smuzhiyun
1870*4882a593Smuzhiyun slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
1871*4882a593Smuzhiyun num_vfs = bitmap_weight(slaves_pport.slaves,
1872*4882a593Smuzhiyun dev->persist->num_vfs + 1) - 1;
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
1875*4882a593Smuzhiyun if (!memcmp(priv->port[port].gid_table.roce_gids[i].raw, gid,
1876*4882a593Smuzhiyun MLX4_ROCE_GID_ENTRY_SIZE)) {
1877*4882a593Smuzhiyun found_ix = i;
1878*4882a593Smuzhiyun break;
1879*4882a593Smuzhiyun }
1880*4882a593Smuzhiyun }
1881*4882a593Smuzhiyun
1882*4882a593Smuzhiyun if (found_ix >= 0) {
1883*4882a593Smuzhiyun /* Calculate a slave_gid which is the slave number in the gid
1884*4882a593Smuzhiyun * table and not a globally unique slave number.
1885*4882a593Smuzhiyun */
1886*4882a593Smuzhiyun if (found_ix < MLX4_ROCE_PF_GIDS)
1887*4882a593Smuzhiyun slave_gid = 0;
1888*4882a593Smuzhiyun else if (found_ix < MLX4_ROCE_PF_GIDS + (vf_gids % num_vfs) *
1889*4882a593Smuzhiyun (vf_gids / num_vfs + 1))
1890*4882a593Smuzhiyun slave_gid = ((found_ix - MLX4_ROCE_PF_GIDS) /
1891*4882a593Smuzhiyun (vf_gids / num_vfs + 1)) + 1;
1892*4882a593Smuzhiyun else
1893*4882a593Smuzhiyun slave_gid =
1894*4882a593Smuzhiyun ((found_ix - MLX4_ROCE_PF_GIDS -
1895*4882a593Smuzhiyun ((vf_gids % num_vfs) * ((vf_gids / num_vfs + 1)))) /
1896*4882a593Smuzhiyun (vf_gids / num_vfs)) + vf_gids % num_vfs + 1;
1897*4882a593Smuzhiyun
1898*4882a593Smuzhiyun /* Calculate the globally unique slave id */
1899*4882a593Smuzhiyun if (slave_gid) {
1900*4882a593Smuzhiyun struct mlx4_active_ports exclusive_ports;
1901*4882a593Smuzhiyun struct mlx4_active_ports actv_ports;
1902*4882a593Smuzhiyun struct mlx4_slaves_pport slaves_pport_actv;
1903*4882a593Smuzhiyun unsigned max_port_p_one;
1904*4882a593Smuzhiyun int num_vfs_before = 0;
1905*4882a593Smuzhiyun int candidate_slave_gid;
1906*4882a593Smuzhiyun
1907*4882a593Smuzhiyun /* Calculate how many VFs are on the previous port, if exists */
1908*4882a593Smuzhiyun for (i = 1; i < port; i++) {
1909*4882a593Smuzhiyun bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
1910*4882a593Smuzhiyun set_bit(i - 1, exclusive_ports.ports);
1911*4882a593Smuzhiyun slaves_pport_actv =
1912*4882a593Smuzhiyun mlx4_phys_to_slaves_pport_actv(
1913*4882a593Smuzhiyun dev, &exclusive_ports);
1914*4882a593Smuzhiyun num_vfs_before += bitmap_weight(
1915*4882a593Smuzhiyun slaves_pport_actv.slaves,
1916*4882a593Smuzhiyun dev->persist->num_vfs + 1);
1917*4882a593Smuzhiyun }
1918*4882a593Smuzhiyun
1919*4882a593Smuzhiyun /* candidate_slave_gid isn't necessarily the correct slave, but
1920*4882a593Smuzhiyun * it has the same number of ports and is assigned to the same
1921*4882a593Smuzhiyun * ports as the real slave we're looking for. On dual port VF,
1922*4882a593Smuzhiyun * slave_gid = [single port VFs on port <port>] +
1923*4882a593Smuzhiyun * [offset of the current slave from the first dual port VF] +
1924*4882a593Smuzhiyun * 1 (for the PF).
1925*4882a593Smuzhiyun */
1926*4882a593Smuzhiyun candidate_slave_gid = slave_gid + num_vfs_before;
1927*4882a593Smuzhiyun
1928*4882a593Smuzhiyun actv_ports = mlx4_get_active_ports(dev, candidate_slave_gid);
1929*4882a593Smuzhiyun max_port_p_one = find_first_bit(
1930*4882a593Smuzhiyun actv_ports.ports, dev->caps.num_ports) +
1931*4882a593Smuzhiyun bitmap_weight(actv_ports.ports,
1932*4882a593Smuzhiyun dev->caps.num_ports) + 1;
1933*4882a593Smuzhiyun
1934*4882a593Smuzhiyun /* Calculate the real slave number */
1935*4882a593Smuzhiyun for (i = 1; i < max_port_p_one; i++) {
1936*4882a593Smuzhiyun if (i == port)
1937*4882a593Smuzhiyun continue;
1938*4882a593Smuzhiyun bitmap_zero(exclusive_ports.ports,
1939*4882a593Smuzhiyun dev->caps.num_ports);
1940*4882a593Smuzhiyun set_bit(i - 1, exclusive_ports.ports);
1941*4882a593Smuzhiyun slaves_pport_actv =
1942*4882a593Smuzhiyun mlx4_phys_to_slaves_pport_actv(
1943*4882a593Smuzhiyun dev, &exclusive_ports);
1944*4882a593Smuzhiyun slave_gid += bitmap_weight(
1945*4882a593Smuzhiyun slaves_pport_actv.slaves,
1946*4882a593Smuzhiyun dev->persist->num_vfs + 1);
1947*4882a593Smuzhiyun }
1948*4882a593Smuzhiyun }
1949*4882a593Smuzhiyun *slave_id = slave_gid;
1950*4882a593Smuzhiyun }
1951*4882a593Smuzhiyun
1952*4882a593Smuzhiyun return (found_ix >= 0) ? 0 : -EINVAL;
1953*4882a593Smuzhiyun }
1954*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_get_slave_from_roce_gid);
1955*4882a593Smuzhiyun
mlx4_get_roce_gid_from_slave(struct mlx4_dev * dev,int port,int slave_id,u8 * gid)1956*4882a593Smuzhiyun int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1957*4882a593Smuzhiyun u8 *gid)
1958*4882a593Smuzhiyun {
1959*4882a593Smuzhiyun struct mlx4_priv *priv = mlx4_priv(dev);
1960*4882a593Smuzhiyun
1961*4882a593Smuzhiyun if (!mlx4_is_master(dev))
1962*4882a593Smuzhiyun return -EINVAL;
1963*4882a593Smuzhiyun
1964*4882a593Smuzhiyun memcpy(gid, priv->port[port].gid_table.roce_gids[slave_id].raw,
1965*4882a593Smuzhiyun MLX4_ROCE_GID_ENTRY_SIZE);
1966*4882a593Smuzhiyun return 0;
1967*4882a593Smuzhiyun }
1968*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_get_roce_gid_from_slave);
1969*4882a593Smuzhiyun
1970*4882a593Smuzhiyun /* Cable Module Info */
1971*4882a593Smuzhiyun #define MODULE_INFO_MAX_READ 48
1972*4882a593Smuzhiyun
1973*4882a593Smuzhiyun #define I2C_ADDR_LOW 0x50
1974*4882a593Smuzhiyun #define I2C_ADDR_HIGH 0x51
1975*4882a593Smuzhiyun #define I2C_PAGE_SIZE 256
1976*4882a593Smuzhiyun #define I2C_HIGH_PAGE_SIZE 128
1977*4882a593Smuzhiyun
1978*4882a593Smuzhiyun /* Module Info Data */
1979*4882a593Smuzhiyun struct mlx4_cable_info {
1980*4882a593Smuzhiyun u8 i2c_addr;
1981*4882a593Smuzhiyun u8 page_num;
1982*4882a593Smuzhiyun __be16 dev_mem_address;
1983*4882a593Smuzhiyun __be16 reserved1;
1984*4882a593Smuzhiyun __be16 size;
1985*4882a593Smuzhiyun __be32 reserved2[2];
1986*4882a593Smuzhiyun u8 data[MODULE_INFO_MAX_READ];
1987*4882a593Smuzhiyun };
1988*4882a593Smuzhiyun
1989*4882a593Smuzhiyun enum cable_info_err {
1990*4882a593Smuzhiyun CABLE_INF_INV_PORT = 0x1,
1991*4882a593Smuzhiyun CABLE_INF_OP_NOSUP = 0x2,
1992*4882a593Smuzhiyun CABLE_INF_NOT_CONN = 0x3,
1993*4882a593Smuzhiyun CABLE_INF_NO_EEPRM = 0x4,
1994*4882a593Smuzhiyun CABLE_INF_PAGE_ERR = 0x5,
1995*4882a593Smuzhiyun CABLE_INF_INV_ADDR = 0x6,
1996*4882a593Smuzhiyun CABLE_INF_I2C_ADDR = 0x7,
1997*4882a593Smuzhiyun CABLE_INF_QSFP_VIO = 0x8,
1998*4882a593Smuzhiyun CABLE_INF_I2C_BUSY = 0x9,
1999*4882a593Smuzhiyun };
2000*4882a593Smuzhiyun
2001*4882a593Smuzhiyun #define MAD_STATUS_2_CABLE_ERR(mad_status) ((mad_status >> 8) & 0xFF)
2002*4882a593Smuzhiyun
cable_info_mad_err_str(u16 mad_status)2003*4882a593Smuzhiyun static inline const char *cable_info_mad_err_str(u16 mad_status)
2004*4882a593Smuzhiyun {
2005*4882a593Smuzhiyun u8 err = MAD_STATUS_2_CABLE_ERR(mad_status);
2006*4882a593Smuzhiyun
2007*4882a593Smuzhiyun switch (err) {
2008*4882a593Smuzhiyun case CABLE_INF_INV_PORT:
2009*4882a593Smuzhiyun return "invalid port selected";
2010*4882a593Smuzhiyun case CABLE_INF_OP_NOSUP:
2011*4882a593Smuzhiyun return "operation not supported for this port (the port is of type CX4 or internal)";
2012*4882a593Smuzhiyun case CABLE_INF_NOT_CONN:
2013*4882a593Smuzhiyun return "cable is not connected";
2014*4882a593Smuzhiyun case CABLE_INF_NO_EEPRM:
2015*4882a593Smuzhiyun return "the connected cable has no EPROM (passive copper cable)";
2016*4882a593Smuzhiyun case CABLE_INF_PAGE_ERR:
2017*4882a593Smuzhiyun return "page number is greater than 15";
2018*4882a593Smuzhiyun case CABLE_INF_INV_ADDR:
2019*4882a593Smuzhiyun return "invalid device_address or size (that is, size equals 0 or address+size is greater than 256)";
2020*4882a593Smuzhiyun case CABLE_INF_I2C_ADDR:
2021*4882a593Smuzhiyun return "invalid I2C slave address";
2022*4882a593Smuzhiyun case CABLE_INF_QSFP_VIO:
2023*4882a593Smuzhiyun return "at least one cable violates the QSFP specification and ignores the modsel signal";
2024*4882a593Smuzhiyun case CABLE_INF_I2C_BUSY:
2025*4882a593Smuzhiyun return "I2C bus is constantly busy";
2026*4882a593Smuzhiyun }
2027*4882a593Smuzhiyun return "Unknown Error";
2028*4882a593Smuzhiyun }
2029*4882a593Smuzhiyun
mlx4_get_module_id(struct mlx4_dev * dev,u8 port,u8 * module_id)2030*4882a593Smuzhiyun static int mlx4_get_module_id(struct mlx4_dev *dev, u8 port, u8 *module_id)
2031*4882a593Smuzhiyun {
2032*4882a593Smuzhiyun struct mlx4_cmd_mailbox *inbox, *outbox;
2033*4882a593Smuzhiyun struct mlx4_mad_ifc *inmad, *outmad;
2034*4882a593Smuzhiyun struct mlx4_cable_info *cable_info;
2035*4882a593Smuzhiyun int ret;
2036*4882a593Smuzhiyun
2037*4882a593Smuzhiyun inbox = mlx4_alloc_cmd_mailbox(dev);
2038*4882a593Smuzhiyun if (IS_ERR(inbox))
2039*4882a593Smuzhiyun return PTR_ERR(inbox);
2040*4882a593Smuzhiyun
2041*4882a593Smuzhiyun outbox = mlx4_alloc_cmd_mailbox(dev);
2042*4882a593Smuzhiyun if (IS_ERR(outbox)) {
2043*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, inbox);
2044*4882a593Smuzhiyun return PTR_ERR(outbox);
2045*4882a593Smuzhiyun }
2046*4882a593Smuzhiyun
2047*4882a593Smuzhiyun inmad = (struct mlx4_mad_ifc *)(inbox->buf);
2048*4882a593Smuzhiyun outmad = (struct mlx4_mad_ifc *)(outbox->buf);
2049*4882a593Smuzhiyun
2050*4882a593Smuzhiyun inmad->method = 0x1; /* Get */
2051*4882a593Smuzhiyun inmad->class_version = 0x1;
2052*4882a593Smuzhiyun inmad->mgmt_class = 0x1;
2053*4882a593Smuzhiyun inmad->base_version = 0x1;
2054*4882a593Smuzhiyun inmad->attr_id = cpu_to_be16(0xFF60); /* Module Info */
2055*4882a593Smuzhiyun
2056*4882a593Smuzhiyun cable_info = (struct mlx4_cable_info *)inmad->data;
2057*4882a593Smuzhiyun cable_info->dev_mem_address = 0;
2058*4882a593Smuzhiyun cable_info->page_num = 0;
2059*4882a593Smuzhiyun cable_info->i2c_addr = I2C_ADDR_LOW;
2060*4882a593Smuzhiyun cable_info->size = cpu_to_be16(1);
2061*4882a593Smuzhiyun
2062*4882a593Smuzhiyun ret = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
2063*4882a593Smuzhiyun MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
2064*4882a593Smuzhiyun MLX4_CMD_NATIVE);
2065*4882a593Smuzhiyun if (ret)
2066*4882a593Smuzhiyun goto out;
2067*4882a593Smuzhiyun
2068*4882a593Smuzhiyun if (be16_to_cpu(outmad->status)) {
2069*4882a593Smuzhiyun /* Mad returned with bad status */
2070*4882a593Smuzhiyun ret = be16_to_cpu(outmad->status);
2071*4882a593Smuzhiyun mlx4_warn(dev,
2072*4882a593Smuzhiyun "MLX4_CMD_MAD_IFC Get Module ID attr(%x) port(%d) i2c_addr(%x) offset(%d) size(%d): Response Mad Status(%x) - %s\n",
2073*4882a593Smuzhiyun 0xFF60, port, I2C_ADDR_LOW, 0, 1, ret,
2074*4882a593Smuzhiyun cable_info_mad_err_str(ret));
2075*4882a593Smuzhiyun ret = -ret;
2076*4882a593Smuzhiyun goto out;
2077*4882a593Smuzhiyun }
2078*4882a593Smuzhiyun cable_info = (struct mlx4_cable_info *)outmad->data;
2079*4882a593Smuzhiyun *module_id = cable_info->data[0];
2080*4882a593Smuzhiyun out:
2081*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, inbox);
2082*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, outbox);
2083*4882a593Smuzhiyun return ret;
2084*4882a593Smuzhiyun }
2085*4882a593Smuzhiyun
mlx4_sfp_eeprom_params_set(u8 * i2c_addr,u8 * page_num,u16 * offset)2086*4882a593Smuzhiyun static void mlx4_sfp_eeprom_params_set(u8 *i2c_addr, u8 *page_num, u16 *offset)
2087*4882a593Smuzhiyun {
2088*4882a593Smuzhiyun *i2c_addr = I2C_ADDR_LOW;
2089*4882a593Smuzhiyun *page_num = 0;
2090*4882a593Smuzhiyun
2091*4882a593Smuzhiyun if (*offset < I2C_PAGE_SIZE)
2092*4882a593Smuzhiyun return;
2093*4882a593Smuzhiyun
2094*4882a593Smuzhiyun *i2c_addr = I2C_ADDR_HIGH;
2095*4882a593Smuzhiyun *offset -= I2C_PAGE_SIZE;
2096*4882a593Smuzhiyun }
2097*4882a593Smuzhiyun
mlx4_qsfp_eeprom_params_set(u8 * i2c_addr,u8 * page_num,u16 * offset)2098*4882a593Smuzhiyun static void mlx4_qsfp_eeprom_params_set(u8 *i2c_addr, u8 *page_num, u16 *offset)
2099*4882a593Smuzhiyun {
2100*4882a593Smuzhiyun /* Offsets 0-255 belong to page 0.
2101*4882a593Smuzhiyun * Offsets 256-639 belong to pages 01, 02, 03.
2102*4882a593Smuzhiyun * For example, offset 400 is page 02: 1 + (400 - 256) / 128 = 2
2103*4882a593Smuzhiyun */
2104*4882a593Smuzhiyun if (*offset < I2C_PAGE_SIZE)
2105*4882a593Smuzhiyun *page_num = 0;
2106*4882a593Smuzhiyun else
2107*4882a593Smuzhiyun *page_num = 1 + (*offset - I2C_PAGE_SIZE) / I2C_HIGH_PAGE_SIZE;
2108*4882a593Smuzhiyun *i2c_addr = I2C_ADDR_LOW;
2109*4882a593Smuzhiyun *offset -= *page_num * I2C_HIGH_PAGE_SIZE;
2110*4882a593Smuzhiyun }
2111*4882a593Smuzhiyun
2112*4882a593Smuzhiyun /**
2113*4882a593Smuzhiyun * mlx4_get_module_info - Read cable module eeprom data
2114*4882a593Smuzhiyun * @dev: mlx4_dev.
2115*4882a593Smuzhiyun * @port: port number.
2116*4882a593Smuzhiyun * @offset: byte offset in eeprom to start reading data from.
2117*4882a593Smuzhiyun * @size: num of bytes to read.
2118*4882a593Smuzhiyun * @data: output buffer to put the requested data into.
2119*4882a593Smuzhiyun *
2120*4882a593Smuzhiyun * Reads cable module eeprom data, puts the outcome data into
2121*4882a593Smuzhiyun * data pointer paramer.
2122*4882a593Smuzhiyun * Returns num of read bytes on success or a negative error
2123*4882a593Smuzhiyun * code.
2124*4882a593Smuzhiyun */
mlx4_get_module_info(struct mlx4_dev * dev,u8 port,u16 offset,u16 size,u8 * data)2125*4882a593Smuzhiyun int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
2126*4882a593Smuzhiyun u16 offset, u16 size, u8 *data)
2127*4882a593Smuzhiyun {
2128*4882a593Smuzhiyun struct mlx4_cmd_mailbox *inbox, *outbox;
2129*4882a593Smuzhiyun struct mlx4_mad_ifc *inmad, *outmad;
2130*4882a593Smuzhiyun struct mlx4_cable_info *cable_info;
2131*4882a593Smuzhiyun u8 module_id, i2c_addr, page_num;
2132*4882a593Smuzhiyun int ret;
2133*4882a593Smuzhiyun
2134*4882a593Smuzhiyun if (size > MODULE_INFO_MAX_READ)
2135*4882a593Smuzhiyun size = MODULE_INFO_MAX_READ;
2136*4882a593Smuzhiyun
2137*4882a593Smuzhiyun ret = mlx4_get_module_id(dev, port, &module_id);
2138*4882a593Smuzhiyun if (ret)
2139*4882a593Smuzhiyun return ret;
2140*4882a593Smuzhiyun
2141*4882a593Smuzhiyun switch (module_id) {
2142*4882a593Smuzhiyun case MLX4_MODULE_ID_SFP:
2143*4882a593Smuzhiyun mlx4_sfp_eeprom_params_set(&i2c_addr, &page_num, &offset);
2144*4882a593Smuzhiyun break;
2145*4882a593Smuzhiyun case MLX4_MODULE_ID_QSFP:
2146*4882a593Smuzhiyun case MLX4_MODULE_ID_QSFP_PLUS:
2147*4882a593Smuzhiyun case MLX4_MODULE_ID_QSFP28:
2148*4882a593Smuzhiyun mlx4_qsfp_eeprom_params_set(&i2c_addr, &page_num, &offset);
2149*4882a593Smuzhiyun break;
2150*4882a593Smuzhiyun default:
2151*4882a593Smuzhiyun mlx4_err(dev, "Module ID not recognized: %#x\n", module_id);
2152*4882a593Smuzhiyun return -EINVAL;
2153*4882a593Smuzhiyun }
2154*4882a593Smuzhiyun
2155*4882a593Smuzhiyun inbox = mlx4_alloc_cmd_mailbox(dev);
2156*4882a593Smuzhiyun if (IS_ERR(inbox))
2157*4882a593Smuzhiyun return PTR_ERR(inbox);
2158*4882a593Smuzhiyun
2159*4882a593Smuzhiyun outbox = mlx4_alloc_cmd_mailbox(dev);
2160*4882a593Smuzhiyun if (IS_ERR(outbox)) {
2161*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, inbox);
2162*4882a593Smuzhiyun return PTR_ERR(outbox);
2163*4882a593Smuzhiyun }
2164*4882a593Smuzhiyun
2165*4882a593Smuzhiyun inmad = (struct mlx4_mad_ifc *)(inbox->buf);
2166*4882a593Smuzhiyun outmad = (struct mlx4_mad_ifc *)(outbox->buf);
2167*4882a593Smuzhiyun
2168*4882a593Smuzhiyun inmad->method = 0x1; /* Get */
2169*4882a593Smuzhiyun inmad->class_version = 0x1;
2170*4882a593Smuzhiyun inmad->mgmt_class = 0x1;
2171*4882a593Smuzhiyun inmad->base_version = 0x1;
2172*4882a593Smuzhiyun inmad->attr_id = cpu_to_be16(0xFF60); /* Module Info */
2173*4882a593Smuzhiyun
2174*4882a593Smuzhiyun if (offset < I2C_PAGE_SIZE && offset + size > I2C_PAGE_SIZE)
2175*4882a593Smuzhiyun /* Cross pages reads are not allowed
2176*4882a593Smuzhiyun * read until offset 256 in low page
2177*4882a593Smuzhiyun */
2178*4882a593Smuzhiyun size -= offset + size - I2C_PAGE_SIZE;
2179*4882a593Smuzhiyun
2180*4882a593Smuzhiyun cable_info = (struct mlx4_cable_info *)inmad->data;
2181*4882a593Smuzhiyun cable_info->dev_mem_address = cpu_to_be16(offset);
2182*4882a593Smuzhiyun cable_info->page_num = page_num;
2183*4882a593Smuzhiyun cable_info->i2c_addr = i2c_addr;
2184*4882a593Smuzhiyun cable_info->size = cpu_to_be16(size);
2185*4882a593Smuzhiyun
2186*4882a593Smuzhiyun ret = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
2187*4882a593Smuzhiyun MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
2188*4882a593Smuzhiyun MLX4_CMD_NATIVE);
2189*4882a593Smuzhiyun if (ret)
2190*4882a593Smuzhiyun goto out;
2191*4882a593Smuzhiyun
2192*4882a593Smuzhiyun if (be16_to_cpu(outmad->status)) {
2193*4882a593Smuzhiyun /* Mad returned with bad status */
2194*4882a593Smuzhiyun ret = be16_to_cpu(outmad->status);
2195*4882a593Smuzhiyun mlx4_warn(dev,
2196*4882a593Smuzhiyun "MLX4_CMD_MAD_IFC Get Module info attr(%x) port(%d) i2c_addr(%x) offset(%d) size(%d): Response Mad Status(%x) - %s\n",
2197*4882a593Smuzhiyun 0xFF60, port, i2c_addr, offset, size,
2198*4882a593Smuzhiyun ret, cable_info_mad_err_str(ret));
2199*4882a593Smuzhiyun
2200*4882a593Smuzhiyun if (i2c_addr == I2C_ADDR_HIGH &&
2201*4882a593Smuzhiyun MAD_STATUS_2_CABLE_ERR(ret) == CABLE_INF_I2C_ADDR)
2202*4882a593Smuzhiyun /* Some SFP cables do not support i2c slave
2203*4882a593Smuzhiyun * address 0x51 (high page), abort silently.
2204*4882a593Smuzhiyun */
2205*4882a593Smuzhiyun ret = 0;
2206*4882a593Smuzhiyun else
2207*4882a593Smuzhiyun ret = -ret;
2208*4882a593Smuzhiyun goto out;
2209*4882a593Smuzhiyun }
2210*4882a593Smuzhiyun cable_info = (struct mlx4_cable_info *)outmad->data;
2211*4882a593Smuzhiyun memcpy(data, cable_info->data, size);
2212*4882a593Smuzhiyun ret = size;
2213*4882a593Smuzhiyun out:
2214*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, inbox);
2215*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, outbox);
2216*4882a593Smuzhiyun return ret;
2217*4882a593Smuzhiyun }
2218*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_get_module_info);
2219*4882a593Smuzhiyun
mlx4_max_tc(struct mlx4_dev * dev)2220*4882a593Smuzhiyun int mlx4_max_tc(struct mlx4_dev *dev)
2221*4882a593Smuzhiyun {
2222*4882a593Smuzhiyun u8 num_tc = dev->caps.max_tc_eth;
2223*4882a593Smuzhiyun
2224*4882a593Smuzhiyun if (!num_tc)
2225*4882a593Smuzhiyun num_tc = MLX4_TC_MAX_NUMBER;
2226*4882a593Smuzhiyun
2227*4882a593Smuzhiyun return num_tc;
2228*4882a593Smuzhiyun }
2229*4882a593Smuzhiyun EXPORT_SYMBOL(mlx4_max_tc);
2230