1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _MLX4_STATS_ 3*4882a593Smuzhiyun #define _MLX4_STATS_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifdef MLX4_EN_PERF_STAT 6*4882a593Smuzhiyun #define NUM_PERF_STATS NUM_PERF_COUNTERS 7*4882a593Smuzhiyun #else 8*4882a593Smuzhiyun #define NUM_PERF_STATS 0 9*4882a593Smuzhiyun #endif 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define NUM_PRIORITIES 9 12*4882a593Smuzhiyun #define NUM_PRIORITY_STATS 2 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct mlx4_en_pkt_stats { 15*4882a593Smuzhiyun unsigned long rx_multicast_packets; 16*4882a593Smuzhiyun unsigned long rx_broadcast_packets; 17*4882a593Smuzhiyun unsigned long rx_jabbers; 18*4882a593Smuzhiyun unsigned long rx_in_range_length_error; 19*4882a593Smuzhiyun unsigned long rx_out_range_length_error; 20*4882a593Smuzhiyun unsigned long tx_multicast_packets; 21*4882a593Smuzhiyun unsigned long tx_broadcast_packets; 22*4882a593Smuzhiyun unsigned long rx_prio[NUM_PRIORITIES][NUM_PRIORITY_STATS]; 23*4882a593Smuzhiyun unsigned long tx_prio[NUM_PRIORITIES][NUM_PRIORITY_STATS]; 24*4882a593Smuzhiyun #define NUM_PKT_STATS 43 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct mlx4_en_counter_stats { 28*4882a593Smuzhiyun unsigned long rx_packets; 29*4882a593Smuzhiyun unsigned long rx_bytes; 30*4882a593Smuzhiyun unsigned long tx_packets; 31*4882a593Smuzhiyun unsigned long tx_bytes; 32*4882a593Smuzhiyun #define NUM_PF_STATS 4 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct mlx4_en_port_stats { 36*4882a593Smuzhiyun unsigned long tso_packets; 37*4882a593Smuzhiyun unsigned long xmit_more; 38*4882a593Smuzhiyun unsigned long queue_stopped; 39*4882a593Smuzhiyun unsigned long wake_queue; 40*4882a593Smuzhiyun unsigned long tx_timeout; 41*4882a593Smuzhiyun unsigned long rx_alloc_pages; 42*4882a593Smuzhiyun unsigned long rx_chksum_good; 43*4882a593Smuzhiyun unsigned long rx_chksum_none; 44*4882a593Smuzhiyun unsigned long rx_chksum_complete; 45*4882a593Smuzhiyun unsigned long tx_chksum_offload; 46*4882a593Smuzhiyun #define NUM_PORT_STATS 10 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct mlx4_en_perf_stats { 50*4882a593Smuzhiyun u32 tx_poll; 51*4882a593Smuzhiyun u64 tx_pktsz_avg; 52*4882a593Smuzhiyun u32 inflight_avg; 53*4882a593Smuzhiyun u16 tx_coal_avg; 54*4882a593Smuzhiyun u16 rx_coal_avg; 55*4882a593Smuzhiyun u32 napi_quota; 56*4882a593Smuzhiyun #define NUM_PERF_COUNTERS 6 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct mlx4_en_xdp_stats { 60*4882a593Smuzhiyun unsigned long rx_xdp_drop; 61*4882a593Smuzhiyun unsigned long rx_xdp_tx; 62*4882a593Smuzhiyun unsigned long rx_xdp_tx_full; 63*4882a593Smuzhiyun #define NUM_XDP_STATS 3 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct mlx4_en_phy_stats { 67*4882a593Smuzhiyun unsigned long rx_packets_phy; 68*4882a593Smuzhiyun unsigned long rx_bytes_phy; 69*4882a593Smuzhiyun unsigned long tx_packets_phy; 70*4882a593Smuzhiyun unsigned long tx_bytes_phy; 71*4882a593Smuzhiyun #define NUM_PHY_STATS 4 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define NUM_MAIN_STATS 21 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define MLX4_NUM_PRIORITIES 8 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct mlx4_en_flow_stats_rx { 79*4882a593Smuzhiyun u64 rx_pause; 80*4882a593Smuzhiyun u64 rx_pause_duration; 81*4882a593Smuzhiyun u64 rx_pause_transition; 82*4882a593Smuzhiyun #define NUM_FLOW_STATS_RX 3 83*4882a593Smuzhiyun #define NUM_FLOW_PRIORITY_STATS_RX (NUM_FLOW_STATS_RX * \ 84*4882a593Smuzhiyun MLX4_NUM_PRIORITIES) 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define FLOW_PRIORITY_STATS_IDX_RX_FRAMES (NUM_MAIN_STATS + \ 88*4882a593Smuzhiyun NUM_PORT_STATS + \ 89*4882a593Smuzhiyun NUM_PF_STATS + \ 90*4882a593Smuzhiyun NUM_FLOW_PRIORITY_STATS_RX) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct mlx4_en_flow_stats_tx { 93*4882a593Smuzhiyun u64 tx_pause; 94*4882a593Smuzhiyun u64 tx_pause_duration; 95*4882a593Smuzhiyun u64 tx_pause_transition; 96*4882a593Smuzhiyun #define NUM_FLOW_STATS_TX 3 97*4882a593Smuzhiyun #define NUM_FLOW_PRIORITY_STATS_TX (NUM_FLOW_STATS_TX * \ 98*4882a593Smuzhiyun MLX4_NUM_PRIORITIES) 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define FLOW_PRIORITY_STATS_IDX_TX_FRAMES (NUM_MAIN_STATS + \ 102*4882a593Smuzhiyun NUM_PORT_STATS + \ 103*4882a593Smuzhiyun NUM_PF_STATS + \ 104*4882a593Smuzhiyun NUM_FLOW_PRIORITY_STATS_RX + \ 105*4882a593Smuzhiyun NUM_FLOW_STATS_RX + \ 106*4882a593Smuzhiyun NUM_FLOW_PRIORITY_STATS_TX) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define NUM_FLOW_STATS (NUM_FLOW_STATS_RX + NUM_FLOW_STATS_TX + \ 109*4882a593Smuzhiyun NUM_FLOW_PRIORITY_STATS_TX + \ 110*4882a593Smuzhiyun NUM_FLOW_PRIORITY_STATS_RX) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct mlx4_en_stat_out_flow_control_mbox { 113*4882a593Smuzhiyun /* Total number of PAUSE frames received from the far-end port */ 114*4882a593Smuzhiyun __be64 rx_pause; 115*4882a593Smuzhiyun /* Total number of microseconds that far-end port requested to pause 116*4882a593Smuzhiyun * transmission of packets 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun __be64 rx_pause_duration; 119*4882a593Smuzhiyun /* Number of received transmission from XOFF state to XON state */ 120*4882a593Smuzhiyun __be64 rx_pause_transition; 121*4882a593Smuzhiyun /* Total number of PAUSE frames sent from the far-end port */ 122*4882a593Smuzhiyun __be64 tx_pause; 123*4882a593Smuzhiyun /* Total time in microseconds that transmission of packets has been 124*4882a593Smuzhiyun * paused 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun __be64 tx_pause_duration; 127*4882a593Smuzhiyun /* Number of transmitter transitions from XOFF state to XON state */ 128*4882a593Smuzhiyun __be64 tx_pause_transition; 129*4882a593Smuzhiyun /* Reserverd */ 130*4882a593Smuzhiyun __be64 reserved[2]; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun enum { 134*4882a593Smuzhiyun MLX4_DUMP_ETH_STATS_FLOW_CONTROL = 1 << 12 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define NUM_ALL_STATS (NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PKT_STATS + \ 138*4882a593Smuzhiyun NUM_FLOW_STATS + NUM_PERF_STATS + NUM_PF_STATS + \ 139*4882a593Smuzhiyun NUM_XDP_STATS + NUM_PHY_STATS) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define MLX4_FIND_NETDEV_STAT(n) (offsetof(struct net_device_stats, n) / \ 142*4882a593Smuzhiyun sizeof(((struct net_device_stats *)0)->n)) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #endif 145