1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This software is available to you under a choice of one of two
6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
9*4882a593Smuzhiyun * OpenIB.org BSD license below:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
12*4882a593Smuzhiyun * without modification, are permitted provided that the following
13*4882a593Smuzhiyun * conditions are met:
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * - Redistributions of source code must retain the above
16*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
17*4882a593Smuzhiyun * disclaimer.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
20*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
21*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
22*4882a593Smuzhiyun * provided with the distribution.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31*4882a593Smuzhiyun * SOFTWARE.
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #ifndef MLX4_ICM_H
35*4882a593Smuzhiyun #define MLX4_ICM_H
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include <linux/list.h>
38*4882a593Smuzhiyun #include <linux/pci.h>
39*4882a593Smuzhiyun #include <linux/mutex.h>
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define MLX4_ICM_CHUNK_LEN \
42*4882a593Smuzhiyun ((256 - sizeof(struct list_head) - 2 * sizeof(int)) / \
43*4882a593Smuzhiyun (sizeof(struct scatterlist)))
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun enum {
46*4882a593Smuzhiyun MLX4_ICM_PAGE_SHIFT = 12,
47*4882a593Smuzhiyun MLX4_ICM_PAGE_SIZE = 1 << MLX4_ICM_PAGE_SHIFT,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun struct mlx4_icm_buf {
51*4882a593Smuzhiyun void *addr;
52*4882a593Smuzhiyun size_t size;
53*4882a593Smuzhiyun dma_addr_t dma_addr;
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun struct mlx4_icm_chunk {
57*4882a593Smuzhiyun struct list_head list;
58*4882a593Smuzhiyun int npages;
59*4882a593Smuzhiyun int nsg;
60*4882a593Smuzhiyun bool coherent;
61*4882a593Smuzhiyun union {
62*4882a593Smuzhiyun struct scatterlist sg[MLX4_ICM_CHUNK_LEN];
63*4882a593Smuzhiyun struct mlx4_icm_buf buf[MLX4_ICM_CHUNK_LEN];
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct mlx4_icm {
68*4882a593Smuzhiyun struct list_head chunk_list;
69*4882a593Smuzhiyun int refcount;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct mlx4_icm_iter {
73*4882a593Smuzhiyun struct mlx4_icm *icm;
74*4882a593Smuzhiyun struct mlx4_icm_chunk *chunk;
75*4882a593Smuzhiyun int page_idx;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun struct mlx4_dev;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun struct mlx4_icm *mlx4_alloc_icm(struct mlx4_dev *dev, int npages,
81*4882a593Smuzhiyun gfp_t gfp_mask, int coherent);
82*4882a593Smuzhiyun void mlx4_free_icm(struct mlx4_dev *dev, struct mlx4_icm *icm, int coherent);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun int mlx4_table_get(struct mlx4_dev *dev, struct mlx4_icm_table *table, u32 obj);
85*4882a593Smuzhiyun void mlx4_table_put(struct mlx4_dev *dev, struct mlx4_icm_table *table, u32 obj);
86*4882a593Smuzhiyun int mlx4_table_get_range(struct mlx4_dev *dev, struct mlx4_icm_table *table,
87*4882a593Smuzhiyun u32 start, u32 end);
88*4882a593Smuzhiyun void mlx4_table_put_range(struct mlx4_dev *dev, struct mlx4_icm_table *table,
89*4882a593Smuzhiyun u32 start, u32 end);
90*4882a593Smuzhiyun int mlx4_init_icm_table(struct mlx4_dev *dev, struct mlx4_icm_table *table,
91*4882a593Smuzhiyun u64 virt, int obj_size, u32 nobj, int reserved,
92*4882a593Smuzhiyun int use_lowmem, int use_coherent);
93*4882a593Smuzhiyun void mlx4_cleanup_icm_table(struct mlx4_dev *dev, struct mlx4_icm_table *table);
94*4882a593Smuzhiyun void *mlx4_table_find(struct mlx4_icm_table *table, u32 obj, dma_addr_t *dma_handle);
95*4882a593Smuzhiyun
mlx4_icm_first(struct mlx4_icm * icm,struct mlx4_icm_iter * iter)96*4882a593Smuzhiyun static inline void mlx4_icm_first(struct mlx4_icm *icm,
97*4882a593Smuzhiyun struct mlx4_icm_iter *iter)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun iter->icm = icm;
100*4882a593Smuzhiyun iter->chunk = list_empty(&icm->chunk_list) ?
101*4882a593Smuzhiyun NULL : list_entry(icm->chunk_list.next,
102*4882a593Smuzhiyun struct mlx4_icm_chunk, list);
103*4882a593Smuzhiyun iter->page_idx = 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
mlx4_icm_last(struct mlx4_icm_iter * iter)106*4882a593Smuzhiyun static inline int mlx4_icm_last(struct mlx4_icm_iter *iter)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun return !iter->chunk;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
mlx4_icm_next(struct mlx4_icm_iter * iter)111*4882a593Smuzhiyun static inline void mlx4_icm_next(struct mlx4_icm_iter *iter)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun if (++iter->page_idx >= iter->chunk->nsg) {
114*4882a593Smuzhiyun if (iter->chunk->list.next == &iter->icm->chunk_list) {
115*4882a593Smuzhiyun iter->chunk = NULL;
116*4882a593Smuzhiyun return;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun iter->chunk = list_entry(iter->chunk->list.next,
120*4882a593Smuzhiyun struct mlx4_icm_chunk, list);
121*4882a593Smuzhiyun iter->page_idx = 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
mlx4_icm_addr(struct mlx4_icm_iter * iter)125*4882a593Smuzhiyun static inline dma_addr_t mlx4_icm_addr(struct mlx4_icm_iter *iter)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun if (iter->chunk->coherent)
128*4882a593Smuzhiyun return iter->chunk->buf[iter->page_idx].dma_addr;
129*4882a593Smuzhiyun else
130*4882a593Smuzhiyun return sg_dma_address(&iter->chunk->sg[iter->page_idx]);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
mlx4_icm_size(struct mlx4_icm_iter * iter)133*4882a593Smuzhiyun static inline unsigned long mlx4_icm_size(struct mlx4_icm_iter *iter)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun if (iter->chunk->coherent)
136*4882a593Smuzhiyun return iter->chunk->buf[iter->page_idx].size;
137*4882a593Smuzhiyun else
138*4882a593Smuzhiyun return sg_dma_len(&iter->chunk->sg[iter->page_idx]);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
142*4882a593Smuzhiyun int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #endif /* MLX4_ICM_H */
145