1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3*4882a593Smuzhiyun * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. 4*4882a593Smuzhiyun * All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This software is available to you under a choice of one of two 7*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 8*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 9*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 10*4882a593Smuzhiyun * OpenIB.org BSD license below: 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 13*4882a593Smuzhiyun * without modification, are permitted provided that the following 14*4882a593Smuzhiyun * conditions are met: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * - Redistributions of source code must retain the above 17*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 18*4882a593Smuzhiyun * disclaimer. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 21*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 22*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 23*4882a593Smuzhiyun * provided with the distribution. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32*4882a593Smuzhiyun * SOFTWARE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef MLX4_FW_QOS_H 36*4882a593Smuzhiyun #define MLX4_FW_QOS_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #include <linux/mlx4/cmd.h> 39*4882a593Smuzhiyun #include <linux/mlx4/device.h> 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MLX4_NUM_UP 8 42*4882a593Smuzhiyun #define MLX4_NUM_TC 8 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Default supported priorities for VPP allocation */ 45*4882a593Smuzhiyun #define MLX4_DEFAULT_QOS_PRIO (0) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Derived from FW feature definition, 0 is the default vport fo all QPs */ 48*4882a593Smuzhiyun #define MLX4_VPP_DEFAULT_VPORT (0) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct mlx4_vport_qos_param { 51*4882a593Smuzhiyun u32 bw_share; 52*4882a593Smuzhiyun u32 max_avg_bw; 53*4882a593Smuzhiyun u8 enable; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /** 57*4882a593Smuzhiyun * mlx4_SET_PORT_PRIO2TC - This routine maps user priorities to traffic 58*4882a593Smuzhiyun * classes of a given port and device. 59*4882a593Smuzhiyun * 60*4882a593Smuzhiyun * @dev: mlx4_dev. 61*4882a593Smuzhiyun * @port: Physical port number. 62*4882a593Smuzhiyun * @prio2tc: Array of TC associated with each priorities. 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun * Returns 0 on success or a negative mlx4_core errno code. 65*4882a593Smuzhiyun **/ 66*4882a593Smuzhiyun int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /** 69*4882a593Smuzhiyun * mlx4_SET_PORT_SCHEDULER - This routine configures the arbitration between 70*4882a593Smuzhiyun * traffic classes (ETS) and configured rate limit for traffic classes. 71*4882a593Smuzhiyun * tc_tx_bw, pg and ratelimit are arrays where each index represents a TC. 72*4882a593Smuzhiyun * The description for those parameters below refers to a single TC. 73*4882a593Smuzhiyun * 74*4882a593Smuzhiyun * @dev: mlx4_dev. 75*4882a593Smuzhiyun * @port: Physical port number. 76*4882a593Smuzhiyun * @tc_tx_bw: The percentage of the bandwidth allocated for traffic class 77*4882a593Smuzhiyun * within a TC group. The sum of the bw_percentage of all the traffic 78*4882a593Smuzhiyun * classes within a TC group must equal 100% for correct operation. 79*4882a593Smuzhiyun * @pg: The TC group the traffic class is associated with. 80*4882a593Smuzhiyun * @ratelimit: The maximal bandwidth allowed for the use by this traffic class. 81*4882a593Smuzhiyun * 82*4882a593Smuzhiyun * Returns 0 on success or a negative mlx4_core errno code. 83*4882a593Smuzhiyun **/ 84*4882a593Smuzhiyun int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 85*4882a593Smuzhiyun u8 *pg, u16 *ratelimit); 86*4882a593Smuzhiyun /** 87*4882a593Smuzhiyun * mlx4_ALLOCATE_VPP_get - Query port VPP available resources and allocation. 88*4882a593Smuzhiyun * Before distribution of VPPs to priorities, only available_vpp is returned. 89*4882a593Smuzhiyun * After initialization it returns the distribution of VPPs among priorities. 90*4882a593Smuzhiyun * 91*4882a593Smuzhiyun * @dev: mlx4_dev. 92*4882a593Smuzhiyun * @port: Physical port number. 93*4882a593Smuzhiyun * @available_vpp: Pointer to variable where number of available VPPs is stored 94*4882a593Smuzhiyun * @vpp_p_up: Distribution of VPPs to priorities is stored in this array 95*4882a593Smuzhiyun * 96*4882a593Smuzhiyun * Returns 0 on success or a negative mlx4_core errno code. 97*4882a593Smuzhiyun **/ 98*4882a593Smuzhiyun int mlx4_ALLOCATE_VPP_get(struct mlx4_dev *dev, u8 port, 99*4882a593Smuzhiyun u16 *available_vpp, u8 *vpp_p_up); 100*4882a593Smuzhiyun /** 101*4882a593Smuzhiyun * mlx4_ALLOCATE_VPP_set - Distribution of VPPs among differnt priorities. 102*4882a593Smuzhiyun * The total number of VPPs assigned to all for a port must not exceed 103*4882a593Smuzhiyun * the value reported by available_vpp in mlx4_ALLOCATE_VPP_get. 104*4882a593Smuzhiyun * VPP allocation is allowed only after the port type has been set, 105*4882a593Smuzhiyun * and while no QPs are open for this port. 106*4882a593Smuzhiyun * 107*4882a593Smuzhiyun * @dev: mlx4_dev. 108*4882a593Smuzhiyun * @port: Physical port number. 109*4882a593Smuzhiyun * @vpp_p_up: Allocation of VPPs to different priorities. 110*4882a593Smuzhiyun * 111*4882a593Smuzhiyun * Returns 0 on success or a negative mlx4_core errno code. 112*4882a593Smuzhiyun **/ 113*4882a593Smuzhiyun int mlx4_ALLOCATE_VPP_set(struct mlx4_dev *dev, u8 port, u8 *vpp_p_up); 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /** 116*4882a593Smuzhiyun * mlx4_SET_VPORT_QOS_get - Query QoS proporties of a Vport. 117*4882a593Smuzhiyun * Each priority allowed for the Vport is assigned with a share of the BW, 118*4882a593Smuzhiyun * and a BW limitation. This commands query the current QoS values. 119*4882a593Smuzhiyun * 120*4882a593Smuzhiyun * @dev: mlx4_dev. 121*4882a593Smuzhiyun * @port: Physical port number. 122*4882a593Smuzhiyun * @vport: Vport id. 123*4882a593Smuzhiyun * @out_param: Array of mlx4_vport_qos_param that will contain the values. 124*4882a593Smuzhiyun * 125*4882a593Smuzhiyun * Returns 0 on success or a negative mlx4_core errno code. 126*4882a593Smuzhiyun **/ 127*4882a593Smuzhiyun int mlx4_SET_VPORT_QOS_get(struct mlx4_dev *dev, u8 port, u8 vport, 128*4882a593Smuzhiyun struct mlx4_vport_qos_param *out_param); 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /** 131*4882a593Smuzhiyun * mlx4_SET_VPORT_QOS_set - Set QoS proporties of a Vport. 132*4882a593Smuzhiyun * QoS parameters can be modified at any time, but must be initialized 133*4882a593Smuzhiyun * before any QP is associated with the VPort. 134*4882a593Smuzhiyun * 135*4882a593Smuzhiyun * @dev: mlx4_dev. 136*4882a593Smuzhiyun * @port: Physical port number. 137*4882a593Smuzhiyun * @vport: Vport id. 138*4882a593Smuzhiyun * @out_param: Array of mlx4_vport_qos_param which holds the requested values. 139*4882a593Smuzhiyun * 140*4882a593Smuzhiyun * Returns 0 on success or a negative mlx4_core errno code. 141*4882a593Smuzhiyun **/ 142*4882a593Smuzhiyun int mlx4_SET_VPORT_QOS_set(struct mlx4_dev *dev, u8 port, u8 vport, 143*4882a593Smuzhiyun struct mlx4_vport_qos_param *in_param); 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #endif /* MLX4_FW_QOS_H */ 146