1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3*4882a593Smuzhiyun * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4*4882a593Smuzhiyun * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This software is available to you under a choice of one of two 7*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 8*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 9*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 10*4882a593Smuzhiyun * OpenIB.org BSD license below: 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 13*4882a593Smuzhiyun * without modification, are permitted provided that the following 14*4882a593Smuzhiyun * conditions are met: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * - Redistributions of source code must retain the above 17*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 18*4882a593Smuzhiyun * disclaimer. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 21*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 22*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 23*4882a593Smuzhiyun * provided with the distribution. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32*4882a593Smuzhiyun * SOFTWARE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef MLX4_FW_H 36*4882a593Smuzhiyun #define MLX4_FW_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #include "mlx4.h" 39*4882a593Smuzhiyun #include "icm.h" 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct mlx4_mod_stat_cfg { 42*4882a593Smuzhiyun u8 log_pg_sz; 43*4882a593Smuzhiyun u8 log_pg_sz_m; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct mlx4_port_cap { 47*4882a593Smuzhiyun u8 link_state; 48*4882a593Smuzhiyun u8 supported_port_types; 49*4882a593Smuzhiyun u8 suggested_type; 50*4882a593Smuzhiyun u8 default_sense; 51*4882a593Smuzhiyun u8 log_max_macs; 52*4882a593Smuzhiyun u8 log_max_vlans; 53*4882a593Smuzhiyun int ib_mtu; 54*4882a593Smuzhiyun int max_port_width; 55*4882a593Smuzhiyun int max_vl; 56*4882a593Smuzhiyun int max_tc_eth; 57*4882a593Smuzhiyun int max_gids; 58*4882a593Smuzhiyun int max_pkeys; 59*4882a593Smuzhiyun u64 def_mac; 60*4882a593Smuzhiyun u16 eth_mtu; 61*4882a593Smuzhiyun int trans_type; 62*4882a593Smuzhiyun int vendor_oui; 63*4882a593Smuzhiyun u16 wavelength; 64*4882a593Smuzhiyun u64 trans_code; 65*4882a593Smuzhiyun u8 dmfs_optimized_state; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct mlx4_dev_cap { 69*4882a593Smuzhiyun int max_srq_sz; 70*4882a593Smuzhiyun int max_qp_sz; 71*4882a593Smuzhiyun int reserved_qps; 72*4882a593Smuzhiyun int max_qps; 73*4882a593Smuzhiyun int reserved_srqs; 74*4882a593Smuzhiyun int max_srqs; 75*4882a593Smuzhiyun int max_cq_sz; 76*4882a593Smuzhiyun int reserved_cqs; 77*4882a593Smuzhiyun int max_cqs; 78*4882a593Smuzhiyun int max_mpts; 79*4882a593Smuzhiyun int reserved_eqs; 80*4882a593Smuzhiyun int max_eqs; 81*4882a593Smuzhiyun int num_sys_eqs; 82*4882a593Smuzhiyun int reserved_mtts; 83*4882a593Smuzhiyun int reserved_mrws; 84*4882a593Smuzhiyun int max_requester_per_qp; 85*4882a593Smuzhiyun int max_responder_per_qp; 86*4882a593Smuzhiyun int max_rdma_global; 87*4882a593Smuzhiyun int local_ca_ack_delay; 88*4882a593Smuzhiyun int num_ports; 89*4882a593Smuzhiyun u32 max_msg_sz; 90*4882a593Smuzhiyun u16 stat_rate_support; 91*4882a593Smuzhiyun int fs_log_max_ucast_qp_range_size; 92*4882a593Smuzhiyun int fs_max_num_qp_per_entry; 93*4882a593Smuzhiyun u64 flags; 94*4882a593Smuzhiyun u64 flags2; 95*4882a593Smuzhiyun int reserved_uars; 96*4882a593Smuzhiyun int uar_size; 97*4882a593Smuzhiyun int min_page_sz; 98*4882a593Smuzhiyun int bf_reg_size; 99*4882a593Smuzhiyun int bf_regs_per_page; 100*4882a593Smuzhiyun int max_sq_sg; 101*4882a593Smuzhiyun int max_sq_desc_sz; 102*4882a593Smuzhiyun int max_rq_sg; 103*4882a593Smuzhiyun int max_rq_desc_sz; 104*4882a593Smuzhiyun int max_qp_per_mcg; 105*4882a593Smuzhiyun int reserved_mgms; 106*4882a593Smuzhiyun int max_mcgs; 107*4882a593Smuzhiyun int reserved_pds; 108*4882a593Smuzhiyun int max_pds; 109*4882a593Smuzhiyun int reserved_xrcds; 110*4882a593Smuzhiyun int max_xrcds; 111*4882a593Smuzhiyun int qpc_entry_sz; 112*4882a593Smuzhiyun int rdmarc_entry_sz; 113*4882a593Smuzhiyun int altc_entry_sz; 114*4882a593Smuzhiyun int aux_entry_sz; 115*4882a593Smuzhiyun int srq_entry_sz; 116*4882a593Smuzhiyun int cqc_entry_sz; 117*4882a593Smuzhiyun int eqc_entry_sz; 118*4882a593Smuzhiyun int dmpt_entry_sz; 119*4882a593Smuzhiyun int cmpt_entry_sz; 120*4882a593Smuzhiyun int mtt_entry_sz; 121*4882a593Smuzhiyun int resize_srq; 122*4882a593Smuzhiyun u32 bmme_flags; 123*4882a593Smuzhiyun u32 reserved_lkey; 124*4882a593Smuzhiyun u64 max_icm_sz; 125*4882a593Smuzhiyun int max_gso_sz; 126*4882a593Smuzhiyun int max_rss_tbl_sz; 127*4882a593Smuzhiyun u32 max_counters; 128*4882a593Smuzhiyun u32 dmfs_high_rate_qpn_base; 129*4882a593Smuzhiyun u32 dmfs_high_rate_qpn_range; 130*4882a593Smuzhiyun struct mlx4_rate_limit_caps rl_caps; 131*4882a593Smuzhiyun u32 health_buffer_addrs; 132*4882a593Smuzhiyun struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1]; 133*4882a593Smuzhiyun bool wol_port[MLX4_MAX_PORTS + 1]; 134*4882a593Smuzhiyun bool map_clock_to_user; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun struct mlx4_func_cap { 138*4882a593Smuzhiyun u8 num_ports; 139*4882a593Smuzhiyun u8 flags; 140*4882a593Smuzhiyun u32 pf_context_behaviour; 141*4882a593Smuzhiyun int qp_quota; 142*4882a593Smuzhiyun int cq_quota; 143*4882a593Smuzhiyun int srq_quota; 144*4882a593Smuzhiyun int mpt_quota; 145*4882a593Smuzhiyun int mtt_quota; 146*4882a593Smuzhiyun int max_eq; 147*4882a593Smuzhiyun int reserved_eq; 148*4882a593Smuzhiyun int mcg_quota; 149*4882a593Smuzhiyun struct mlx4_spec_qps spec_qps; 150*4882a593Smuzhiyun u32 reserved_lkey; 151*4882a593Smuzhiyun u8 physical_port; 152*4882a593Smuzhiyun u8 flags0; 153*4882a593Smuzhiyun u8 flags1; 154*4882a593Smuzhiyun u64 phys_port_id; 155*4882a593Smuzhiyun u32 extra_flags; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun struct mlx4_func { 159*4882a593Smuzhiyun int bus; 160*4882a593Smuzhiyun int device; 161*4882a593Smuzhiyun int function; 162*4882a593Smuzhiyun int physical_function; 163*4882a593Smuzhiyun int rsvd_eqs; 164*4882a593Smuzhiyun int max_eq; 165*4882a593Smuzhiyun int rsvd_uars; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun struct mlx4_adapter { 169*4882a593Smuzhiyun char board_id[MLX4_BOARD_ID_LEN]; 170*4882a593Smuzhiyun u8 inta_pin; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun struct mlx4_init_hca_param { 174*4882a593Smuzhiyun u64 qpc_base; 175*4882a593Smuzhiyun u64 rdmarc_base; 176*4882a593Smuzhiyun u64 auxc_base; 177*4882a593Smuzhiyun u64 altc_base; 178*4882a593Smuzhiyun u64 srqc_base; 179*4882a593Smuzhiyun u64 cqc_base; 180*4882a593Smuzhiyun u64 eqc_base; 181*4882a593Smuzhiyun u64 mc_base; 182*4882a593Smuzhiyun u64 dmpt_base; 183*4882a593Smuzhiyun u64 cmpt_base; 184*4882a593Smuzhiyun u64 mtt_base; 185*4882a593Smuzhiyun u64 global_caps; 186*4882a593Smuzhiyun u8 log_mc_entry_sz; 187*4882a593Smuzhiyun u8 log_mc_hash_sz; 188*4882a593Smuzhiyun u16 hca_core_clock; /* Internal Clock Frequency (in MHz) */ 189*4882a593Smuzhiyun u8 log_num_qps; 190*4882a593Smuzhiyun u8 log_num_srqs; 191*4882a593Smuzhiyun u8 log_num_cqs; 192*4882a593Smuzhiyun u8 log_num_eqs; 193*4882a593Smuzhiyun u16 num_sys_eqs; 194*4882a593Smuzhiyun u8 log_rd_per_qp; 195*4882a593Smuzhiyun u8 log_mc_table_sz; 196*4882a593Smuzhiyun u8 log_mpt_sz; 197*4882a593Smuzhiyun u8 log_uar_sz; 198*4882a593Smuzhiyun u8 mw_enabled; /* Enable memory windows */ 199*4882a593Smuzhiyun u8 uar_page_sz; /* log pg sz in 4k chunks */ 200*4882a593Smuzhiyun u8 steering_mode; /* for QUERY_HCA */ 201*4882a593Smuzhiyun u8 dmfs_high_steer_mode; /* for QUERY_HCA */ 202*4882a593Smuzhiyun u64 dev_cap_enabled; 203*4882a593Smuzhiyun u16 cqe_size; /* For use only when CQE stride feature enabled */ 204*4882a593Smuzhiyun u16 eqe_size; /* For use only when EQE stride feature enabled */ 205*4882a593Smuzhiyun u8 rss_ip_frags; 206*4882a593Smuzhiyun u8 phv_check_en; /* for QUERY_HCA */ 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun struct mlx4_init_ib_param { 210*4882a593Smuzhiyun int port_width; 211*4882a593Smuzhiyun int vl_cap; 212*4882a593Smuzhiyun int mtu_cap; 213*4882a593Smuzhiyun u16 gid_cap; 214*4882a593Smuzhiyun u16 pkey_cap; 215*4882a593Smuzhiyun int set_guid0; 216*4882a593Smuzhiyun u64 guid0; 217*4882a593Smuzhiyun int set_node_guid; 218*4882a593Smuzhiyun u64 node_guid; 219*4882a593Smuzhiyun int set_si_guid; 220*4882a593Smuzhiyun u64 si_guid; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun struct mlx4_set_ib_param { 224*4882a593Smuzhiyun int set_si_guid; 225*4882a593Smuzhiyun int reset_qkey_viol; 226*4882a593Smuzhiyun u64 si_guid; 227*4882a593Smuzhiyun u32 cap_mask; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap); 231*4882a593Smuzhiyun int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap); 232*4882a593Smuzhiyun int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap); 233*4882a593Smuzhiyun int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 234*4882a593Smuzhiyun struct mlx4_func_cap *func_cap); 235*4882a593Smuzhiyun int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 236*4882a593Smuzhiyun struct mlx4_vhcr *vhcr, 237*4882a593Smuzhiyun struct mlx4_cmd_mailbox *inbox, 238*4882a593Smuzhiyun struct mlx4_cmd_mailbox *outbox, 239*4882a593Smuzhiyun struct mlx4_cmd_info *cmd); 240*4882a593Smuzhiyun int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave); 241*4882a593Smuzhiyun int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm); 242*4882a593Smuzhiyun int mlx4_UNMAP_FA(struct mlx4_dev *dev); 243*4882a593Smuzhiyun int mlx4_RUN_FW(struct mlx4_dev *dev); 244*4882a593Smuzhiyun int mlx4_QUERY_FW(struct mlx4_dev *dev); 245*4882a593Smuzhiyun int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter); 246*4882a593Smuzhiyun int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); 247*4882a593Smuzhiyun int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); 248*4882a593Smuzhiyun int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic); 249*4882a593Smuzhiyun int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt); 250*4882a593Smuzhiyun int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages); 251*4882a593Smuzhiyun int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm); 252*4882a593Smuzhiyun int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev); 253*4882a593Smuzhiyun int mlx4_NOP(struct mlx4_dev *dev); 254*4882a593Smuzhiyun int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg); 255*4882a593Smuzhiyun void mlx4_opreq_action(struct work_struct *work); 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun #endif /* MLX4_FW_H */ 258