1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <linux/slab.h>
35*4882a593Smuzhiyun #include <linux/vmalloc.h>
36*4882a593Smuzhiyun #include <linux/mlx4/qp.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include "mlx4_en.h"
39*4882a593Smuzhiyun
mlx4_en_fill_qp_context(struct mlx4_en_priv * priv,int size,int stride,int is_tx,int rss,int qpn,int cqn,int user_prio,struct mlx4_qp_context * context)40*4882a593Smuzhiyun void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
41*4882a593Smuzhiyun int is_tx, int rss, int qpn, int cqn,
42*4882a593Smuzhiyun int user_prio, struct mlx4_qp_context *context)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
45*4882a593Smuzhiyun struct net_device *dev = priv->dev;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun memset(context, 0, sizeof(*context));
48*4882a593Smuzhiyun context->flags = cpu_to_be32(7 << 16 | rss << MLX4_RSS_QPC_FLAG_OFFSET);
49*4882a593Smuzhiyun context->pd = cpu_to_be32(mdev->priv_pdn);
50*4882a593Smuzhiyun context->mtu_msgmax = 0xff;
51*4882a593Smuzhiyun if (!is_tx && !rss)
52*4882a593Smuzhiyun context->rq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4);
53*4882a593Smuzhiyun if (is_tx) {
54*4882a593Smuzhiyun context->sq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4);
55*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)
56*4882a593Smuzhiyun context->params2 |= cpu_to_be32(MLX4_QP_BIT_FPP);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun } else {
59*4882a593Smuzhiyun context->sq_size_stride = ilog2(TXBB_SIZE) - 4;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun context->usr_page = cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev,
62*4882a593Smuzhiyun mdev->priv_uar.index));
63*4882a593Smuzhiyun context->local_qpn = cpu_to_be32(qpn);
64*4882a593Smuzhiyun context->pri_path.ackto = 1 & 0x07;
65*4882a593Smuzhiyun context->pri_path.sched_queue = 0x83 | (priv->port - 1) << 6;
66*4882a593Smuzhiyun /* force user priority per tx ring */
67*4882a593Smuzhiyun if (user_prio >= 0 && priv->prof->num_up == MLX4_EN_NUM_UP_HIGH) {
68*4882a593Smuzhiyun context->pri_path.sched_queue |= user_prio << 3;
69*4882a593Smuzhiyun context->pri_path.feup = MLX4_FEUP_FORCE_ETH_UP;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun context->pri_path.counter_index = priv->counter_index;
72*4882a593Smuzhiyun context->cqn_send = cpu_to_be32(cqn);
73*4882a593Smuzhiyun context->cqn_recv = cpu_to_be32(cqn);
74*4882a593Smuzhiyun if (!rss &&
75*4882a593Smuzhiyun (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK) &&
76*4882a593Smuzhiyun context->pri_path.counter_index !=
77*4882a593Smuzhiyun MLX4_SINK_COUNTER_INDEX(mdev->dev)) {
78*4882a593Smuzhiyun /* disable multicast loopback to qp with same counter */
79*4882a593Smuzhiyun if (!(dev->features & NETIF_F_LOOPBACK))
80*4882a593Smuzhiyun context->pri_path.fl |= MLX4_FL_ETH_SRC_CHECK_MC_LB;
81*4882a593Smuzhiyun context->pri_path.control |= MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun context->db_rec_addr = cpu_to_be64(priv->res.db.dma << 2);
84*4882a593Smuzhiyun if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX))
85*4882a593Smuzhiyun context->param3 |= cpu_to_be32(1 << 30);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (!is_tx && !rss &&
88*4882a593Smuzhiyun (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)) {
89*4882a593Smuzhiyun en_dbg(HW, priv, "Setting RX qp %x tunnel mode to RX tunneled & non-tunneled\n", qpn);
90*4882a593Smuzhiyun context->srqn = cpu_to_be32(7 << 28); /* this fills bits 30:28 */
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
mlx4_en_change_mcast_lb(struct mlx4_en_priv * priv,struct mlx4_qp * qp,int loopback)94*4882a593Smuzhiyun int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
95*4882a593Smuzhiyun int loopback)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun int ret;
98*4882a593Smuzhiyun struct mlx4_update_qp_params qp_params;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun memset(&qp_params, 0, sizeof(qp_params));
101*4882a593Smuzhiyun if (!loopback)
102*4882a593Smuzhiyun qp_params.flags = MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun ret = mlx4_update_qp(priv->mdev->dev, qp->qpn,
105*4882a593Smuzhiyun MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB,
106*4882a593Smuzhiyun &qp_params);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return ret;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
mlx4_en_sqp_event(struct mlx4_qp * qp,enum mlx4_event event)111*4882a593Smuzhiyun void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun return;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116