1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <linux/bpf.h>
35*4882a593Smuzhiyun #include <linux/etherdevice.h>
36*4882a593Smuzhiyun #include <linux/tcp.h>
37*4882a593Smuzhiyun #include <linux/if_vlan.h>
38*4882a593Smuzhiyun #include <linux/delay.h>
39*4882a593Smuzhiyun #include <linux/slab.h>
40*4882a593Smuzhiyun #include <linux/hash.h>
41*4882a593Smuzhiyun #include <net/ip.h>
42*4882a593Smuzhiyun #include <net/vxlan.h>
43*4882a593Smuzhiyun #include <net/devlink.h>
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #include <linux/mlx4/driver.h>
46*4882a593Smuzhiyun #include <linux/mlx4/device.h>
47*4882a593Smuzhiyun #include <linux/mlx4/cmd.h>
48*4882a593Smuzhiyun #include <linux/mlx4/cq.h>
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #include "mlx4_en.h"
51*4882a593Smuzhiyun #include "en_port.h"
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define MLX4_EN_MAX_XDP_MTU ((int)(PAGE_SIZE - ETH_HLEN - (2 * VLAN_HLEN) - \
54*4882a593Smuzhiyun XDP_PACKET_HEADROOM - \
55*4882a593Smuzhiyun SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
56*4882a593Smuzhiyun
mlx4_en_setup_tc(struct net_device * dev,u8 up)57*4882a593Smuzhiyun int mlx4_en_setup_tc(struct net_device *dev, u8 up)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
60*4882a593Smuzhiyun int i;
61*4882a593Smuzhiyun unsigned int offset = 0;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (up && up != MLX4_EN_NUM_UP_HIGH)
64*4882a593Smuzhiyun return -EINVAL;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun netdev_set_num_tc(dev, up);
67*4882a593Smuzhiyun netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
68*4882a593Smuzhiyun /* Partition Tx queues evenly amongst UP's */
69*4882a593Smuzhiyun for (i = 0; i < up; i++) {
70*4882a593Smuzhiyun netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
71*4882a593Smuzhiyun offset += priv->num_tx_rings_p_up;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #ifdef CONFIG_MLX4_EN_DCB
75*4882a593Smuzhiyun if (!mlx4_is_slave(priv->mdev->dev)) {
76*4882a593Smuzhiyun if (up) {
77*4882a593Smuzhiyun if (priv->dcbx_cap)
78*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_DCB_ENABLED;
79*4882a593Smuzhiyun } else {
80*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_DCB_ENABLED;
81*4882a593Smuzhiyun priv->cee_config.pfc_state = false;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun #endif /* CONFIG_MLX4_EN_DCB */
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
mlx4_en_alloc_tx_queue_per_tc(struct net_device * dev,u8 tc)89*4882a593Smuzhiyun int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
92*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
93*4882a593Smuzhiyun struct mlx4_en_port_profile new_prof;
94*4882a593Smuzhiyun struct mlx4_en_priv *tmp;
95*4882a593Smuzhiyun int total_count;
96*4882a593Smuzhiyun int port_up = 0;
97*4882a593Smuzhiyun int err = 0;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
100*4882a593Smuzhiyun if (!tmp)
101*4882a593Smuzhiyun return -ENOMEM;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
104*4882a593Smuzhiyun memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
105*4882a593Smuzhiyun new_prof.num_up = (tc == 0) ? MLX4_EN_NUM_UP_LOW :
106*4882a593Smuzhiyun MLX4_EN_NUM_UP_HIGH;
107*4882a593Smuzhiyun new_prof.tx_ring_num[TX] = new_prof.num_tx_rings_p_up *
108*4882a593Smuzhiyun new_prof.num_up;
109*4882a593Smuzhiyun total_count = new_prof.tx_ring_num[TX] + new_prof.tx_ring_num[TX_XDP];
110*4882a593Smuzhiyun if (total_count > MAX_TX_RINGS) {
111*4882a593Smuzhiyun err = -EINVAL;
112*4882a593Smuzhiyun en_err(priv,
113*4882a593Smuzhiyun "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n",
114*4882a593Smuzhiyun total_count, MAX_TX_RINGS);
115*4882a593Smuzhiyun goto out;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
118*4882a593Smuzhiyun if (err)
119*4882a593Smuzhiyun goto out;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun if (priv->port_up) {
122*4882a593Smuzhiyun port_up = 1;
123*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun mlx4_en_safe_replace_resources(priv, tmp);
127*4882a593Smuzhiyun if (port_up) {
128*4882a593Smuzhiyun err = mlx4_en_start_port(dev);
129*4882a593Smuzhiyun if (err) {
130*4882a593Smuzhiyun en_err(priv, "Failed starting port for setup TC\n");
131*4882a593Smuzhiyun goto out;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun err = mlx4_en_setup_tc(dev, tc);
136*4882a593Smuzhiyun out:
137*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
138*4882a593Smuzhiyun kfree(tmp);
139*4882a593Smuzhiyun return err;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
__mlx4_en_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)142*4882a593Smuzhiyun static int __mlx4_en_setup_tc(struct net_device *dev, enum tc_setup_type type,
143*4882a593Smuzhiyun void *type_data)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun struct tc_mqprio_qopt *mqprio = type_data;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun if (type != TC_SETUP_QDISC_MQPRIO)
148*4882a593Smuzhiyun return -EOPNOTSUPP;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun if (mqprio->num_tc && mqprio->num_tc != MLX4_EN_NUM_UP_HIGH)
151*4882a593Smuzhiyun return -EINVAL;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun return mlx4_en_alloc_tx_queue_per_tc(dev, mqprio->num_tc);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun struct mlx4_en_filter {
161*4882a593Smuzhiyun struct list_head next;
162*4882a593Smuzhiyun struct work_struct work;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun u8 ip_proto;
165*4882a593Smuzhiyun __be32 src_ip;
166*4882a593Smuzhiyun __be32 dst_ip;
167*4882a593Smuzhiyun __be16 src_port;
168*4882a593Smuzhiyun __be16 dst_port;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun int rxq_index;
171*4882a593Smuzhiyun struct mlx4_en_priv *priv;
172*4882a593Smuzhiyun u32 flow_id; /* RFS infrastructure id */
173*4882a593Smuzhiyun int id; /* mlx4_en driver id */
174*4882a593Smuzhiyun u64 reg_id; /* Flow steering API id */
175*4882a593Smuzhiyun u8 activated; /* Used to prevent expiry before filter
176*4882a593Smuzhiyun * is attached
177*4882a593Smuzhiyun */
178*4882a593Smuzhiyun struct hlist_node filter_chain;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
182*4882a593Smuzhiyun
mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)183*4882a593Smuzhiyun static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun switch (ip_proto) {
186*4882a593Smuzhiyun case IPPROTO_UDP:
187*4882a593Smuzhiyun return MLX4_NET_TRANS_RULE_ID_UDP;
188*4882a593Smuzhiyun case IPPROTO_TCP:
189*4882a593Smuzhiyun return MLX4_NET_TRANS_RULE_ID_TCP;
190*4882a593Smuzhiyun default:
191*4882a593Smuzhiyun return MLX4_NET_TRANS_RULE_NUM;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* Must not acquire state_lock, as its corresponding work_sync
196*4882a593Smuzhiyun * is done under it.
197*4882a593Smuzhiyun */
mlx4_en_filter_work(struct work_struct * work)198*4882a593Smuzhiyun static void mlx4_en_filter_work(struct work_struct *work)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun struct mlx4_en_filter *filter = container_of(work,
201*4882a593Smuzhiyun struct mlx4_en_filter,
202*4882a593Smuzhiyun work);
203*4882a593Smuzhiyun struct mlx4_en_priv *priv = filter->priv;
204*4882a593Smuzhiyun struct mlx4_spec_list spec_tcp_udp = {
205*4882a593Smuzhiyun .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun .tcp_udp = {
208*4882a593Smuzhiyun .dst_port = filter->dst_port,
209*4882a593Smuzhiyun .dst_port_msk = (__force __be16)-1,
210*4882a593Smuzhiyun .src_port = filter->src_port,
211*4882a593Smuzhiyun .src_port_msk = (__force __be16)-1,
212*4882a593Smuzhiyun },
213*4882a593Smuzhiyun },
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun struct mlx4_spec_list spec_ip = {
216*4882a593Smuzhiyun .id = MLX4_NET_TRANS_RULE_ID_IPV4,
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun .ipv4 = {
219*4882a593Smuzhiyun .dst_ip = filter->dst_ip,
220*4882a593Smuzhiyun .dst_ip_msk = (__force __be32)-1,
221*4882a593Smuzhiyun .src_ip = filter->src_ip,
222*4882a593Smuzhiyun .src_ip_msk = (__force __be32)-1,
223*4882a593Smuzhiyun },
224*4882a593Smuzhiyun },
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun struct mlx4_spec_list spec_eth = {
227*4882a593Smuzhiyun .id = MLX4_NET_TRANS_RULE_ID_ETH,
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun struct mlx4_net_trans_rule rule = {
230*4882a593Smuzhiyun .list = LIST_HEAD_INIT(rule.list),
231*4882a593Smuzhiyun .queue_mode = MLX4_NET_TRANS_Q_LIFO,
232*4882a593Smuzhiyun .exclusive = 1,
233*4882a593Smuzhiyun .allow_loopback = 1,
234*4882a593Smuzhiyun .promisc_mode = MLX4_FS_REGULAR,
235*4882a593Smuzhiyun .port = priv->port,
236*4882a593Smuzhiyun .priority = MLX4_DOMAIN_RFS,
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun int rc;
239*4882a593Smuzhiyun __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
242*4882a593Smuzhiyun en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
243*4882a593Smuzhiyun filter->ip_proto);
244*4882a593Smuzhiyun goto ignore;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun list_add_tail(&spec_eth.list, &rule.list);
247*4882a593Smuzhiyun list_add_tail(&spec_ip.list, &rule.list);
248*4882a593Smuzhiyun list_add_tail(&spec_tcp_udp.list, &rule.list);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
251*4882a593Smuzhiyun memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
252*4882a593Smuzhiyun memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun filter->activated = 0;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun if (filter->reg_id) {
257*4882a593Smuzhiyun rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
258*4882a593Smuzhiyun if (rc && rc != -ENOENT)
259*4882a593Smuzhiyun en_err(priv, "Error detaching flow. rc = %d\n", rc);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
263*4882a593Smuzhiyun if (rc)
264*4882a593Smuzhiyun en_err(priv, "Error attaching flow. err = %d\n", rc);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun ignore:
267*4882a593Smuzhiyun mlx4_en_filter_rfs_expire(priv);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun filter->activated = 1;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun static inline struct hlist_head *
filter_hash_bucket(struct mlx4_en_priv * priv,__be32 src_ip,__be32 dst_ip,__be16 src_port,__be16 dst_port)273*4882a593Smuzhiyun filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
274*4882a593Smuzhiyun __be16 src_port, __be16 dst_port)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun unsigned long l;
277*4882a593Smuzhiyun int bucket_idx;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun l = (__force unsigned long)src_port |
280*4882a593Smuzhiyun ((__force unsigned long)dst_port << 2);
281*4882a593Smuzhiyun l ^= (__force unsigned long)(src_ip ^ dst_ip);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun return &priv->filter_hash[bucket_idx];
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun static struct mlx4_en_filter *
mlx4_en_filter_alloc(struct mlx4_en_priv * priv,int rxq_index,__be32 src_ip,__be32 dst_ip,u8 ip_proto,__be16 src_port,__be16 dst_port,u32 flow_id)289*4882a593Smuzhiyun mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
290*4882a593Smuzhiyun __be32 dst_ip, u8 ip_proto, __be16 src_port,
291*4882a593Smuzhiyun __be16 dst_port, u32 flow_id)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun struct mlx4_en_filter *filter = NULL;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
296*4882a593Smuzhiyun if (!filter)
297*4882a593Smuzhiyun return NULL;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun filter->priv = priv;
300*4882a593Smuzhiyun filter->rxq_index = rxq_index;
301*4882a593Smuzhiyun INIT_WORK(&filter->work, mlx4_en_filter_work);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun filter->src_ip = src_ip;
304*4882a593Smuzhiyun filter->dst_ip = dst_ip;
305*4882a593Smuzhiyun filter->ip_proto = ip_proto;
306*4882a593Smuzhiyun filter->src_port = src_port;
307*4882a593Smuzhiyun filter->dst_port = dst_port;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun filter->flow_id = flow_id;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun list_add_tail(&filter->next, &priv->filters);
314*4882a593Smuzhiyun hlist_add_head(&filter->filter_chain,
315*4882a593Smuzhiyun filter_hash_bucket(priv, src_ip, dst_ip, src_port,
316*4882a593Smuzhiyun dst_port));
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun return filter;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
mlx4_en_filter_free(struct mlx4_en_filter * filter)321*4882a593Smuzhiyun static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun struct mlx4_en_priv *priv = filter->priv;
324*4882a593Smuzhiyun int rc;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun list_del(&filter->next);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
329*4882a593Smuzhiyun if (rc && rc != -ENOENT)
330*4882a593Smuzhiyun en_err(priv, "Error detaching flow. rc = %d\n", rc);
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun kfree(filter);
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun static inline struct mlx4_en_filter *
mlx4_en_filter_find(struct mlx4_en_priv * priv,__be32 src_ip,__be32 dst_ip,u8 ip_proto,__be16 src_port,__be16 dst_port)336*4882a593Smuzhiyun mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
337*4882a593Smuzhiyun u8 ip_proto, __be16 src_port, __be16 dst_port)
338*4882a593Smuzhiyun {
339*4882a593Smuzhiyun struct mlx4_en_filter *filter;
340*4882a593Smuzhiyun struct mlx4_en_filter *ret = NULL;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun hlist_for_each_entry(filter,
343*4882a593Smuzhiyun filter_hash_bucket(priv, src_ip, dst_ip,
344*4882a593Smuzhiyun src_port, dst_port),
345*4882a593Smuzhiyun filter_chain) {
346*4882a593Smuzhiyun if (filter->src_ip == src_ip &&
347*4882a593Smuzhiyun filter->dst_ip == dst_ip &&
348*4882a593Smuzhiyun filter->ip_proto == ip_proto &&
349*4882a593Smuzhiyun filter->src_port == src_port &&
350*4882a593Smuzhiyun filter->dst_port == dst_port) {
351*4882a593Smuzhiyun ret = filter;
352*4882a593Smuzhiyun break;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun return ret;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun static int
mlx4_en_filter_rfs(struct net_device * net_dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)360*4882a593Smuzhiyun mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
361*4882a593Smuzhiyun u16 rxq_index, u32 flow_id)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(net_dev);
364*4882a593Smuzhiyun struct mlx4_en_filter *filter;
365*4882a593Smuzhiyun const struct iphdr *ip;
366*4882a593Smuzhiyun const __be16 *ports;
367*4882a593Smuzhiyun u8 ip_proto;
368*4882a593Smuzhiyun __be32 src_ip;
369*4882a593Smuzhiyun __be32 dst_ip;
370*4882a593Smuzhiyun __be16 src_port;
371*4882a593Smuzhiyun __be16 dst_port;
372*4882a593Smuzhiyun int nhoff = skb_network_offset(skb);
373*4882a593Smuzhiyun int ret = 0;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun if (skb->encapsulation)
376*4882a593Smuzhiyun return -EPROTONOSUPPORT;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun if (skb->protocol != htons(ETH_P_IP))
379*4882a593Smuzhiyun return -EPROTONOSUPPORT;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun ip = (const struct iphdr *)(skb->data + nhoff);
382*4882a593Smuzhiyun if (ip_is_fragment(ip))
383*4882a593Smuzhiyun return -EPROTONOSUPPORT;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
386*4882a593Smuzhiyun return -EPROTONOSUPPORT;
387*4882a593Smuzhiyun ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun ip_proto = ip->protocol;
390*4882a593Smuzhiyun src_ip = ip->saddr;
391*4882a593Smuzhiyun dst_ip = ip->daddr;
392*4882a593Smuzhiyun src_port = ports[0];
393*4882a593Smuzhiyun dst_port = ports[1];
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun spin_lock_bh(&priv->filters_lock);
396*4882a593Smuzhiyun filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
397*4882a593Smuzhiyun src_port, dst_port);
398*4882a593Smuzhiyun if (filter) {
399*4882a593Smuzhiyun if (filter->rxq_index == rxq_index)
400*4882a593Smuzhiyun goto out;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun filter->rxq_index = rxq_index;
403*4882a593Smuzhiyun } else {
404*4882a593Smuzhiyun filter = mlx4_en_filter_alloc(priv, rxq_index,
405*4882a593Smuzhiyun src_ip, dst_ip, ip_proto,
406*4882a593Smuzhiyun src_port, dst_port, flow_id);
407*4882a593Smuzhiyun if (!filter) {
408*4882a593Smuzhiyun ret = -ENOMEM;
409*4882a593Smuzhiyun goto err;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun queue_work(priv->mdev->workqueue, &filter->work);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun out:
416*4882a593Smuzhiyun ret = filter->id;
417*4882a593Smuzhiyun err:
418*4882a593Smuzhiyun spin_unlock_bh(&priv->filters_lock);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun return ret;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
mlx4_en_cleanup_filters(struct mlx4_en_priv * priv)423*4882a593Smuzhiyun void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun struct mlx4_en_filter *filter, *tmp;
426*4882a593Smuzhiyun LIST_HEAD(del_list);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun spin_lock_bh(&priv->filters_lock);
429*4882a593Smuzhiyun list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
430*4882a593Smuzhiyun list_move(&filter->next, &del_list);
431*4882a593Smuzhiyun hlist_del(&filter->filter_chain);
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun spin_unlock_bh(&priv->filters_lock);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun list_for_each_entry_safe(filter, tmp, &del_list, next) {
436*4882a593Smuzhiyun cancel_work_sync(&filter->work);
437*4882a593Smuzhiyun mlx4_en_filter_free(filter);
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
mlx4_en_filter_rfs_expire(struct mlx4_en_priv * priv)441*4882a593Smuzhiyun static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
444*4882a593Smuzhiyun LIST_HEAD(del_list);
445*4882a593Smuzhiyun int i = 0;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun spin_lock_bh(&priv->filters_lock);
448*4882a593Smuzhiyun list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
449*4882a593Smuzhiyun if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
450*4882a593Smuzhiyun break;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun if (filter->activated &&
453*4882a593Smuzhiyun !work_pending(&filter->work) &&
454*4882a593Smuzhiyun rps_may_expire_flow(priv->dev,
455*4882a593Smuzhiyun filter->rxq_index, filter->flow_id,
456*4882a593Smuzhiyun filter->id)) {
457*4882a593Smuzhiyun list_move(&filter->next, &del_list);
458*4882a593Smuzhiyun hlist_del(&filter->filter_chain);
459*4882a593Smuzhiyun } else
460*4882a593Smuzhiyun last_filter = filter;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun i++;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun if (last_filter && (&last_filter->next != priv->filters.next))
466*4882a593Smuzhiyun list_move(&priv->filters, &last_filter->next);
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun spin_unlock_bh(&priv->filters_lock);
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun list_for_each_entry_safe(filter, tmp, &del_list, next)
471*4882a593Smuzhiyun mlx4_en_filter_free(filter);
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun #endif
474*4882a593Smuzhiyun
mlx4_en_vlan_rx_add_vid(struct net_device * dev,__be16 proto,u16 vid)475*4882a593Smuzhiyun static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
476*4882a593Smuzhiyun __be16 proto, u16 vid)
477*4882a593Smuzhiyun {
478*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
479*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
480*4882a593Smuzhiyun int err;
481*4882a593Smuzhiyun int idx;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun en_dbg(HW, priv, "adding VLAN:%d\n", vid);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun set_bit(vid, priv->active_vlans);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun /* Add VID to port VLAN filter */
488*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
489*4882a593Smuzhiyun if (mdev->device_up && priv->port_up) {
490*4882a593Smuzhiyun err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
491*4882a593Smuzhiyun if (err) {
492*4882a593Smuzhiyun en_err(priv, "Failed configuring VLAN filter\n");
493*4882a593Smuzhiyun goto out;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun err = mlx4_register_vlan(mdev->dev, priv->port, vid, &idx);
497*4882a593Smuzhiyun if (err)
498*4882a593Smuzhiyun en_dbg(HW, priv, "Failed adding vlan %d\n", vid);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun out:
501*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
502*4882a593Smuzhiyun return err;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
mlx4_en_vlan_rx_kill_vid(struct net_device * dev,__be16 proto,u16 vid)505*4882a593Smuzhiyun static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
506*4882a593Smuzhiyun __be16 proto, u16 vid)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
509*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
510*4882a593Smuzhiyun int err = 0;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun en_dbg(HW, priv, "Killing VID:%d\n", vid);
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun clear_bit(vid, priv->active_vlans);
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun /* Remove VID from port VLAN filter */
517*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
518*4882a593Smuzhiyun mlx4_unregister_vlan(mdev->dev, priv->port, vid);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun if (mdev->device_up && priv->port_up) {
521*4882a593Smuzhiyun err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
522*4882a593Smuzhiyun if (err)
523*4882a593Smuzhiyun en_err(priv, "Failed configuring VLAN filter\n");
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun return err;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun
mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN+2],u64 src_mac)530*4882a593Smuzhiyun static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun int i;
533*4882a593Smuzhiyun for (i = ETH_ALEN - 1; i >= 0; --i) {
534*4882a593Smuzhiyun dst_mac[i] = src_mac & 0xff;
535*4882a593Smuzhiyun src_mac >>= 8;
536*4882a593Smuzhiyun }
537*4882a593Smuzhiyun memset(&dst_mac[ETH_ALEN], 0, 2);
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun
mlx4_en_tunnel_steer_add(struct mlx4_en_priv * priv,unsigned char * addr,int qpn,u64 * reg_id)541*4882a593Smuzhiyun static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
542*4882a593Smuzhiyun int qpn, u64 *reg_id)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun int err;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
547*4882a593Smuzhiyun priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
548*4882a593Smuzhiyun return 0; /* do nothing */
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
551*4882a593Smuzhiyun MLX4_DOMAIN_NIC, reg_id);
552*4882a593Smuzhiyun if (err) {
553*4882a593Smuzhiyun en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
554*4882a593Smuzhiyun return err;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
557*4882a593Smuzhiyun return 0;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun
mlx4_en_uc_steer_add(struct mlx4_en_priv * priv,unsigned char * mac,int * qpn,u64 * reg_id)561*4882a593Smuzhiyun static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
562*4882a593Smuzhiyun unsigned char *mac, int *qpn, u64 *reg_id)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
565*4882a593Smuzhiyun struct mlx4_dev *dev = mdev->dev;
566*4882a593Smuzhiyun int err;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun switch (dev->caps.steering_mode) {
569*4882a593Smuzhiyun case MLX4_STEERING_MODE_B0: {
570*4882a593Smuzhiyun struct mlx4_qp qp;
571*4882a593Smuzhiyun u8 gid[16] = {0};
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun qp.qpn = *qpn;
574*4882a593Smuzhiyun memcpy(&gid[10], mac, ETH_ALEN);
575*4882a593Smuzhiyun gid[5] = priv->port;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
578*4882a593Smuzhiyun break;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun case MLX4_STEERING_MODE_DEVICE_MANAGED: {
581*4882a593Smuzhiyun struct mlx4_spec_list spec_eth = { {NULL} };
582*4882a593Smuzhiyun __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun struct mlx4_net_trans_rule rule = {
585*4882a593Smuzhiyun .queue_mode = MLX4_NET_TRANS_Q_FIFO,
586*4882a593Smuzhiyun .exclusive = 0,
587*4882a593Smuzhiyun .allow_loopback = 1,
588*4882a593Smuzhiyun .promisc_mode = MLX4_FS_REGULAR,
589*4882a593Smuzhiyun .priority = MLX4_DOMAIN_NIC,
590*4882a593Smuzhiyun };
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun rule.port = priv->port;
593*4882a593Smuzhiyun rule.qpn = *qpn;
594*4882a593Smuzhiyun INIT_LIST_HEAD(&rule.list);
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
597*4882a593Smuzhiyun memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
598*4882a593Smuzhiyun memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
599*4882a593Smuzhiyun list_add_tail(&spec_eth.list, &rule.list);
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun err = mlx4_flow_attach(dev, &rule, reg_id);
602*4882a593Smuzhiyun break;
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun default:
605*4882a593Smuzhiyun return -EINVAL;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun if (err)
608*4882a593Smuzhiyun en_warn(priv, "Failed Attaching Unicast\n");
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun return err;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
mlx4_en_uc_steer_release(struct mlx4_en_priv * priv,unsigned char * mac,int qpn,u64 reg_id)613*4882a593Smuzhiyun static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
614*4882a593Smuzhiyun unsigned char *mac, int qpn, u64 reg_id)
615*4882a593Smuzhiyun {
616*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
617*4882a593Smuzhiyun struct mlx4_dev *dev = mdev->dev;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun switch (dev->caps.steering_mode) {
620*4882a593Smuzhiyun case MLX4_STEERING_MODE_B0: {
621*4882a593Smuzhiyun struct mlx4_qp qp;
622*4882a593Smuzhiyun u8 gid[16] = {0};
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun qp.qpn = qpn;
625*4882a593Smuzhiyun memcpy(&gid[10], mac, ETH_ALEN);
626*4882a593Smuzhiyun gid[5] = priv->port;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
629*4882a593Smuzhiyun break;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun case MLX4_STEERING_MODE_DEVICE_MANAGED: {
632*4882a593Smuzhiyun mlx4_flow_detach(dev, reg_id);
633*4882a593Smuzhiyun break;
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun default:
636*4882a593Smuzhiyun en_err(priv, "Invalid steering mode.\n");
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
mlx4_en_get_qp(struct mlx4_en_priv * priv)640*4882a593Smuzhiyun static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
643*4882a593Smuzhiyun struct mlx4_dev *dev = mdev->dev;
644*4882a593Smuzhiyun int index = 0;
645*4882a593Smuzhiyun int err = 0;
646*4882a593Smuzhiyun int *qpn = &priv->base_qpn;
647*4882a593Smuzhiyun u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
650*4882a593Smuzhiyun priv->dev->dev_addr);
651*4882a593Smuzhiyun index = mlx4_register_mac(dev, priv->port, mac);
652*4882a593Smuzhiyun if (index < 0) {
653*4882a593Smuzhiyun err = index;
654*4882a593Smuzhiyun en_err(priv, "Failed adding MAC: %pM\n",
655*4882a593Smuzhiyun priv->dev->dev_addr);
656*4882a593Smuzhiyun return err;
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun en_info(priv, "Steering Mode %d\n", dev->caps.steering_mode);
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
662*4882a593Smuzhiyun int base_qpn = mlx4_get_base_qpn(dev, priv->port);
663*4882a593Smuzhiyun *qpn = base_qpn + index;
664*4882a593Smuzhiyun return 0;
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP,
668*4882a593Smuzhiyun MLX4_RES_USAGE_DRIVER);
669*4882a593Smuzhiyun en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
670*4882a593Smuzhiyun if (err) {
671*4882a593Smuzhiyun en_err(priv, "Failed to reserve qp for mac registration\n");
672*4882a593Smuzhiyun mlx4_unregister_mac(dev, priv->port, mac);
673*4882a593Smuzhiyun return err;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun return 0;
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
mlx4_en_put_qp(struct mlx4_en_priv * priv)679*4882a593Smuzhiyun static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
682*4882a593Smuzhiyun struct mlx4_dev *dev = mdev->dev;
683*4882a593Smuzhiyun int qpn = priv->base_qpn;
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
686*4882a593Smuzhiyun u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
687*4882a593Smuzhiyun en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
688*4882a593Smuzhiyun priv->dev->dev_addr);
689*4882a593Smuzhiyun mlx4_unregister_mac(dev, priv->port, mac);
690*4882a593Smuzhiyun } else {
691*4882a593Smuzhiyun en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
692*4882a593Smuzhiyun priv->port, qpn);
693*4882a593Smuzhiyun mlx4_qp_release_range(dev, qpn, 1);
694*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
mlx4_en_replace_mac(struct mlx4_en_priv * priv,int qpn,unsigned char * new_mac,unsigned char * prev_mac)698*4882a593Smuzhiyun static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
699*4882a593Smuzhiyun unsigned char *new_mac, unsigned char *prev_mac)
700*4882a593Smuzhiyun {
701*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
702*4882a593Smuzhiyun struct mlx4_dev *dev = mdev->dev;
703*4882a593Smuzhiyun int err = 0;
704*4882a593Smuzhiyun u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
707*4882a593Smuzhiyun struct hlist_head *bucket;
708*4882a593Smuzhiyun unsigned int mac_hash;
709*4882a593Smuzhiyun struct mlx4_mac_entry *entry;
710*4882a593Smuzhiyun struct hlist_node *tmp;
711*4882a593Smuzhiyun u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
714*4882a593Smuzhiyun hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
715*4882a593Smuzhiyun if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
716*4882a593Smuzhiyun mlx4_en_uc_steer_release(priv, entry->mac,
717*4882a593Smuzhiyun qpn, entry->reg_id);
718*4882a593Smuzhiyun mlx4_unregister_mac(dev, priv->port,
719*4882a593Smuzhiyun prev_mac_u64);
720*4882a593Smuzhiyun hlist_del_rcu(&entry->hlist);
721*4882a593Smuzhiyun synchronize_rcu();
722*4882a593Smuzhiyun memcpy(entry->mac, new_mac, ETH_ALEN);
723*4882a593Smuzhiyun entry->reg_id = 0;
724*4882a593Smuzhiyun mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
725*4882a593Smuzhiyun hlist_add_head_rcu(&entry->hlist,
726*4882a593Smuzhiyun &priv->mac_hash[mac_hash]);
727*4882a593Smuzhiyun mlx4_register_mac(dev, priv->port, new_mac_u64);
728*4882a593Smuzhiyun err = mlx4_en_uc_steer_add(priv, new_mac,
729*4882a593Smuzhiyun &qpn,
730*4882a593Smuzhiyun &entry->reg_id);
731*4882a593Smuzhiyun if (err)
732*4882a593Smuzhiyun return err;
733*4882a593Smuzhiyun if (priv->tunnel_reg_id) {
734*4882a593Smuzhiyun mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
735*4882a593Smuzhiyun priv->tunnel_reg_id = 0;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
738*4882a593Smuzhiyun &priv->tunnel_reg_id);
739*4882a593Smuzhiyun return err;
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun return -EINVAL;
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun
mlx4_en_update_user_mac(struct mlx4_en_priv * priv,unsigned char new_mac[ETH_ALEN+2])748*4882a593Smuzhiyun static void mlx4_en_update_user_mac(struct mlx4_en_priv *priv,
749*4882a593Smuzhiyun unsigned char new_mac[ETH_ALEN + 2])
750*4882a593Smuzhiyun {
751*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
752*4882a593Smuzhiyun int err;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_USER_MAC_EN))
755*4882a593Smuzhiyun return;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun err = mlx4_SET_PORT_user_mac(mdev->dev, priv->port, new_mac);
758*4882a593Smuzhiyun if (err)
759*4882a593Smuzhiyun en_err(priv, "Failed to pass user MAC(%pM) to Firmware for port %d, with error %d\n",
760*4882a593Smuzhiyun new_mac, priv->port, err);
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun
mlx4_en_do_set_mac(struct mlx4_en_priv * priv,unsigned char new_mac[ETH_ALEN+2])763*4882a593Smuzhiyun static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
764*4882a593Smuzhiyun unsigned char new_mac[ETH_ALEN + 2])
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun int err = 0;
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun if (priv->port_up) {
769*4882a593Smuzhiyun /* Remove old MAC and insert the new one */
770*4882a593Smuzhiyun err = mlx4_en_replace_mac(priv, priv->base_qpn,
771*4882a593Smuzhiyun new_mac, priv->current_mac);
772*4882a593Smuzhiyun if (err)
773*4882a593Smuzhiyun en_err(priv, "Failed changing HW MAC address\n");
774*4882a593Smuzhiyun } else
775*4882a593Smuzhiyun en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun if (!err)
778*4882a593Smuzhiyun memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun return err;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun
mlx4_en_set_mac(struct net_device * dev,void * addr)783*4882a593Smuzhiyun static int mlx4_en_set_mac(struct net_device *dev, void *addr)
784*4882a593Smuzhiyun {
785*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
786*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
787*4882a593Smuzhiyun struct sockaddr *saddr = addr;
788*4882a593Smuzhiyun unsigned char new_mac[ETH_ALEN + 2];
789*4882a593Smuzhiyun int err;
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun if (!is_valid_ether_addr(saddr->sa_data))
792*4882a593Smuzhiyun return -EADDRNOTAVAIL;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
795*4882a593Smuzhiyun memcpy(new_mac, saddr->sa_data, ETH_ALEN);
796*4882a593Smuzhiyun err = mlx4_en_do_set_mac(priv, new_mac);
797*4882a593Smuzhiyun if (err)
798*4882a593Smuzhiyun goto out;
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
801*4882a593Smuzhiyun mlx4_en_update_user_mac(priv, new_mac);
802*4882a593Smuzhiyun out:
803*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun return err;
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun
mlx4_en_clear_list(struct net_device * dev)808*4882a593Smuzhiyun static void mlx4_en_clear_list(struct net_device *dev)
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
811*4882a593Smuzhiyun struct mlx4_en_mc_list *tmp, *mc_to_del;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
814*4882a593Smuzhiyun list_del(&mc_to_del->list);
815*4882a593Smuzhiyun kfree(mc_to_del);
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun
mlx4_en_cache_mclist(struct net_device * dev)819*4882a593Smuzhiyun static void mlx4_en_cache_mclist(struct net_device *dev)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
822*4882a593Smuzhiyun struct netdev_hw_addr *ha;
823*4882a593Smuzhiyun struct mlx4_en_mc_list *tmp;
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun mlx4_en_clear_list(dev);
826*4882a593Smuzhiyun netdev_for_each_mc_addr(ha, dev) {
827*4882a593Smuzhiyun tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
828*4882a593Smuzhiyun if (!tmp) {
829*4882a593Smuzhiyun mlx4_en_clear_list(dev);
830*4882a593Smuzhiyun return;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun memcpy(tmp->addr, ha->addr, ETH_ALEN);
833*4882a593Smuzhiyun list_add_tail(&tmp->list, &priv->mc_list);
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun
update_mclist_flags(struct mlx4_en_priv * priv,struct list_head * dst,struct list_head * src)837*4882a593Smuzhiyun static void update_mclist_flags(struct mlx4_en_priv *priv,
838*4882a593Smuzhiyun struct list_head *dst,
839*4882a593Smuzhiyun struct list_head *src)
840*4882a593Smuzhiyun {
841*4882a593Smuzhiyun struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
842*4882a593Smuzhiyun bool found;
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun /* Find all the entries that should be removed from dst,
845*4882a593Smuzhiyun * These are the entries that are not found in src
846*4882a593Smuzhiyun */
847*4882a593Smuzhiyun list_for_each_entry(dst_tmp, dst, list) {
848*4882a593Smuzhiyun found = false;
849*4882a593Smuzhiyun list_for_each_entry(src_tmp, src, list) {
850*4882a593Smuzhiyun if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
851*4882a593Smuzhiyun found = true;
852*4882a593Smuzhiyun break;
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun if (!found)
856*4882a593Smuzhiyun dst_tmp->action = MCLIST_REM;
857*4882a593Smuzhiyun }
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun /* Add entries that exist in src but not in dst
860*4882a593Smuzhiyun * mark them as need to add
861*4882a593Smuzhiyun */
862*4882a593Smuzhiyun list_for_each_entry(src_tmp, src, list) {
863*4882a593Smuzhiyun found = false;
864*4882a593Smuzhiyun list_for_each_entry(dst_tmp, dst, list) {
865*4882a593Smuzhiyun if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
866*4882a593Smuzhiyun dst_tmp->action = MCLIST_NONE;
867*4882a593Smuzhiyun found = true;
868*4882a593Smuzhiyun break;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun if (!found) {
872*4882a593Smuzhiyun new_mc = kmemdup(src_tmp,
873*4882a593Smuzhiyun sizeof(struct mlx4_en_mc_list),
874*4882a593Smuzhiyun GFP_KERNEL);
875*4882a593Smuzhiyun if (!new_mc)
876*4882a593Smuzhiyun return;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun new_mc->action = MCLIST_ADD;
879*4882a593Smuzhiyun list_add_tail(&new_mc->list, dst);
880*4882a593Smuzhiyun }
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun
mlx4_en_set_rx_mode(struct net_device * dev)884*4882a593Smuzhiyun static void mlx4_en_set_rx_mode(struct net_device *dev)
885*4882a593Smuzhiyun {
886*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun if (!priv->port_up)
889*4882a593Smuzhiyun return;
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun
mlx4_en_set_promisc_mode(struct mlx4_en_priv * priv,struct mlx4_en_dev * mdev)894*4882a593Smuzhiyun static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
895*4882a593Smuzhiyun struct mlx4_en_dev *mdev)
896*4882a593Smuzhiyun {
897*4882a593Smuzhiyun int err = 0;
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
900*4882a593Smuzhiyun if (netif_msg_rx_status(priv))
901*4882a593Smuzhiyun en_warn(priv, "Entering promiscuous mode\n");
902*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_PROMISC;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun /* Enable promiscouos mode */
905*4882a593Smuzhiyun switch (mdev->dev->caps.steering_mode) {
906*4882a593Smuzhiyun case MLX4_STEERING_MODE_DEVICE_MANAGED:
907*4882a593Smuzhiyun err = mlx4_flow_steer_promisc_add(mdev->dev,
908*4882a593Smuzhiyun priv->port,
909*4882a593Smuzhiyun priv->base_qpn,
910*4882a593Smuzhiyun MLX4_FS_ALL_DEFAULT);
911*4882a593Smuzhiyun if (err)
912*4882a593Smuzhiyun en_err(priv, "Failed enabling promiscuous mode\n");
913*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
914*4882a593Smuzhiyun break;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun case MLX4_STEERING_MODE_B0:
917*4882a593Smuzhiyun err = mlx4_unicast_promisc_add(mdev->dev,
918*4882a593Smuzhiyun priv->base_qpn,
919*4882a593Smuzhiyun priv->port);
920*4882a593Smuzhiyun if (err)
921*4882a593Smuzhiyun en_err(priv, "Failed enabling unicast promiscuous mode\n");
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun /* Add the default qp number as multicast
924*4882a593Smuzhiyun * promisc
925*4882a593Smuzhiyun */
926*4882a593Smuzhiyun if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
927*4882a593Smuzhiyun err = mlx4_multicast_promisc_add(mdev->dev,
928*4882a593Smuzhiyun priv->base_qpn,
929*4882a593Smuzhiyun priv->port);
930*4882a593Smuzhiyun if (err)
931*4882a593Smuzhiyun en_err(priv, "Failed enabling multicast promiscuous mode\n");
932*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
933*4882a593Smuzhiyun }
934*4882a593Smuzhiyun break;
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun case MLX4_STEERING_MODE_A0:
937*4882a593Smuzhiyun err = mlx4_SET_PORT_qpn_calc(mdev->dev,
938*4882a593Smuzhiyun priv->port,
939*4882a593Smuzhiyun priv->base_qpn,
940*4882a593Smuzhiyun 1);
941*4882a593Smuzhiyun if (err)
942*4882a593Smuzhiyun en_err(priv, "Failed enabling promiscuous mode\n");
943*4882a593Smuzhiyun break;
944*4882a593Smuzhiyun }
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun /* Disable port multicast filter (unconditionally) */
947*4882a593Smuzhiyun err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
948*4882a593Smuzhiyun 0, MLX4_MCAST_DISABLE);
949*4882a593Smuzhiyun if (err)
950*4882a593Smuzhiyun en_err(priv, "Failed disabling multicast filter\n");
951*4882a593Smuzhiyun }
952*4882a593Smuzhiyun }
953*4882a593Smuzhiyun
mlx4_en_clear_promisc_mode(struct mlx4_en_priv * priv,struct mlx4_en_dev * mdev)954*4882a593Smuzhiyun static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
955*4882a593Smuzhiyun struct mlx4_en_dev *mdev)
956*4882a593Smuzhiyun {
957*4882a593Smuzhiyun int err = 0;
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun if (netif_msg_rx_status(priv))
960*4882a593Smuzhiyun en_warn(priv, "Leaving promiscuous mode\n");
961*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_PROMISC;
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun /* Disable promiscouos mode */
964*4882a593Smuzhiyun switch (mdev->dev->caps.steering_mode) {
965*4882a593Smuzhiyun case MLX4_STEERING_MODE_DEVICE_MANAGED:
966*4882a593Smuzhiyun err = mlx4_flow_steer_promisc_remove(mdev->dev,
967*4882a593Smuzhiyun priv->port,
968*4882a593Smuzhiyun MLX4_FS_ALL_DEFAULT);
969*4882a593Smuzhiyun if (err)
970*4882a593Smuzhiyun en_err(priv, "Failed disabling promiscuous mode\n");
971*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
972*4882a593Smuzhiyun break;
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun case MLX4_STEERING_MODE_B0:
975*4882a593Smuzhiyun err = mlx4_unicast_promisc_remove(mdev->dev,
976*4882a593Smuzhiyun priv->base_qpn,
977*4882a593Smuzhiyun priv->port);
978*4882a593Smuzhiyun if (err)
979*4882a593Smuzhiyun en_err(priv, "Failed disabling unicast promiscuous mode\n");
980*4882a593Smuzhiyun /* Disable Multicast promisc */
981*4882a593Smuzhiyun if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
982*4882a593Smuzhiyun err = mlx4_multicast_promisc_remove(mdev->dev,
983*4882a593Smuzhiyun priv->base_qpn,
984*4882a593Smuzhiyun priv->port);
985*4882a593Smuzhiyun if (err)
986*4882a593Smuzhiyun en_err(priv, "Failed disabling multicast promiscuous mode\n");
987*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun break;
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun case MLX4_STEERING_MODE_A0:
992*4882a593Smuzhiyun err = mlx4_SET_PORT_qpn_calc(mdev->dev,
993*4882a593Smuzhiyun priv->port,
994*4882a593Smuzhiyun priv->base_qpn, 0);
995*4882a593Smuzhiyun if (err)
996*4882a593Smuzhiyun en_err(priv, "Failed disabling promiscuous mode\n");
997*4882a593Smuzhiyun break;
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun
mlx4_en_do_multicast(struct mlx4_en_priv * priv,struct net_device * dev,struct mlx4_en_dev * mdev)1001*4882a593Smuzhiyun static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
1002*4882a593Smuzhiyun struct net_device *dev,
1003*4882a593Smuzhiyun struct mlx4_en_dev *mdev)
1004*4882a593Smuzhiyun {
1005*4882a593Smuzhiyun struct mlx4_en_mc_list *mclist, *tmp;
1006*4882a593Smuzhiyun u64 mcast_addr = 0;
1007*4882a593Smuzhiyun u8 mc_list[16] = {0};
1008*4882a593Smuzhiyun int err = 0;
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun /* Enable/disable the multicast filter according to IFF_ALLMULTI */
1011*4882a593Smuzhiyun if (dev->flags & IFF_ALLMULTI) {
1012*4882a593Smuzhiyun err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1013*4882a593Smuzhiyun 0, MLX4_MCAST_DISABLE);
1014*4882a593Smuzhiyun if (err)
1015*4882a593Smuzhiyun en_err(priv, "Failed disabling multicast filter\n");
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun /* Add the default qp number as multicast promisc */
1018*4882a593Smuzhiyun if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
1019*4882a593Smuzhiyun switch (mdev->dev->caps.steering_mode) {
1020*4882a593Smuzhiyun case MLX4_STEERING_MODE_DEVICE_MANAGED:
1021*4882a593Smuzhiyun err = mlx4_flow_steer_promisc_add(mdev->dev,
1022*4882a593Smuzhiyun priv->port,
1023*4882a593Smuzhiyun priv->base_qpn,
1024*4882a593Smuzhiyun MLX4_FS_MC_DEFAULT);
1025*4882a593Smuzhiyun break;
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun case MLX4_STEERING_MODE_B0:
1028*4882a593Smuzhiyun err = mlx4_multicast_promisc_add(mdev->dev,
1029*4882a593Smuzhiyun priv->base_qpn,
1030*4882a593Smuzhiyun priv->port);
1031*4882a593Smuzhiyun break;
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun case MLX4_STEERING_MODE_A0:
1034*4882a593Smuzhiyun break;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun if (err)
1037*4882a593Smuzhiyun en_err(priv, "Failed entering multicast promisc mode\n");
1038*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1039*4882a593Smuzhiyun }
1040*4882a593Smuzhiyun } else {
1041*4882a593Smuzhiyun /* Disable Multicast promisc */
1042*4882a593Smuzhiyun if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1043*4882a593Smuzhiyun switch (mdev->dev->caps.steering_mode) {
1044*4882a593Smuzhiyun case MLX4_STEERING_MODE_DEVICE_MANAGED:
1045*4882a593Smuzhiyun err = mlx4_flow_steer_promisc_remove(mdev->dev,
1046*4882a593Smuzhiyun priv->port,
1047*4882a593Smuzhiyun MLX4_FS_MC_DEFAULT);
1048*4882a593Smuzhiyun break;
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun case MLX4_STEERING_MODE_B0:
1051*4882a593Smuzhiyun err = mlx4_multicast_promisc_remove(mdev->dev,
1052*4882a593Smuzhiyun priv->base_qpn,
1053*4882a593Smuzhiyun priv->port);
1054*4882a593Smuzhiyun break;
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun case MLX4_STEERING_MODE_A0:
1057*4882a593Smuzhiyun break;
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun if (err)
1060*4882a593Smuzhiyun en_err(priv, "Failed disabling multicast promiscuous mode\n");
1061*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1062*4882a593Smuzhiyun }
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1065*4882a593Smuzhiyun 0, MLX4_MCAST_DISABLE);
1066*4882a593Smuzhiyun if (err)
1067*4882a593Smuzhiyun en_err(priv, "Failed disabling multicast filter\n");
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun /* Flush mcast filter and init it with broadcast address */
1070*4882a593Smuzhiyun mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1071*4882a593Smuzhiyun 1, MLX4_MCAST_CONFIG);
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun /* Update multicast list - we cache all addresses so they won't
1074*4882a593Smuzhiyun * change while HW is updated holding the command semaphor */
1075*4882a593Smuzhiyun netif_addr_lock_bh(dev);
1076*4882a593Smuzhiyun mlx4_en_cache_mclist(dev);
1077*4882a593Smuzhiyun netif_addr_unlock_bh(dev);
1078*4882a593Smuzhiyun list_for_each_entry(mclist, &priv->mc_list, list) {
1079*4882a593Smuzhiyun mcast_addr = mlx4_mac_to_u64(mclist->addr);
1080*4882a593Smuzhiyun mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1081*4882a593Smuzhiyun mcast_addr, 0, MLX4_MCAST_CONFIG);
1082*4882a593Smuzhiyun }
1083*4882a593Smuzhiyun err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1084*4882a593Smuzhiyun 0, MLX4_MCAST_ENABLE);
1085*4882a593Smuzhiyun if (err)
1086*4882a593Smuzhiyun en_err(priv, "Failed enabling multicast filter\n");
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1089*4882a593Smuzhiyun list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1090*4882a593Smuzhiyun if (mclist->action == MCLIST_REM) {
1091*4882a593Smuzhiyun /* detach this address and delete from list */
1092*4882a593Smuzhiyun memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1093*4882a593Smuzhiyun mc_list[5] = priv->port;
1094*4882a593Smuzhiyun err = mlx4_multicast_detach(mdev->dev,
1095*4882a593Smuzhiyun priv->rss_map.indir_qp,
1096*4882a593Smuzhiyun mc_list,
1097*4882a593Smuzhiyun MLX4_PROT_ETH,
1098*4882a593Smuzhiyun mclist->reg_id);
1099*4882a593Smuzhiyun if (err)
1100*4882a593Smuzhiyun en_err(priv, "Fail to detach multicast address\n");
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun if (mclist->tunnel_reg_id) {
1103*4882a593Smuzhiyun err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1104*4882a593Smuzhiyun if (err)
1105*4882a593Smuzhiyun en_err(priv, "Failed to detach multicast address\n");
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun /* remove from list */
1109*4882a593Smuzhiyun list_del(&mclist->list);
1110*4882a593Smuzhiyun kfree(mclist);
1111*4882a593Smuzhiyun } else if (mclist->action == MCLIST_ADD) {
1112*4882a593Smuzhiyun /* attach the address */
1113*4882a593Smuzhiyun memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1114*4882a593Smuzhiyun /* needed for B0 steering support */
1115*4882a593Smuzhiyun mc_list[5] = priv->port;
1116*4882a593Smuzhiyun err = mlx4_multicast_attach(mdev->dev,
1117*4882a593Smuzhiyun priv->rss_map.indir_qp,
1118*4882a593Smuzhiyun mc_list,
1119*4882a593Smuzhiyun priv->port, 0,
1120*4882a593Smuzhiyun MLX4_PROT_ETH,
1121*4882a593Smuzhiyun &mclist->reg_id);
1122*4882a593Smuzhiyun if (err)
1123*4882a593Smuzhiyun en_err(priv, "Fail to attach multicast address\n");
1124*4882a593Smuzhiyun
1125*4882a593Smuzhiyun err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1126*4882a593Smuzhiyun &mclist->tunnel_reg_id);
1127*4882a593Smuzhiyun if (err)
1128*4882a593Smuzhiyun en_err(priv, "Failed to attach multicast address\n");
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun }
1132*4882a593Smuzhiyun }
1133*4882a593Smuzhiyun
mlx4_en_do_uc_filter(struct mlx4_en_priv * priv,struct net_device * dev,struct mlx4_en_dev * mdev)1134*4882a593Smuzhiyun static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1135*4882a593Smuzhiyun struct net_device *dev,
1136*4882a593Smuzhiyun struct mlx4_en_dev *mdev)
1137*4882a593Smuzhiyun {
1138*4882a593Smuzhiyun struct netdev_hw_addr *ha;
1139*4882a593Smuzhiyun struct mlx4_mac_entry *entry;
1140*4882a593Smuzhiyun struct hlist_node *tmp;
1141*4882a593Smuzhiyun bool found;
1142*4882a593Smuzhiyun u64 mac;
1143*4882a593Smuzhiyun int err = 0;
1144*4882a593Smuzhiyun struct hlist_head *bucket;
1145*4882a593Smuzhiyun unsigned int i;
1146*4882a593Smuzhiyun int removed = 0;
1147*4882a593Smuzhiyun u32 prev_flags;
1148*4882a593Smuzhiyun
1149*4882a593Smuzhiyun /* Note that we do not need to protect our mac_hash traversal with rcu,
1150*4882a593Smuzhiyun * since all modification code is protected by mdev->state_lock
1151*4882a593Smuzhiyun */
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun /* find what to remove */
1154*4882a593Smuzhiyun for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1155*4882a593Smuzhiyun bucket = &priv->mac_hash[i];
1156*4882a593Smuzhiyun hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1157*4882a593Smuzhiyun found = false;
1158*4882a593Smuzhiyun netdev_for_each_uc_addr(ha, dev) {
1159*4882a593Smuzhiyun if (ether_addr_equal_64bits(entry->mac,
1160*4882a593Smuzhiyun ha->addr)) {
1161*4882a593Smuzhiyun found = true;
1162*4882a593Smuzhiyun break;
1163*4882a593Smuzhiyun }
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun /* MAC address of the port is not in uc list */
1167*4882a593Smuzhiyun if (ether_addr_equal_64bits(entry->mac,
1168*4882a593Smuzhiyun priv->current_mac))
1169*4882a593Smuzhiyun found = true;
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun if (!found) {
1172*4882a593Smuzhiyun mac = mlx4_mac_to_u64(entry->mac);
1173*4882a593Smuzhiyun mlx4_en_uc_steer_release(priv, entry->mac,
1174*4882a593Smuzhiyun priv->base_qpn,
1175*4882a593Smuzhiyun entry->reg_id);
1176*4882a593Smuzhiyun mlx4_unregister_mac(mdev->dev, priv->port, mac);
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun hlist_del_rcu(&entry->hlist);
1179*4882a593Smuzhiyun kfree_rcu(entry, rcu);
1180*4882a593Smuzhiyun en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1181*4882a593Smuzhiyun entry->mac, priv->port);
1182*4882a593Smuzhiyun ++removed;
1183*4882a593Smuzhiyun }
1184*4882a593Smuzhiyun }
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun /* if we didn't remove anything, there is no use in trying to add
1188*4882a593Smuzhiyun * again once we are in a forced promisc mode state
1189*4882a593Smuzhiyun */
1190*4882a593Smuzhiyun if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1191*4882a593Smuzhiyun return;
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun prev_flags = priv->flags;
1194*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun /* find what to add */
1197*4882a593Smuzhiyun netdev_for_each_uc_addr(ha, dev) {
1198*4882a593Smuzhiyun found = false;
1199*4882a593Smuzhiyun bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
1200*4882a593Smuzhiyun hlist_for_each_entry(entry, bucket, hlist) {
1201*4882a593Smuzhiyun if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1202*4882a593Smuzhiyun found = true;
1203*4882a593Smuzhiyun break;
1204*4882a593Smuzhiyun }
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun if (!found) {
1208*4882a593Smuzhiyun entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1209*4882a593Smuzhiyun if (!entry) {
1210*4882a593Smuzhiyun en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1211*4882a593Smuzhiyun ha->addr, priv->port);
1212*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1213*4882a593Smuzhiyun break;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun mac = mlx4_mac_to_u64(ha->addr);
1216*4882a593Smuzhiyun memcpy(entry->mac, ha->addr, ETH_ALEN);
1217*4882a593Smuzhiyun err = mlx4_register_mac(mdev->dev, priv->port, mac);
1218*4882a593Smuzhiyun if (err < 0) {
1219*4882a593Smuzhiyun en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1220*4882a593Smuzhiyun ha->addr, priv->port, err);
1221*4882a593Smuzhiyun kfree(entry);
1222*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1223*4882a593Smuzhiyun break;
1224*4882a593Smuzhiyun }
1225*4882a593Smuzhiyun err = mlx4_en_uc_steer_add(priv, ha->addr,
1226*4882a593Smuzhiyun &priv->base_qpn,
1227*4882a593Smuzhiyun &entry->reg_id);
1228*4882a593Smuzhiyun if (err) {
1229*4882a593Smuzhiyun en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1230*4882a593Smuzhiyun ha->addr, priv->port, err);
1231*4882a593Smuzhiyun mlx4_unregister_mac(mdev->dev, priv->port, mac);
1232*4882a593Smuzhiyun kfree(entry);
1233*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1234*4882a593Smuzhiyun break;
1235*4882a593Smuzhiyun } else {
1236*4882a593Smuzhiyun unsigned int mac_hash;
1237*4882a593Smuzhiyun en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1238*4882a593Smuzhiyun ha->addr, priv->port);
1239*4882a593Smuzhiyun mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1240*4882a593Smuzhiyun bucket = &priv->mac_hash[mac_hash];
1241*4882a593Smuzhiyun hlist_add_head_rcu(&entry->hlist, bucket);
1242*4882a593Smuzhiyun }
1243*4882a593Smuzhiyun }
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1247*4882a593Smuzhiyun en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1248*4882a593Smuzhiyun priv->port);
1249*4882a593Smuzhiyun } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1250*4882a593Smuzhiyun en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1251*4882a593Smuzhiyun priv->port);
1252*4882a593Smuzhiyun }
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun
mlx4_en_do_set_rx_mode(struct work_struct * work)1255*4882a593Smuzhiyun static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1256*4882a593Smuzhiyun {
1257*4882a593Smuzhiyun struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1258*4882a593Smuzhiyun rx_mode_task);
1259*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1260*4882a593Smuzhiyun struct net_device *dev = priv->dev;
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
1263*4882a593Smuzhiyun if (!mdev->device_up) {
1264*4882a593Smuzhiyun en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1265*4882a593Smuzhiyun goto out;
1266*4882a593Smuzhiyun }
1267*4882a593Smuzhiyun if (!priv->port_up) {
1268*4882a593Smuzhiyun en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1269*4882a593Smuzhiyun goto out;
1270*4882a593Smuzhiyun }
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun if (!netif_carrier_ok(dev)) {
1273*4882a593Smuzhiyun if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1274*4882a593Smuzhiyun if (priv->port_state.link_state) {
1275*4882a593Smuzhiyun priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1276*4882a593Smuzhiyun netif_carrier_on(dev);
1277*4882a593Smuzhiyun en_dbg(LINK, priv, "Link Up\n");
1278*4882a593Smuzhiyun }
1279*4882a593Smuzhiyun }
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun if (dev->priv_flags & IFF_UNICAST_FLT)
1283*4882a593Smuzhiyun mlx4_en_do_uc_filter(priv, dev, mdev);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun /* Promsicuous mode: disable all filters */
1286*4882a593Smuzhiyun if ((dev->flags & IFF_PROMISC) ||
1287*4882a593Smuzhiyun (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
1288*4882a593Smuzhiyun mlx4_en_set_promisc_mode(priv, mdev);
1289*4882a593Smuzhiyun goto out;
1290*4882a593Smuzhiyun }
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun /* Not in promiscuous mode */
1293*4882a593Smuzhiyun if (priv->flags & MLX4_EN_FLAG_PROMISC)
1294*4882a593Smuzhiyun mlx4_en_clear_promisc_mode(priv, mdev);
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun mlx4_en_do_multicast(priv, dev, mdev);
1297*4882a593Smuzhiyun out:
1298*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
1299*4882a593Smuzhiyun }
1300*4882a593Smuzhiyun
mlx4_en_set_rss_steer_rules(struct mlx4_en_priv * priv)1301*4882a593Smuzhiyun static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv)
1302*4882a593Smuzhiyun {
1303*4882a593Smuzhiyun u64 reg_id;
1304*4882a593Smuzhiyun int err = 0;
1305*4882a593Smuzhiyun int *qpn = &priv->base_qpn;
1306*4882a593Smuzhiyun struct mlx4_mac_entry *entry;
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, ®_id);
1309*4882a593Smuzhiyun if (err)
1310*4882a593Smuzhiyun return err;
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
1313*4882a593Smuzhiyun &priv->tunnel_reg_id);
1314*4882a593Smuzhiyun if (err)
1315*4882a593Smuzhiyun goto tunnel_err;
1316*4882a593Smuzhiyun
1317*4882a593Smuzhiyun entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1318*4882a593Smuzhiyun if (!entry) {
1319*4882a593Smuzhiyun err = -ENOMEM;
1320*4882a593Smuzhiyun goto alloc_err;
1321*4882a593Smuzhiyun }
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
1324*4882a593Smuzhiyun memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
1325*4882a593Smuzhiyun entry->reg_id = reg_id;
1326*4882a593Smuzhiyun hlist_add_head_rcu(&entry->hlist,
1327*4882a593Smuzhiyun &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
1328*4882a593Smuzhiyun
1329*4882a593Smuzhiyun return 0;
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun alloc_err:
1332*4882a593Smuzhiyun if (priv->tunnel_reg_id)
1333*4882a593Smuzhiyun mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun tunnel_err:
1336*4882a593Smuzhiyun mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
1337*4882a593Smuzhiyun return err;
1338*4882a593Smuzhiyun }
1339*4882a593Smuzhiyun
mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv * priv)1340*4882a593Smuzhiyun static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv)
1341*4882a593Smuzhiyun {
1342*4882a593Smuzhiyun u64 mac;
1343*4882a593Smuzhiyun unsigned int i;
1344*4882a593Smuzhiyun int qpn = priv->base_qpn;
1345*4882a593Smuzhiyun struct hlist_head *bucket;
1346*4882a593Smuzhiyun struct hlist_node *tmp;
1347*4882a593Smuzhiyun struct mlx4_mac_entry *entry;
1348*4882a593Smuzhiyun
1349*4882a593Smuzhiyun for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1350*4882a593Smuzhiyun bucket = &priv->mac_hash[i];
1351*4882a593Smuzhiyun hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1352*4882a593Smuzhiyun mac = mlx4_mac_to_u64(entry->mac);
1353*4882a593Smuzhiyun en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n",
1354*4882a593Smuzhiyun entry->mac);
1355*4882a593Smuzhiyun mlx4_en_uc_steer_release(priv, entry->mac,
1356*4882a593Smuzhiyun qpn, entry->reg_id);
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun mlx4_unregister_mac(priv->mdev->dev, priv->port, mac);
1359*4882a593Smuzhiyun hlist_del_rcu(&entry->hlist);
1360*4882a593Smuzhiyun kfree_rcu(entry, rcu);
1361*4882a593Smuzhiyun }
1362*4882a593Smuzhiyun }
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun if (priv->tunnel_reg_id) {
1365*4882a593Smuzhiyun mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1366*4882a593Smuzhiyun priv->tunnel_reg_id = 0;
1367*4882a593Smuzhiyun }
1368*4882a593Smuzhiyun }
1369*4882a593Smuzhiyun
mlx4_en_tx_timeout(struct net_device * dev,unsigned int txqueue)1370*4882a593Smuzhiyun static void mlx4_en_tx_timeout(struct net_device *dev, unsigned int txqueue)
1371*4882a593Smuzhiyun {
1372*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1373*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1374*4882a593Smuzhiyun struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX][txqueue];
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun if (netif_msg_timer(priv))
1377*4882a593Smuzhiyun en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
1380*4882a593Smuzhiyun txqueue, tx_ring->qpn, tx_ring->sp_cqn,
1381*4882a593Smuzhiyun tx_ring->cons, tx_ring->prod);
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun priv->port_stats.tx_timeout++;
1384*4882a593Smuzhiyun if (!test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state)) {
1385*4882a593Smuzhiyun en_dbg(DRV, priv, "Scheduling port restart\n");
1386*4882a593Smuzhiyun queue_work(mdev->workqueue, &priv->restart_task);
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun static void
mlx4_en_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)1392*4882a593Smuzhiyun mlx4_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1393*4882a593Smuzhiyun {
1394*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun spin_lock_bh(&priv->stats_lock);
1397*4882a593Smuzhiyun mlx4_en_fold_software_stats(dev);
1398*4882a593Smuzhiyun netdev_stats_to_stats64(stats, &dev->stats);
1399*4882a593Smuzhiyun spin_unlock_bh(&priv->stats_lock);
1400*4882a593Smuzhiyun }
1401*4882a593Smuzhiyun
mlx4_en_set_default_moderation(struct mlx4_en_priv * priv)1402*4882a593Smuzhiyun static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1403*4882a593Smuzhiyun {
1404*4882a593Smuzhiyun struct mlx4_en_cq *cq;
1405*4882a593Smuzhiyun int i, t;
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun /* If we haven't received a specific coalescing setting
1408*4882a593Smuzhiyun * (module param), we set the moderation parameters as follows:
1409*4882a593Smuzhiyun * - moder_cnt is set to the number of mtu sized packets to
1410*4882a593Smuzhiyun * satisfy our coalescing target.
1411*4882a593Smuzhiyun * - moder_time is set to a fixed value.
1412*4882a593Smuzhiyun */
1413*4882a593Smuzhiyun priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
1414*4882a593Smuzhiyun priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
1415*4882a593Smuzhiyun priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1416*4882a593Smuzhiyun priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
1417*4882a593Smuzhiyun en_dbg(INTR, priv, "Default coalescing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1418*4882a593Smuzhiyun priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun /* Setup cq moderation params */
1421*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
1422*4882a593Smuzhiyun cq = priv->rx_cq[i];
1423*4882a593Smuzhiyun cq->moder_cnt = priv->rx_frames;
1424*4882a593Smuzhiyun cq->moder_time = priv->rx_usecs;
1425*4882a593Smuzhiyun priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1426*4882a593Smuzhiyun priv->last_moder_packets[i] = 0;
1427*4882a593Smuzhiyun priv->last_moder_bytes[i] = 0;
1428*4882a593Smuzhiyun }
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
1431*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++) {
1432*4882a593Smuzhiyun cq = priv->tx_cq[t][i];
1433*4882a593Smuzhiyun cq->moder_cnt = priv->tx_frames;
1434*4882a593Smuzhiyun cq->moder_time = priv->tx_usecs;
1435*4882a593Smuzhiyun }
1436*4882a593Smuzhiyun }
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun /* Reset auto-moderation params */
1439*4882a593Smuzhiyun priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1440*4882a593Smuzhiyun priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1441*4882a593Smuzhiyun priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1442*4882a593Smuzhiyun priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1443*4882a593Smuzhiyun priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
1444*4882a593Smuzhiyun priv->adaptive_rx_coal = 1;
1445*4882a593Smuzhiyun priv->last_moder_jiffies = 0;
1446*4882a593Smuzhiyun priv->last_moder_tx_packets = 0;
1447*4882a593Smuzhiyun }
1448*4882a593Smuzhiyun
mlx4_en_auto_moderation(struct mlx4_en_priv * priv)1449*4882a593Smuzhiyun static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1450*4882a593Smuzhiyun {
1451*4882a593Smuzhiyun unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
1452*4882a593Smuzhiyun u32 pkt_rate_high, pkt_rate_low;
1453*4882a593Smuzhiyun struct mlx4_en_cq *cq;
1454*4882a593Smuzhiyun unsigned long packets;
1455*4882a593Smuzhiyun unsigned long rate;
1456*4882a593Smuzhiyun unsigned long avg_pkt_size;
1457*4882a593Smuzhiyun unsigned long rx_packets;
1458*4882a593Smuzhiyun unsigned long rx_bytes;
1459*4882a593Smuzhiyun unsigned long rx_pkt_diff;
1460*4882a593Smuzhiyun int moder_time;
1461*4882a593Smuzhiyun int ring, err;
1462*4882a593Smuzhiyun
1463*4882a593Smuzhiyun if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1464*4882a593Smuzhiyun return;
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun pkt_rate_low = READ_ONCE(priv->pkt_rate_low);
1467*4882a593Smuzhiyun pkt_rate_high = READ_ONCE(priv->pkt_rate_high);
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun for (ring = 0; ring < priv->rx_ring_num; ring++) {
1470*4882a593Smuzhiyun rx_packets = READ_ONCE(priv->rx_ring[ring]->packets);
1471*4882a593Smuzhiyun rx_bytes = READ_ONCE(priv->rx_ring[ring]->bytes);
1472*4882a593Smuzhiyun
1473*4882a593Smuzhiyun rx_pkt_diff = rx_packets - priv->last_moder_packets[ring];
1474*4882a593Smuzhiyun packets = rx_pkt_diff;
1475*4882a593Smuzhiyun rate = packets * HZ / period;
1476*4882a593Smuzhiyun avg_pkt_size = packets ? (rx_bytes -
1477*4882a593Smuzhiyun priv->last_moder_bytes[ring]) / packets : 0;
1478*4882a593Smuzhiyun
1479*4882a593Smuzhiyun /* Apply auto-moderation only when packet rate
1480*4882a593Smuzhiyun * exceeds a rate that it matters */
1481*4882a593Smuzhiyun if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1482*4882a593Smuzhiyun avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
1483*4882a593Smuzhiyun if (rate <= pkt_rate_low)
1484*4882a593Smuzhiyun moder_time = priv->rx_usecs_low;
1485*4882a593Smuzhiyun else if (rate >= pkt_rate_high)
1486*4882a593Smuzhiyun moder_time = priv->rx_usecs_high;
1487*4882a593Smuzhiyun else
1488*4882a593Smuzhiyun moder_time = (rate - pkt_rate_low) *
1489*4882a593Smuzhiyun (priv->rx_usecs_high - priv->rx_usecs_low) /
1490*4882a593Smuzhiyun (pkt_rate_high - pkt_rate_low) +
1491*4882a593Smuzhiyun priv->rx_usecs_low;
1492*4882a593Smuzhiyun } else {
1493*4882a593Smuzhiyun moder_time = priv->rx_usecs_low;
1494*4882a593Smuzhiyun }
1495*4882a593Smuzhiyun
1496*4882a593Smuzhiyun cq = priv->rx_cq[ring];
1497*4882a593Smuzhiyun if (moder_time != priv->last_moder_time[ring] ||
1498*4882a593Smuzhiyun cq->moder_cnt != priv->rx_frames) {
1499*4882a593Smuzhiyun priv->last_moder_time[ring] = moder_time;
1500*4882a593Smuzhiyun cq->moder_time = moder_time;
1501*4882a593Smuzhiyun cq->moder_cnt = priv->rx_frames;
1502*4882a593Smuzhiyun err = mlx4_en_set_cq_moder(priv, cq);
1503*4882a593Smuzhiyun if (err)
1504*4882a593Smuzhiyun en_err(priv, "Failed modifying moderation for cq:%d\n",
1505*4882a593Smuzhiyun ring);
1506*4882a593Smuzhiyun }
1507*4882a593Smuzhiyun priv->last_moder_packets[ring] = rx_packets;
1508*4882a593Smuzhiyun priv->last_moder_bytes[ring] = rx_bytes;
1509*4882a593Smuzhiyun }
1510*4882a593Smuzhiyun
1511*4882a593Smuzhiyun priv->last_moder_jiffies = jiffies;
1512*4882a593Smuzhiyun }
1513*4882a593Smuzhiyun
mlx4_en_do_get_stats(struct work_struct * work)1514*4882a593Smuzhiyun static void mlx4_en_do_get_stats(struct work_struct *work)
1515*4882a593Smuzhiyun {
1516*4882a593Smuzhiyun struct delayed_work *delay = to_delayed_work(work);
1517*4882a593Smuzhiyun struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1518*4882a593Smuzhiyun stats_task);
1519*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1520*4882a593Smuzhiyun int err;
1521*4882a593Smuzhiyun
1522*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
1523*4882a593Smuzhiyun if (mdev->device_up) {
1524*4882a593Smuzhiyun if (priv->port_up) {
1525*4882a593Smuzhiyun err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1526*4882a593Smuzhiyun if (err)
1527*4882a593Smuzhiyun en_dbg(HW, priv, "Could not update stats\n");
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun mlx4_en_auto_moderation(priv);
1530*4882a593Smuzhiyun }
1531*4882a593Smuzhiyun
1532*4882a593Smuzhiyun queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1533*4882a593Smuzhiyun }
1534*4882a593Smuzhiyun if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
1535*4882a593Smuzhiyun mlx4_en_do_set_mac(priv, priv->current_mac);
1536*4882a593Smuzhiyun mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1537*4882a593Smuzhiyun }
1538*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
1539*4882a593Smuzhiyun }
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun /* mlx4_en_service_task - Run service task for tasks that needed to be done
1542*4882a593Smuzhiyun * periodically
1543*4882a593Smuzhiyun */
mlx4_en_service_task(struct work_struct * work)1544*4882a593Smuzhiyun static void mlx4_en_service_task(struct work_struct *work)
1545*4882a593Smuzhiyun {
1546*4882a593Smuzhiyun struct delayed_work *delay = to_delayed_work(work);
1547*4882a593Smuzhiyun struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1548*4882a593Smuzhiyun service_task);
1549*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1550*4882a593Smuzhiyun
1551*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
1552*4882a593Smuzhiyun if (mdev->device_up) {
1553*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1554*4882a593Smuzhiyun mlx4_en_ptp_overflow_check(mdev);
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun mlx4_en_recover_from_oom(priv);
1557*4882a593Smuzhiyun queue_delayed_work(mdev->workqueue, &priv->service_task,
1558*4882a593Smuzhiyun SERVICE_TASK_DELAY);
1559*4882a593Smuzhiyun }
1560*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
1561*4882a593Smuzhiyun }
1562*4882a593Smuzhiyun
mlx4_en_linkstate(struct work_struct * work)1563*4882a593Smuzhiyun static void mlx4_en_linkstate(struct work_struct *work)
1564*4882a593Smuzhiyun {
1565*4882a593Smuzhiyun struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1566*4882a593Smuzhiyun linkstate_task);
1567*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1568*4882a593Smuzhiyun int linkstate = priv->link_state;
1569*4882a593Smuzhiyun
1570*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
1571*4882a593Smuzhiyun /* If observable port state changed set carrier state and
1572*4882a593Smuzhiyun * report to system log */
1573*4882a593Smuzhiyun if (priv->last_link_state != linkstate) {
1574*4882a593Smuzhiyun if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
1575*4882a593Smuzhiyun en_info(priv, "Link Down\n");
1576*4882a593Smuzhiyun netif_carrier_off(priv->dev);
1577*4882a593Smuzhiyun } else {
1578*4882a593Smuzhiyun en_info(priv, "Link Up\n");
1579*4882a593Smuzhiyun netif_carrier_on(priv->dev);
1580*4882a593Smuzhiyun }
1581*4882a593Smuzhiyun }
1582*4882a593Smuzhiyun priv->last_link_state = linkstate;
1583*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
1584*4882a593Smuzhiyun }
1585*4882a593Smuzhiyun
mlx4_en_init_affinity_hint(struct mlx4_en_priv * priv,int ring_idx)1586*4882a593Smuzhiyun static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1587*4882a593Smuzhiyun {
1588*4882a593Smuzhiyun struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1589*4882a593Smuzhiyun int numa_node = priv->mdev->dev->numa_node;
1590*4882a593Smuzhiyun
1591*4882a593Smuzhiyun if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1592*4882a593Smuzhiyun return -ENOMEM;
1593*4882a593Smuzhiyun
1594*4882a593Smuzhiyun cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node),
1595*4882a593Smuzhiyun ring->affinity_mask);
1596*4882a593Smuzhiyun return 0;
1597*4882a593Smuzhiyun }
1598*4882a593Smuzhiyun
mlx4_en_free_affinity_hint(struct mlx4_en_priv * priv,int ring_idx)1599*4882a593Smuzhiyun static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1600*4882a593Smuzhiyun {
1601*4882a593Smuzhiyun free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1602*4882a593Smuzhiyun }
1603*4882a593Smuzhiyun
mlx4_en_init_recycle_ring(struct mlx4_en_priv * priv,int tx_ring_idx)1604*4882a593Smuzhiyun static void mlx4_en_init_recycle_ring(struct mlx4_en_priv *priv,
1605*4882a593Smuzhiyun int tx_ring_idx)
1606*4882a593Smuzhiyun {
1607*4882a593Smuzhiyun struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX_XDP][tx_ring_idx];
1608*4882a593Smuzhiyun int rr_index = tx_ring_idx;
1609*4882a593Smuzhiyun
1610*4882a593Smuzhiyun tx_ring->free_tx_desc = mlx4_en_recycle_tx_desc;
1611*4882a593Smuzhiyun tx_ring->recycle_ring = priv->rx_ring[rr_index];
1612*4882a593Smuzhiyun en_dbg(DRV, priv, "Set tx_ring[%d][%d]->recycle_ring = rx_ring[%d]\n",
1613*4882a593Smuzhiyun TX_XDP, tx_ring_idx, rr_index);
1614*4882a593Smuzhiyun }
1615*4882a593Smuzhiyun
mlx4_en_start_port(struct net_device * dev)1616*4882a593Smuzhiyun int mlx4_en_start_port(struct net_device *dev)
1617*4882a593Smuzhiyun {
1618*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1619*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1620*4882a593Smuzhiyun struct mlx4_en_cq *cq;
1621*4882a593Smuzhiyun struct mlx4_en_tx_ring *tx_ring;
1622*4882a593Smuzhiyun int rx_index = 0;
1623*4882a593Smuzhiyun int err = 0;
1624*4882a593Smuzhiyun int i, t;
1625*4882a593Smuzhiyun int j;
1626*4882a593Smuzhiyun u8 mc_list[16] = {0};
1627*4882a593Smuzhiyun
1628*4882a593Smuzhiyun if (priv->port_up) {
1629*4882a593Smuzhiyun en_dbg(DRV, priv, "start port called while port already up\n");
1630*4882a593Smuzhiyun return 0;
1631*4882a593Smuzhiyun }
1632*4882a593Smuzhiyun
1633*4882a593Smuzhiyun INIT_LIST_HEAD(&priv->mc_list);
1634*4882a593Smuzhiyun INIT_LIST_HEAD(&priv->curr_list);
1635*4882a593Smuzhiyun INIT_LIST_HEAD(&priv->ethtool_list);
1636*4882a593Smuzhiyun memset(&priv->ethtool_rules[0], 0,
1637*4882a593Smuzhiyun sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
1638*4882a593Smuzhiyun
1639*4882a593Smuzhiyun /* Calculate Rx buf size */
1640*4882a593Smuzhiyun dev->mtu = min(dev->mtu, priv->max_mtu);
1641*4882a593Smuzhiyun mlx4_en_calc_rx_buf(dev);
1642*4882a593Smuzhiyun en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
1643*4882a593Smuzhiyun
1644*4882a593Smuzhiyun /* Configure rx cq's and rings */
1645*4882a593Smuzhiyun err = mlx4_en_activate_rx_rings(priv);
1646*4882a593Smuzhiyun if (err) {
1647*4882a593Smuzhiyun en_err(priv, "Failed to activate RX rings\n");
1648*4882a593Smuzhiyun return err;
1649*4882a593Smuzhiyun }
1650*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
1651*4882a593Smuzhiyun cq = priv->rx_cq[i];
1652*4882a593Smuzhiyun
1653*4882a593Smuzhiyun err = mlx4_en_init_affinity_hint(priv, i);
1654*4882a593Smuzhiyun if (err) {
1655*4882a593Smuzhiyun en_err(priv, "Failed preparing IRQ affinity hint\n");
1656*4882a593Smuzhiyun goto cq_err;
1657*4882a593Smuzhiyun }
1658*4882a593Smuzhiyun
1659*4882a593Smuzhiyun err = mlx4_en_activate_cq(priv, cq, i);
1660*4882a593Smuzhiyun if (err) {
1661*4882a593Smuzhiyun en_err(priv, "Failed activating Rx CQ\n");
1662*4882a593Smuzhiyun mlx4_en_free_affinity_hint(priv, i);
1663*4882a593Smuzhiyun goto cq_err;
1664*4882a593Smuzhiyun }
1665*4882a593Smuzhiyun
1666*4882a593Smuzhiyun for (j = 0; j < cq->size; j++) {
1667*4882a593Smuzhiyun struct mlx4_cqe *cqe = NULL;
1668*4882a593Smuzhiyun
1669*4882a593Smuzhiyun cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1670*4882a593Smuzhiyun priv->cqe_factor;
1671*4882a593Smuzhiyun cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1672*4882a593Smuzhiyun }
1673*4882a593Smuzhiyun
1674*4882a593Smuzhiyun err = mlx4_en_set_cq_moder(priv, cq);
1675*4882a593Smuzhiyun if (err) {
1676*4882a593Smuzhiyun en_err(priv, "Failed setting cq moderation parameters\n");
1677*4882a593Smuzhiyun mlx4_en_deactivate_cq(priv, cq);
1678*4882a593Smuzhiyun mlx4_en_free_affinity_hint(priv, i);
1679*4882a593Smuzhiyun goto cq_err;
1680*4882a593Smuzhiyun }
1681*4882a593Smuzhiyun mlx4_en_arm_cq(priv, cq);
1682*4882a593Smuzhiyun priv->rx_ring[i]->cqn = cq->mcq.cqn;
1683*4882a593Smuzhiyun ++rx_index;
1684*4882a593Smuzhiyun }
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun /* Set qp number */
1687*4882a593Smuzhiyun en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
1688*4882a593Smuzhiyun err = mlx4_en_get_qp(priv);
1689*4882a593Smuzhiyun if (err) {
1690*4882a593Smuzhiyun en_err(priv, "Failed getting eth qp\n");
1691*4882a593Smuzhiyun goto cq_err;
1692*4882a593Smuzhiyun }
1693*4882a593Smuzhiyun mdev->mac_removed[priv->port] = 0;
1694*4882a593Smuzhiyun
1695*4882a593Smuzhiyun priv->counter_index =
1696*4882a593Smuzhiyun mlx4_get_default_counter_index(mdev->dev, priv->port);
1697*4882a593Smuzhiyun
1698*4882a593Smuzhiyun err = mlx4_en_config_rss_steer(priv);
1699*4882a593Smuzhiyun if (err) {
1700*4882a593Smuzhiyun en_err(priv, "Failed configuring rss steering\n");
1701*4882a593Smuzhiyun goto mac_err;
1702*4882a593Smuzhiyun }
1703*4882a593Smuzhiyun
1704*4882a593Smuzhiyun err = mlx4_en_create_drop_qp(priv);
1705*4882a593Smuzhiyun if (err)
1706*4882a593Smuzhiyun goto rss_err;
1707*4882a593Smuzhiyun
1708*4882a593Smuzhiyun /* Configure tx cq's and rings */
1709*4882a593Smuzhiyun for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
1710*4882a593Smuzhiyun u8 num_tx_rings_p_up = t == TX ?
1711*4882a593Smuzhiyun priv->num_tx_rings_p_up : priv->tx_ring_num[t];
1712*4882a593Smuzhiyun
1713*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++) {
1714*4882a593Smuzhiyun /* Configure cq */
1715*4882a593Smuzhiyun cq = priv->tx_cq[t][i];
1716*4882a593Smuzhiyun err = mlx4_en_activate_cq(priv, cq, i);
1717*4882a593Smuzhiyun if (err) {
1718*4882a593Smuzhiyun en_err(priv, "Failed allocating Tx CQ\n");
1719*4882a593Smuzhiyun goto tx_err;
1720*4882a593Smuzhiyun }
1721*4882a593Smuzhiyun err = mlx4_en_set_cq_moder(priv, cq);
1722*4882a593Smuzhiyun if (err) {
1723*4882a593Smuzhiyun en_err(priv, "Failed setting cq moderation parameters\n");
1724*4882a593Smuzhiyun mlx4_en_deactivate_cq(priv, cq);
1725*4882a593Smuzhiyun goto tx_err;
1726*4882a593Smuzhiyun }
1727*4882a593Smuzhiyun en_dbg(DRV, priv,
1728*4882a593Smuzhiyun "Resetting index of collapsed CQ:%d to -1\n", i);
1729*4882a593Smuzhiyun cq->buf->wqe_index = cpu_to_be16(0xffff);
1730*4882a593Smuzhiyun
1731*4882a593Smuzhiyun /* Configure ring */
1732*4882a593Smuzhiyun tx_ring = priv->tx_ring[t][i];
1733*4882a593Smuzhiyun err = mlx4_en_activate_tx_ring(priv, tx_ring,
1734*4882a593Smuzhiyun cq->mcq.cqn,
1735*4882a593Smuzhiyun i / num_tx_rings_p_up);
1736*4882a593Smuzhiyun if (err) {
1737*4882a593Smuzhiyun en_err(priv, "Failed allocating Tx ring\n");
1738*4882a593Smuzhiyun mlx4_en_deactivate_cq(priv, cq);
1739*4882a593Smuzhiyun goto tx_err;
1740*4882a593Smuzhiyun }
1741*4882a593Smuzhiyun clear_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &tx_ring->state);
1742*4882a593Smuzhiyun if (t != TX_XDP) {
1743*4882a593Smuzhiyun tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
1744*4882a593Smuzhiyun tx_ring->recycle_ring = NULL;
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun /* Arm CQ for TX completions */
1747*4882a593Smuzhiyun mlx4_en_arm_cq(priv, cq);
1748*4882a593Smuzhiyun
1749*4882a593Smuzhiyun } else {
1750*4882a593Smuzhiyun mlx4_en_init_tx_xdp_ring_descs(priv, tx_ring);
1751*4882a593Smuzhiyun mlx4_en_init_recycle_ring(priv, i);
1752*4882a593Smuzhiyun /* XDP TX CQ should never be armed */
1753*4882a593Smuzhiyun }
1754*4882a593Smuzhiyun
1755*4882a593Smuzhiyun /* Set initial ownership of all Tx TXBBs to SW (1) */
1756*4882a593Smuzhiyun for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1757*4882a593Smuzhiyun *((u32 *)(tx_ring->buf + j)) = 0xffffffff;
1758*4882a593Smuzhiyun }
1759*4882a593Smuzhiyun }
1760*4882a593Smuzhiyun
1761*4882a593Smuzhiyun /* Configure port */
1762*4882a593Smuzhiyun err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1763*4882a593Smuzhiyun priv->rx_skb_size + ETH_FCS_LEN,
1764*4882a593Smuzhiyun priv->prof->tx_pause,
1765*4882a593Smuzhiyun priv->prof->tx_ppp,
1766*4882a593Smuzhiyun priv->prof->rx_pause,
1767*4882a593Smuzhiyun priv->prof->rx_ppp);
1768*4882a593Smuzhiyun if (err) {
1769*4882a593Smuzhiyun en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1770*4882a593Smuzhiyun priv->port, err);
1771*4882a593Smuzhiyun goto tx_err;
1772*4882a593Smuzhiyun }
1773*4882a593Smuzhiyun
1774*4882a593Smuzhiyun err = mlx4_SET_PORT_user_mtu(mdev->dev, priv->port, dev->mtu);
1775*4882a593Smuzhiyun if (err) {
1776*4882a593Smuzhiyun en_err(priv, "Failed to pass user MTU(%d) to Firmware for port %d, with error %d\n",
1777*4882a593Smuzhiyun dev->mtu, priv->port, err);
1778*4882a593Smuzhiyun goto tx_err;
1779*4882a593Smuzhiyun }
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun /* Set default qp number */
1782*4882a593Smuzhiyun err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1783*4882a593Smuzhiyun if (err) {
1784*4882a593Smuzhiyun en_err(priv, "Failed setting default qp numbers\n");
1785*4882a593Smuzhiyun goto tx_err;
1786*4882a593Smuzhiyun }
1787*4882a593Smuzhiyun
1788*4882a593Smuzhiyun if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1789*4882a593Smuzhiyun err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
1790*4882a593Smuzhiyun if (err) {
1791*4882a593Smuzhiyun en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1792*4882a593Smuzhiyun err);
1793*4882a593Smuzhiyun goto tx_err;
1794*4882a593Smuzhiyun }
1795*4882a593Smuzhiyun }
1796*4882a593Smuzhiyun
1797*4882a593Smuzhiyun /* Init port */
1798*4882a593Smuzhiyun en_dbg(HW, priv, "Initializing port\n");
1799*4882a593Smuzhiyun err = mlx4_INIT_PORT(mdev->dev, priv->port);
1800*4882a593Smuzhiyun if (err) {
1801*4882a593Smuzhiyun en_err(priv, "Failed Initializing port\n");
1802*4882a593Smuzhiyun goto tx_err;
1803*4882a593Smuzhiyun }
1804*4882a593Smuzhiyun
1805*4882a593Smuzhiyun /* Set Unicast and VXLAN steering rules */
1806*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 &&
1807*4882a593Smuzhiyun mlx4_en_set_rss_steer_rules(priv))
1808*4882a593Smuzhiyun mlx4_warn(mdev, "Failed setting steering rules\n");
1809*4882a593Smuzhiyun
1810*4882a593Smuzhiyun /* Attach rx QP to bradcast address */
1811*4882a593Smuzhiyun eth_broadcast_addr(&mc_list[10]);
1812*4882a593Smuzhiyun mc_list[5] = priv->port; /* needed for B0 steering support */
1813*4882a593Smuzhiyun if (mlx4_multicast_attach(mdev->dev, priv->rss_map.indir_qp, mc_list,
1814*4882a593Smuzhiyun priv->port, 0, MLX4_PROT_ETH,
1815*4882a593Smuzhiyun &priv->broadcast_id))
1816*4882a593Smuzhiyun mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1817*4882a593Smuzhiyun
1818*4882a593Smuzhiyun /* Must redo promiscuous mode setup. */
1819*4882a593Smuzhiyun priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1820*4882a593Smuzhiyun
1821*4882a593Smuzhiyun /* Schedule multicast task to populate multicast list */
1822*4882a593Smuzhiyun queue_work(mdev->workqueue, &priv->rx_mode_task);
1823*4882a593Smuzhiyun
1824*4882a593Smuzhiyun if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1825*4882a593Smuzhiyun udp_tunnel_nic_reset_ntf(dev);
1826*4882a593Smuzhiyun
1827*4882a593Smuzhiyun priv->port_up = true;
1828*4882a593Smuzhiyun
1829*4882a593Smuzhiyun /* Process all completions if exist to prevent
1830*4882a593Smuzhiyun * the queues freezing if they are full
1831*4882a593Smuzhiyun */
1832*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
1833*4882a593Smuzhiyun local_bh_disable();
1834*4882a593Smuzhiyun napi_schedule(&priv->rx_cq[i]->napi);
1835*4882a593Smuzhiyun local_bh_enable();
1836*4882a593Smuzhiyun }
1837*4882a593Smuzhiyun
1838*4882a593Smuzhiyun clear_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state);
1839*4882a593Smuzhiyun netif_tx_start_all_queues(dev);
1840*4882a593Smuzhiyun netif_device_attach(dev);
1841*4882a593Smuzhiyun
1842*4882a593Smuzhiyun return 0;
1843*4882a593Smuzhiyun
1844*4882a593Smuzhiyun tx_err:
1845*4882a593Smuzhiyun if (t == MLX4_EN_NUM_TX_TYPES) {
1846*4882a593Smuzhiyun t--;
1847*4882a593Smuzhiyun i = priv->tx_ring_num[t];
1848*4882a593Smuzhiyun }
1849*4882a593Smuzhiyun while (t >= 0) {
1850*4882a593Smuzhiyun while (i--) {
1851*4882a593Smuzhiyun mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[t][i]);
1852*4882a593Smuzhiyun mlx4_en_deactivate_cq(priv, priv->tx_cq[t][i]);
1853*4882a593Smuzhiyun }
1854*4882a593Smuzhiyun if (!t--)
1855*4882a593Smuzhiyun break;
1856*4882a593Smuzhiyun i = priv->tx_ring_num[t];
1857*4882a593Smuzhiyun }
1858*4882a593Smuzhiyun mlx4_en_destroy_drop_qp(priv);
1859*4882a593Smuzhiyun rss_err:
1860*4882a593Smuzhiyun mlx4_en_release_rss_steer(priv);
1861*4882a593Smuzhiyun mac_err:
1862*4882a593Smuzhiyun mlx4_en_put_qp(priv);
1863*4882a593Smuzhiyun cq_err:
1864*4882a593Smuzhiyun while (rx_index--) {
1865*4882a593Smuzhiyun mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
1866*4882a593Smuzhiyun mlx4_en_free_affinity_hint(priv, rx_index);
1867*4882a593Smuzhiyun }
1868*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++)
1869*4882a593Smuzhiyun mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
1870*4882a593Smuzhiyun
1871*4882a593Smuzhiyun return err; /* need to close devices */
1872*4882a593Smuzhiyun }
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun
mlx4_en_stop_port(struct net_device * dev,int detach)1875*4882a593Smuzhiyun void mlx4_en_stop_port(struct net_device *dev, int detach)
1876*4882a593Smuzhiyun {
1877*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1878*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1879*4882a593Smuzhiyun struct mlx4_en_mc_list *mclist, *tmp;
1880*4882a593Smuzhiyun struct ethtool_flow_id *flow, *tmp_flow;
1881*4882a593Smuzhiyun int i, t;
1882*4882a593Smuzhiyun u8 mc_list[16] = {0};
1883*4882a593Smuzhiyun
1884*4882a593Smuzhiyun if (!priv->port_up) {
1885*4882a593Smuzhiyun en_dbg(DRV, priv, "stop port called while port already down\n");
1886*4882a593Smuzhiyun return;
1887*4882a593Smuzhiyun }
1888*4882a593Smuzhiyun
1889*4882a593Smuzhiyun /* close port*/
1890*4882a593Smuzhiyun mlx4_CLOSE_PORT(mdev->dev, priv->port);
1891*4882a593Smuzhiyun
1892*4882a593Smuzhiyun /* Synchronize with tx routine */
1893*4882a593Smuzhiyun netif_tx_lock_bh(dev);
1894*4882a593Smuzhiyun if (detach)
1895*4882a593Smuzhiyun netif_device_detach(dev);
1896*4882a593Smuzhiyun netif_tx_stop_all_queues(dev);
1897*4882a593Smuzhiyun netif_tx_unlock_bh(dev);
1898*4882a593Smuzhiyun
1899*4882a593Smuzhiyun netif_tx_disable(dev);
1900*4882a593Smuzhiyun
1901*4882a593Smuzhiyun spin_lock_bh(&priv->stats_lock);
1902*4882a593Smuzhiyun mlx4_en_fold_software_stats(dev);
1903*4882a593Smuzhiyun /* Set port as not active */
1904*4882a593Smuzhiyun priv->port_up = false;
1905*4882a593Smuzhiyun spin_unlock_bh(&priv->stats_lock);
1906*4882a593Smuzhiyun
1907*4882a593Smuzhiyun priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
1908*4882a593Smuzhiyun
1909*4882a593Smuzhiyun /* Promsicuous mode */
1910*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode ==
1911*4882a593Smuzhiyun MLX4_STEERING_MODE_DEVICE_MANAGED) {
1912*4882a593Smuzhiyun priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1913*4882a593Smuzhiyun MLX4_EN_FLAG_MC_PROMISC);
1914*4882a593Smuzhiyun mlx4_flow_steer_promisc_remove(mdev->dev,
1915*4882a593Smuzhiyun priv->port,
1916*4882a593Smuzhiyun MLX4_FS_ALL_DEFAULT);
1917*4882a593Smuzhiyun mlx4_flow_steer_promisc_remove(mdev->dev,
1918*4882a593Smuzhiyun priv->port,
1919*4882a593Smuzhiyun MLX4_FS_MC_DEFAULT);
1920*4882a593Smuzhiyun } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1921*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun /* Disable promiscouos mode */
1924*4882a593Smuzhiyun mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1925*4882a593Smuzhiyun priv->port);
1926*4882a593Smuzhiyun
1927*4882a593Smuzhiyun /* Disable Multicast promisc */
1928*4882a593Smuzhiyun if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1929*4882a593Smuzhiyun mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1930*4882a593Smuzhiyun priv->port);
1931*4882a593Smuzhiyun priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1932*4882a593Smuzhiyun }
1933*4882a593Smuzhiyun }
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun /* Detach All multicasts */
1936*4882a593Smuzhiyun eth_broadcast_addr(&mc_list[10]);
1937*4882a593Smuzhiyun mc_list[5] = priv->port; /* needed for B0 steering support */
1938*4882a593Smuzhiyun mlx4_multicast_detach(mdev->dev, priv->rss_map.indir_qp, mc_list,
1939*4882a593Smuzhiyun MLX4_PROT_ETH, priv->broadcast_id);
1940*4882a593Smuzhiyun list_for_each_entry(mclist, &priv->curr_list, list) {
1941*4882a593Smuzhiyun memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1942*4882a593Smuzhiyun mc_list[5] = priv->port;
1943*4882a593Smuzhiyun mlx4_multicast_detach(mdev->dev, priv->rss_map.indir_qp,
1944*4882a593Smuzhiyun mc_list, MLX4_PROT_ETH, mclist->reg_id);
1945*4882a593Smuzhiyun if (mclist->tunnel_reg_id)
1946*4882a593Smuzhiyun mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1947*4882a593Smuzhiyun }
1948*4882a593Smuzhiyun mlx4_en_clear_list(dev);
1949*4882a593Smuzhiyun list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1950*4882a593Smuzhiyun list_del(&mclist->list);
1951*4882a593Smuzhiyun kfree(mclist);
1952*4882a593Smuzhiyun }
1953*4882a593Smuzhiyun
1954*4882a593Smuzhiyun /* Flush multicast filter */
1955*4882a593Smuzhiyun mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1956*4882a593Smuzhiyun
1957*4882a593Smuzhiyun /* Remove flow steering rules for the port*/
1958*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode ==
1959*4882a593Smuzhiyun MLX4_STEERING_MODE_DEVICE_MANAGED) {
1960*4882a593Smuzhiyun ASSERT_RTNL();
1961*4882a593Smuzhiyun list_for_each_entry_safe(flow, tmp_flow,
1962*4882a593Smuzhiyun &priv->ethtool_list, list) {
1963*4882a593Smuzhiyun mlx4_flow_detach(mdev->dev, flow->id);
1964*4882a593Smuzhiyun list_del(&flow->list);
1965*4882a593Smuzhiyun }
1966*4882a593Smuzhiyun }
1967*4882a593Smuzhiyun
1968*4882a593Smuzhiyun mlx4_en_destroy_drop_qp(priv);
1969*4882a593Smuzhiyun
1970*4882a593Smuzhiyun /* Free TX Rings */
1971*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
1972*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++) {
1973*4882a593Smuzhiyun mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[t][i]);
1974*4882a593Smuzhiyun mlx4_en_deactivate_cq(priv, priv->tx_cq[t][i]);
1975*4882a593Smuzhiyun }
1976*4882a593Smuzhiyun }
1977*4882a593Smuzhiyun msleep(10);
1978*4882a593Smuzhiyun
1979*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1980*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++)
1981*4882a593Smuzhiyun mlx4_en_free_tx_buf(dev, priv->tx_ring[t][i]);
1982*4882a593Smuzhiyun
1983*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
1984*4882a593Smuzhiyun mlx4_en_delete_rss_steer_rules(priv);
1985*4882a593Smuzhiyun
1986*4882a593Smuzhiyun /* Free RSS qps */
1987*4882a593Smuzhiyun mlx4_en_release_rss_steer(priv);
1988*4882a593Smuzhiyun
1989*4882a593Smuzhiyun /* Unregister Mac address for the port */
1990*4882a593Smuzhiyun mlx4_en_put_qp(priv);
1991*4882a593Smuzhiyun if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
1992*4882a593Smuzhiyun mdev->mac_removed[priv->port] = 1;
1993*4882a593Smuzhiyun
1994*4882a593Smuzhiyun /* Free RX Rings */
1995*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
1996*4882a593Smuzhiyun struct mlx4_en_cq *cq = priv->rx_cq[i];
1997*4882a593Smuzhiyun
1998*4882a593Smuzhiyun napi_synchronize(&cq->napi);
1999*4882a593Smuzhiyun mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
2000*4882a593Smuzhiyun mlx4_en_deactivate_cq(priv, cq);
2001*4882a593Smuzhiyun
2002*4882a593Smuzhiyun mlx4_en_free_affinity_hint(priv, i);
2003*4882a593Smuzhiyun }
2004*4882a593Smuzhiyun }
2005*4882a593Smuzhiyun
mlx4_en_restart(struct work_struct * work)2006*4882a593Smuzhiyun static void mlx4_en_restart(struct work_struct *work)
2007*4882a593Smuzhiyun {
2008*4882a593Smuzhiyun struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2009*4882a593Smuzhiyun restart_task);
2010*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2011*4882a593Smuzhiyun struct net_device *dev = priv->dev;
2012*4882a593Smuzhiyun
2013*4882a593Smuzhiyun en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
2014*4882a593Smuzhiyun
2015*4882a593Smuzhiyun rtnl_lock();
2016*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
2017*4882a593Smuzhiyun if (priv->port_up) {
2018*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
2019*4882a593Smuzhiyun if (mlx4_en_start_port(dev))
2020*4882a593Smuzhiyun en_err(priv, "Failed restarting port %d\n", priv->port);
2021*4882a593Smuzhiyun }
2022*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
2023*4882a593Smuzhiyun rtnl_unlock();
2024*4882a593Smuzhiyun }
2025*4882a593Smuzhiyun
mlx4_en_clear_stats(struct net_device * dev)2026*4882a593Smuzhiyun static void mlx4_en_clear_stats(struct net_device *dev)
2027*4882a593Smuzhiyun {
2028*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2029*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2030*4882a593Smuzhiyun struct mlx4_en_tx_ring **tx_ring;
2031*4882a593Smuzhiyun int i;
2032*4882a593Smuzhiyun
2033*4882a593Smuzhiyun if (!mlx4_is_slave(mdev->dev))
2034*4882a593Smuzhiyun if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
2035*4882a593Smuzhiyun en_dbg(HW, priv, "Failed dumping statistics\n");
2036*4882a593Smuzhiyun
2037*4882a593Smuzhiyun memset(&priv->pstats, 0, sizeof(priv->pstats));
2038*4882a593Smuzhiyun memset(&priv->pkstats, 0, sizeof(priv->pkstats));
2039*4882a593Smuzhiyun memset(&priv->port_stats, 0, sizeof(priv->port_stats));
2040*4882a593Smuzhiyun memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
2041*4882a593Smuzhiyun memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
2042*4882a593Smuzhiyun memset(&priv->rx_priority_flowstats, 0,
2043*4882a593Smuzhiyun sizeof(priv->rx_priority_flowstats));
2044*4882a593Smuzhiyun memset(&priv->tx_priority_flowstats, 0,
2045*4882a593Smuzhiyun sizeof(priv->tx_priority_flowstats));
2046*4882a593Smuzhiyun memset(&priv->pf_stats, 0, sizeof(priv->pf_stats));
2047*4882a593Smuzhiyun
2048*4882a593Smuzhiyun tx_ring = priv->tx_ring[TX];
2049*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[TX]; i++) {
2050*4882a593Smuzhiyun tx_ring[i]->bytes = 0;
2051*4882a593Smuzhiyun tx_ring[i]->packets = 0;
2052*4882a593Smuzhiyun tx_ring[i]->tx_csum = 0;
2053*4882a593Smuzhiyun tx_ring[i]->tx_dropped = 0;
2054*4882a593Smuzhiyun tx_ring[i]->queue_stopped = 0;
2055*4882a593Smuzhiyun tx_ring[i]->wake_queue = 0;
2056*4882a593Smuzhiyun tx_ring[i]->tso_packets = 0;
2057*4882a593Smuzhiyun tx_ring[i]->xmit_more = 0;
2058*4882a593Smuzhiyun }
2059*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
2060*4882a593Smuzhiyun priv->rx_ring[i]->bytes = 0;
2061*4882a593Smuzhiyun priv->rx_ring[i]->packets = 0;
2062*4882a593Smuzhiyun priv->rx_ring[i]->csum_ok = 0;
2063*4882a593Smuzhiyun priv->rx_ring[i]->csum_none = 0;
2064*4882a593Smuzhiyun priv->rx_ring[i]->csum_complete = 0;
2065*4882a593Smuzhiyun }
2066*4882a593Smuzhiyun }
2067*4882a593Smuzhiyun
mlx4_en_open(struct net_device * dev)2068*4882a593Smuzhiyun static int mlx4_en_open(struct net_device *dev)
2069*4882a593Smuzhiyun {
2070*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2071*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2072*4882a593Smuzhiyun int err = 0;
2073*4882a593Smuzhiyun
2074*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
2075*4882a593Smuzhiyun
2076*4882a593Smuzhiyun if (!mdev->device_up) {
2077*4882a593Smuzhiyun en_err(priv, "Cannot open - device down/disabled\n");
2078*4882a593Smuzhiyun err = -EBUSY;
2079*4882a593Smuzhiyun goto out;
2080*4882a593Smuzhiyun }
2081*4882a593Smuzhiyun
2082*4882a593Smuzhiyun /* Reset HW statistics and SW counters */
2083*4882a593Smuzhiyun mlx4_en_clear_stats(dev);
2084*4882a593Smuzhiyun
2085*4882a593Smuzhiyun err = mlx4_en_start_port(dev);
2086*4882a593Smuzhiyun if (err)
2087*4882a593Smuzhiyun en_err(priv, "Failed starting port:%d\n", priv->port);
2088*4882a593Smuzhiyun
2089*4882a593Smuzhiyun out:
2090*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
2091*4882a593Smuzhiyun return err;
2092*4882a593Smuzhiyun }
2093*4882a593Smuzhiyun
2094*4882a593Smuzhiyun
mlx4_en_close(struct net_device * dev)2095*4882a593Smuzhiyun static int mlx4_en_close(struct net_device *dev)
2096*4882a593Smuzhiyun {
2097*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2098*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2099*4882a593Smuzhiyun
2100*4882a593Smuzhiyun en_dbg(IFDOWN, priv, "Close port called\n");
2101*4882a593Smuzhiyun
2102*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
2103*4882a593Smuzhiyun
2104*4882a593Smuzhiyun mlx4_en_stop_port(dev, 0);
2105*4882a593Smuzhiyun netif_carrier_off(dev);
2106*4882a593Smuzhiyun
2107*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
2108*4882a593Smuzhiyun return 0;
2109*4882a593Smuzhiyun }
2110*4882a593Smuzhiyun
mlx4_en_free_resources(struct mlx4_en_priv * priv)2111*4882a593Smuzhiyun static void mlx4_en_free_resources(struct mlx4_en_priv *priv)
2112*4882a593Smuzhiyun {
2113*4882a593Smuzhiyun int i, t;
2114*4882a593Smuzhiyun
2115*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
2116*4882a593Smuzhiyun priv->dev->rx_cpu_rmap = NULL;
2117*4882a593Smuzhiyun #endif
2118*4882a593Smuzhiyun
2119*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2120*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++) {
2121*4882a593Smuzhiyun if (priv->tx_ring[t] && priv->tx_ring[t][i])
2122*4882a593Smuzhiyun mlx4_en_destroy_tx_ring(priv,
2123*4882a593Smuzhiyun &priv->tx_ring[t][i]);
2124*4882a593Smuzhiyun if (priv->tx_cq[t] && priv->tx_cq[t][i])
2125*4882a593Smuzhiyun mlx4_en_destroy_cq(priv, &priv->tx_cq[t][i]);
2126*4882a593Smuzhiyun }
2127*4882a593Smuzhiyun kfree(priv->tx_ring[t]);
2128*4882a593Smuzhiyun kfree(priv->tx_cq[t]);
2129*4882a593Smuzhiyun }
2130*4882a593Smuzhiyun
2131*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
2132*4882a593Smuzhiyun if (priv->rx_ring[i])
2133*4882a593Smuzhiyun mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2134*4882a593Smuzhiyun priv->prof->rx_ring_size, priv->stride);
2135*4882a593Smuzhiyun if (priv->rx_cq[i])
2136*4882a593Smuzhiyun mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2137*4882a593Smuzhiyun }
2138*4882a593Smuzhiyun
2139*4882a593Smuzhiyun }
2140*4882a593Smuzhiyun
mlx4_en_alloc_resources(struct mlx4_en_priv * priv)2141*4882a593Smuzhiyun static int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
2142*4882a593Smuzhiyun {
2143*4882a593Smuzhiyun struct mlx4_en_port_profile *prof = priv->prof;
2144*4882a593Smuzhiyun int i, t;
2145*4882a593Smuzhiyun int node;
2146*4882a593Smuzhiyun
2147*4882a593Smuzhiyun /* Create tx Rings */
2148*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2149*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++) {
2150*4882a593Smuzhiyun node = cpu_to_node(i % num_online_cpus());
2151*4882a593Smuzhiyun if (mlx4_en_create_cq(priv, &priv->tx_cq[t][i],
2152*4882a593Smuzhiyun prof->tx_ring_size, i, t, node))
2153*4882a593Smuzhiyun goto err;
2154*4882a593Smuzhiyun
2155*4882a593Smuzhiyun if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[t][i],
2156*4882a593Smuzhiyun prof->tx_ring_size,
2157*4882a593Smuzhiyun TXBB_SIZE, node, i))
2158*4882a593Smuzhiyun goto err;
2159*4882a593Smuzhiyun }
2160*4882a593Smuzhiyun }
2161*4882a593Smuzhiyun
2162*4882a593Smuzhiyun /* Create rx Rings */
2163*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
2164*4882a593Smuzhiyun node = cpu_to_node(i % num_online_cpus());
2165*4882a593Smuzhiyun if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
2166*4882a593Smuzhiyun prof->rx_ring_size, i, RX, node))
2167*4882a593Smuzhiyun goto err;
2168*4882a593Smuzhiyun
2169*4882a593Smuzhiyun if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
2170*4882a593Smuzhiyun prof->rx_ring_size, priv->stride,
2171*4882a593Smuzhiyun node, i))
2172*4882a593Smuzhiyun goto err;
2173*4882a593Smuzhiyun
2174*4882a593Smuzhiyun }
2175*4882a593Smuzhiyun
2176*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
2177*4882a593Smuzhiyun priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port);
2178*4882a593Smuzhiyun #endif
2179*4882a593Smuzhiyun
2180*4882a593Smuzhiyun return 0;
2181*4882a593Smuzhiyun
2182*4882a593Smuzhiyun err:
2183*4882a593Smuzhiyun en_err(priv, "Failed to allocate NIC resources\n");
2184*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
2185*4882a593Smuzhiyun if (priv->rx_ring[i])
2186*4882a593Smuzhiyun mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2187*4882a593Smuzhiyun prof->rx_ring_size,
2188*4882a593Smuzhiyun priv->stride);
2189*4882a593Smuzhiyun if (priv->rx_cq[i])
2190*4882a593Smuzhiyun mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2191*4882a593Smuzhiyun }
2192*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2193*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++) {
2194*4882a593Smuzhiyun if (priv->tx_ring[t][i])
2195*4882a593Smuzhiyun mlx4_en_destroy_tx_ring(priv,
2196*4882a593Smuzhiyun &priv->tx_ring[t][i]);
2197*4882a593Smuzhiyun if (priv->tx_cq[t][i])
2198*4882a593Smuzhiyun mlx4_en_destroy_cq(priv, &priv->tx_cq[t][i]);
2199*4882a593Smuzhiyun }
2200*4882a593Smuzhiyun }
2201*4882a593Smuzhiyun return -ENOMEM;
2202*4882a593Smuzhiyun }
2203*4882a593Smuzhiyun
2204*4882a593Smuzhiyun
mlx4_en_copy_priv(struct mlx4_en_priv * dst,struct mlx4_en_priv * src,struct mlx4_en_port_profile * prof)2205*4882a593Smuzhiyun static int mlx4_en_copy_priv(struct mlx4_en_priv *dst,
2206*4882a593Smuzhiyun struct mlx4_en_priv *src,
2207*4882a593Smuzhiyun struct mlx4_en_port_profile *prof)
2208*4882a593Smuzhiyun {
2209*4882a593Smuzhiyun int t;
2210*4882a593Smuzhiyun
2211*4882a593Smuzhiyun memcpy(&dst->hwtstamp_config, &prof->hwtstamp_config,
2212*4882a593Smuzhiyun sizeof(dst->hwtstamp_config));
2213*4882a593Smuzhiyun dst->num_tx_rings_p_up = prof->num_tx_rings_p_up;
2214*4882a593Smuzhiyun dst->rx_ring_num = prof->rx_ring_num;
2215*4882a593Smuzhiyun dst->flags = prof->flags;
2216*4882a593Smuzhiyun dst->mdev = src->mdev;
2217*4882a593Smuzhiyun dst->port = src->port;
2218*4882a593Smuzhiyun dst->dev = src->dev;
2219*4882a593Smuzhiyun dst->prof = prof;
2220*4882a593Smuzhiyun dst->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2221*4882a593Smuzhiyun DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2222*4882a593Smuzhiyun
2223*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2224*4882a593Smuzhiyun dst->tx_ring_num[t] = prof->tx_ring_num[t];
2225*4882a593Smuzhiyun if (!dst->tx_ring_num[t])
2226*4882a593Smuzhiyun continue;
2227*4882a593Smuzhiyun
2228*4882a593Smuzhiyun dst->tx_ring[t] = kcalloc(MAX_TX_RINGS,
2229*4882a593Smuzhiyun sizeof(struct mlx4_en_tx_ring *),
2230*4882a593Smuzhiyun GFP_KERNEL);
2231*4882a593Smuzhiyun if (!dst->tx_ring[t])
2232*4882a593Smuzhiyun goto err_free_tx;
2233*4882a593Smuzhiyun
2234*4882a593Smuzhiyun dst->tx_cq[t] = kcalloc(MAX_TX_RINGS,
2235*4882a593Smuzhiyun sizeof(struct mlx4_en_cq *),
2236*4882a593Smuzhiyun GFP_KERNEL);
2237*4882a593Smuzhiyun if (!dst->tx_cq[t]) {
2238*4882a593Smuzhiyun kfree(dst->tx_ring[t]);
2239*4882a593Smuzhiyun goto err_free_tx;
2240*4882a593Smuzhiyun }
2241*4882a593Smuzhiyun }
2242*4882a593Smuzhiyun
2243*4882a593Smuzhiyun return 0;
2244*4882a593Smuzhiyun
2245*4882a593Smuzhiyun err_free_tx:
2246*4882a593Smuzhiyun while (t--) {
2247*4882a593Smuzhiyun kfree(dst->tx_ring[t]);
2248*4882a593Smuzhiyun kfree(dst->tx_cq[t]);
2249*4882a593Smuzhiyun }
2250*4882a593Smuzhiyun return -ENOMEM;
2251*4882a593Smuzhiyun }
2252*4882a593Smuzhiyun
mlx4_en_update_priv(struct mlx4_en_priv * dst,struct mlx4_en_priv * src)2253*4882a593Smuzhiyun static void mlx4_en_update_priv(struct mlx4_en_priv *dst,
2254*4882a593Smuzhiyun struct mlx4_en_priv *src)
2255*4882a593Smuzhiyun {
2256*4882a593Smuzhiyun int t;
2257*4882a593Smuzhiyun memcpy(dst->rx_ring, src->rx_ring,
2258*4882a593Smuzhiyun sizeof(struct mlx4_en_rx_ring *) * src->rx_ring_num);
2259*4882a593Smuzhiyun memcpy(dst->rx_cq, src->rx_cq,
2260*4882a593Smuzhiyun sizeof(struct mlx4_en_cq *) * src->rx_ring_num);
2261*4882a593Smuzhiyun memcpy(&dst->hwtstamp_config, &src->hwtstamp_config,
2262*4882a593Smuzhiyun sizeof(dst->hwtstamp_config));
2263*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2264*4882a593Smuzhiyun dst->tx_ring_num[t] = src->tx_ring_num[t];
2265*4882a593Smuzhiyun dst->tx_ring[t] = src->tx_ring[t];
2266*4882a593Smuzhiyun dst->tx_cq[t] = src->tx_cq[t];
2267*4882a593Smuzhiyun }
2268*4882a593Smuzhiyun dst->num_tx_rings_p_up = src->num_tx_rings_p_up;
2269*4882a593Smuzhiyun dst->rx_ring_num = src->rx_ring_num;
2270*4882a593Smuzhiyun memcpy(dst->prof, src->prof, sizeof(struct mlx4_en_port_profile));
2271*4882a593Smuzhiyun }
2272*4882a593Smuzhiyun
mlx4_en_try_alloc_resources(struct mlx4_en_priv * priv,struct mlx4_en_priv * tmp,struct mlx4_en_port_profile * prof,bool carry_xdp_prog)2273*4882a593Smuzhiyun int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
2274*4882a593Smuzhiyun struct mlx4_en_priv *tmp,
2275*4882a593Smuzhiyun struct mlx4_en_port_profile *prof,
2276*4882a593Smuzhiyun bool carry_xdp_prog)
2277*4882a593Smuzhiyun {
2278*4882a593Smuzhiyun struct bpf_prog *xdp_prog;
2279*4882a593Smuzhiyun int i, t, ret;
2280*4882a593Smuzhiyun
2281*4882a593Smuzhiyun ret = mlx4_en_copy_priv(tmp, priv, prof);
2282*4882a593Smuzhiyun if (ret) {
2283*4882a593Smuzhiyun en_warn(priv, "%s: mlx4_en_copy_priv() failed, return\n",
2284*4882a593Smuzhiyun __func__);
2285*4882a593Smuzhiyun return ret;
2286*4882a593Smuzhiyun }
2287*4882a593Smuzhiyun
2288*4882a593Smuzhiyun if (mlx4_en_alloc_resources(tmp)) {
2289*4882a593Smuzhiyun en_warn(priv,
2290*4882a593Smuzhiyun "%s: Resource allocation failed, using previous configuration\n",
2291*4882a593Smuzhiyun __func__);
2292*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2293*4882a593Smuzhiyun kfree(tmp->tx_ring[t]);
2294*4882a593Smuzhiyun kfree(tmp->tx_cq[t]);
2295*4882a593Smuzhiyun }
2296*4882a593Smuzhiyun return -ENOMEM;
2297*4882a593Smuzhiyun }
2298*4882a593Smuzhiyun
2299*4882a593Smuzhiyun /* All rx_rings has the same xdp_prog. Pick the first one. */
2300*4882a593Smuzhiyun xdp_prog = rcu_dereference_protected(
2301*4882a593Smuzhiyun priv->rx_ring[0]->xdp_prog,
2302*4882a593Smuzhiyun lockdep_is_held(&priv->mdev->state_lock));
2303*4882a593Smuzhiyun
2304*4882a593Smuzhiyun if (xdp_prog && carry_xdp_prog) {
2305*4882a593Smuzhiyun bpf_prog_add(xdp_prog, tmp->rx_ring_num);
2306*4882a593Smuzhiyun for (i = 0; i < tmp->rx_ring_num; i++)
2307*4882a593Smuzhiyun rcu_assign_pointer(tmp->rx_ring[i]->xdp_prog,
2308*4882a593Smuzhiyun xdp_prog);
2309*4882a593Smuzhiyun }
2310*4882a593Smuzhiyun
2311*4882a593Smuzhiyun return 0;
2312*4882a593Smuzhiyun }
2313*4882a593Smuzhiyun
mlx4_en_safe_replace_resources(struct mlx4_en_priv * priv,struct mlx4_en_priv * tmp)2314*4882a593Smuzhiyun void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
2315*4882a593Smuzhiyun struct mlx4_en_priv *tmp)
2316*4882a593Smuzhiyun {
2317*4882a593Smuzhiyun mlx4_en_free_resources(priv);
2318*4882a593Smuzhiyun mlx4_en_update_priv(priv, tmp);
2319*4882a593Smuzhiyun }
2320*4882a593Smuzhiyun
mlx4_en_destroy_netdev(struct net_device * dev)2321*4882a593Smuzhiyun void mlx4_en_destroy_netdev(struct net_device *dev)
2322*4882a593Smuzhiyun {
2323*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2324*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2325*4882a593Smuzhiyun
2326*4882a593Smuzhiyun en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
2327*4882a593Smuzhiyun
2328*4882a593Smuzhiyun /* Unregister device - this will close the port if it was up */
2329*4882a593Smuzhiyun if (priv->registered) {
2330*4882a593Smuzhiyun devlink_port_type_clear(mlx4_get_devlink_port(mdev->dev,
2331*4882a593Smuzhiyun priv->port));
2332*4882a593Smuzhiyun unregister_netdev(dev);
2333*4882a593Smuzhiyun }
2334*4882a593Smuzhiyun
2335*4882a593Smuzhiyun if (priv->allocated)
2336*4882a593Smuzhiyun mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2337*4882a593Smuzhiyun
2338*4882a593Smuzhiyun cancel_delayed_work(&priv->stats_task);
2339*4882a593Smuzhiyun cancel_delayed_work(&priv->service_task);
2340*4882a593Smuzhiyun /* flush any pending task for this netdev */
2341*4882a593Smuzhiyun flush_workqueue(mdev->workqueue);
2342*4882a593Smuzhiyun
2343*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2344*4882a593Smuzhiyun mlx4_en_remove_timestamp(mdev);
2345*4882a593Smuzhiyun
2346*4882a593Smuzhiyun /* Detach the netdev so tasks would not attempt to access it */
2347*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
2348*4882a593Smuzhiyun mdev->pndev[priv->port] = NULL;
2349*4882a593Smuzhiyun mdev->upper[priv->port] = NULL;
2350*4882a593Smuzhiyun
2351*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
2352*4882a593Smuzhiyun mlx4_en_cleanup_filters(priv);
2353*4882a593Smuzhiyun #endif
2354*4882a593Smuzhiyun
2355*4882a593Smuzhiyun mlx4_en_free_resources(priv);
2356*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
2357*4882a593Smuzhiyun
2358*4882a593Smuzhiyun free_netdev(dev);
2359*4882a593Smuzhiyun }
2360*4882a593Smuzhiyun
mlx4_en_check_xdp_mtu(struct net_device * dev,int mtu)2361*4882a593Smuzhiyun static bool mlx4_en_check_xdp_mtu(struct net_device *dev, int mtu)
2362*4882a593Smuzhiyun {
2363*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2364*4882a593Smuzhiyun
2365*4882a593Smuzhiyun if (mtu > MLX4_EN_MAX_XDP_MTU) {
2366*4882a593Smuzhiyun en_err(priv, "mtu:%d > max:%d when XDP prog is attached\n",
2367*4882a593Smuzhiyun mtu, MLX4_EN_MAX_XDP_MTU);
2368*4882a593Smuzhiyun return false;
2369*4882a593Smuzhiyun }
2370*4882a593Smuzhiyun
2371*4882a593Smuzhiyun return true;
2372*4882a593Smuzhiyun }
2373*4882a593Smuzhiyun
mlx4_en_change_mtu(struct net_device * dev,int new_mtu)2374*4882a593Smuzhiyun static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2375*4882a593Smuzhiyun {
2376*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2377*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2378*4882a593Smuzhiyun int err = 0;
2379*4882a593Smuzhiyun
2380*4882a593Smuzhiyun en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
2381*4882a593Smuzhiyun dev->mtu, new_mtu);
2382*4882a593Smuzhiyun
2383*4882a593Smuzhiyun if (priv->tx_ring_num[TX_XDP] &&
2384*4882a593Smuzhiyun !mlx4_en_check_xdp_mtu(dev, new_mtu))
2385*4882a593Smuzhiyun return -EOPNOTSUPP;
2386*4882a593Smuzhiyun
2387*4882a593Smuzhiyun dev->mtu = new_mtu;
2388*4882a593Smuzhiyun
2389*4882a593Smuzhiyun if (netif_running(dev)) {
2390*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
2391*4882a593Smuzhiyun if (!mdev->device_up) {
2392*4882a593Smuzhiyun /* NIC is probably restarting - let restart task reset
2393*4882a593Smuzhiyun * the port */
2394*4882a593Smuzhiyun en_dbg(DRV, priv, "Change MTU called with card down!?\n");
2395*4882a593Smuzhiyun } else {
2396*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
2397*4882a593Smuzhiyun err = mlx4_en_start_port(dev);
2398*4882a593Smuzhiyun if (err) {
2399*4882a593Smuzhiyun en_err(priv, "Failed restarting port:%d\n",
2400*4882a593Smuzhiyun priv->port);
2401*4882a593Smuzhiyun if (!test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING,
2402*4882a593Smuzhiyun &priv->state))
2403*4882a593Smuzhiyun queue_work(mdev->workqueue, &priv->restart_task);
2404*4882a593Smuzhiyun }
2405*4882a593Smuzhiyun }
2406*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
2407*4882a593Smuzhiyun }
2408*4882a593Smuzhiyun return 0;
2409*4882a593Smuzhiyun }
2410*4882a593Smuzhiyun
mlx4_en_hwtstamp_set(struct net_device * dev,struct ifreq * ifr)2411*4882a593Smuzhiyun static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2412*4882a593Smuzhiyun {
2413*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2414*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2415*4882a593Smuzhiyun struct hwtstamp_config config;
2416*4882a593Smuzhiyun
2417*4882a593Smuzhiyun if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2418*4882a593Smuzhiyun return -EFAULT;
2419*4882a593Smuzhiyun
2420*4882a593Smuzhiyun /* reserved for future extensions */
2421*4882a593Smuzhiyun if (config.flags)
2422*4882a593Smuzhiyun return -EINVAL;
2423*4882a593Smuzhiyun
2424*4882a593Smuzhiyun /* device doesn't support time stamping */
2425*4882a593Smuzhiyun if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2426*4882a593Smuzhiyun return -EINVAL;
2427*4882a593Smuzhiyun
2428*4882a593Smuzhiyun /* TX HW timestamp */
2429*4882a593Smuzhiyun switch (config.tx_type) {
2430*4882a593Smuzhiyun case HWTSTAMP_TX_OFF:
2431*4882a593Smuzhiyun case HWTSTAMP_TX_ON:
2432*4882a593Smuzhiyun break;
2433*4882a593Smuzhiyun default:
2434*4882a593Smuzhiyun return -ERANGE;
2435*4882a593Smuzhiyun }
2436*4882a593Smuzhiyun
2437*4882a593Smuzhiyun /* RX HW timestamp */
2438*4882a593Smuzhiyun switch (config.rx_filter) {
2439*4882a593Smuzhiyun case HWTSTAMP_FILTER_NONE:
2440*4882a593Smuzhiyun break;
2441*4882a593Smuzhiyun case HWTSTAMP_FILTER_ALL:
2442*4882a593Smuzhiyun case HWTSTAMP_FILTER_SOME:
2443*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2444*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2445*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2446*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2447*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2448*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2449*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2450*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2451*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2452*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_EVENT:
2453*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_SYNC:
2454*4882a593Smuzhiyun case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2455*4882a593Smuzhiyun case HWTSTAMP_FILTER_NTP_ALL:
2456*4882a593Smuzhiyun config.rx_filter = HWTSTAMP_FILTER_ALL;
2457*4882a593Smuzhiyun break;
2458*4882a593Smuzhiyun default:
2459*4882a593Smuzhiyun return -ERANGE;
2460*4882a593Smuzhiyun }
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun if (mlx4_en_reset_config(dev, config, dev->features)) {
2463*4882a593Smuzhiyun config.tx_type = HWTSTAMP_TX_OFF;
2464*4882a593Smuzhiyun config.rx_filter = HWTSTAMP_FILTER_NONE;
2465*4882a593Smuzhiyun }
2466*4882a593Smuzhiyun
2467*4882a593Smuzhiyun return copy_to_user(ifr->ifr_data, &config,
2468*4882a593Smuzhiyun sizeof(config)) ? -EFAULT : 0;
2469*4882a593Smuzhiyun }
2470*4882a593Smuzhiyun
mlx4_en_hwtstamp_get(struct net_device * dev,struct ifreq * ifr)2471*4882a593Smuzhiyun static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2472*4882a593Smuzhiyun {
2473*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2474*4882a593Smuzhiyun
2475*4882a593Smuzhiyun return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2476*4882a593Smuzhiyun sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2477*4882a593Smuzhiyun }
2478*4882a593Smuzhiyun
mlx4_en_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)2479*4882a593Smuzhiyun static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2480*4882a593Smuzhiyun {
2481*4882a593Smuzhiyun switch (cmd) {
2482*4882a593Smuzhiyun case SIOCSHWTSTAMP:
2483*4882a593Smuzhiyun return mlx4_en_hwtstamp_set(dev, ifr);
2484*4882a593Smuzhiyun case SIOCGHWTSTAMP:
2485*4882a593Smuzhiyun return mlx4_en_hwtstamp_get(dev, ifr);
2486*4882a593Smuzhiyun default:
2487*4882a593Smuzhiyun return -EOPNOTSUPP;
2488*4882a593Smuzhiyun }
2489*4882a593Smuzhiyun }
2490*4882a593Smuzhiyun
mlx4_en_fix_features(struct net_device * netdev,netdev_features_t features)2491*4882a593Smuzhiyun static netdev_features_t mlx4_en_fix_features(struct net_device *netdev,
2492*4882a593Smuzhiyun netdev_features_t features)
2493*4882a593Smuzhiyun {
2494*4882a593Smuzhiyun struct mlx4_en_priv *en_priv = netdev_priv(netdev);
2495*4882a593Smuzhiyun struct mlx4_en_dev *mdev = en_priv->mdev;
2496*4882a593Smuzhiyun
2497*4882a593Smuzhiyun /* Since there is no support for separate RX C-TAG/S-TAG vlan accel
2498*4882a593Smuzhiyun * enable/disable make sure S-TAG flag is always in same state as
2499*4882a593Smuzhiyun * C-TAG.
2500*4882a593Smuzhiyun */
2501*4882a593Smuzhiyun if (features & NETIF_F_HW_VLAN_CTAG_RX &&
2502*4882a593Smuzhiyun !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2503*4882a593Smuzhiyun features |= NETIF_F_HW_VLAN_STAG_RX;
2504*4882a593Smuzhiyun else
2505*4882a593Smuzhiyun features &= ~NETIF_F_HW_VLAN_STAG_RX;
2506*4882a593Smuzhiyun
2507*4882a593Smuzhiyun return features;
2508*4882a593Smuzhiyun }
2509*4882a593Smuzhiyun
mlx4_en_set_features(struct net_device * netdev,netdev_features_t features)2510*4882a593Smuzhiyun static int mlx4_en_set_features(struct net_device *netdev,
2511*4882a593Smuzhiyun netdev_features_t features)
2512*4882a593Smuzhiyun {
2513*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(netdev);
2514*4882a593Smuzhiyun bool reset = false;
2515*4882a593Smuzhiyun int ret = 0;
2516*4882a593Smuzhiyun
2517*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) {
2518*4882a593Smuzhiyun en_info(priv, "Turn %s RX-FCS\n",
2519*4882a593Smuzhiyun (features & NETIF_F_RXFCS) ? "ON" : "OFF");
2520*4882a593Smuzhiyun reset = true;
2521*4882a593Smuzhiyun }
2522*4882a593Smuzhiyun
2523*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) {
2524*4882a593Smuzhiyun u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0;
2525*4882a593Smuzhiyun
2526*4882a593Smuzhiyun en_info(priv, "Turn %s RX-ALL\n",
2527*4882a593Smuzhiyun ignore_fcs_value ? "ON" : "OFF");
2528*4882a593Smuzhiyun ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev,
2529*4882a593Smuzhiyun priv->port, ignore_fcs_value);
2530*4882a593Smuzhiyun if (ret)
2531*4882a593Smuzhiyun return ret;
2532*4882a593Smuzhiyun }
2533*4882a593Smuzhiyun
2534*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2535*4882a593Smuzhiyun en_info(priv, "Turn %s RX vlan strip offload\n",
2536*4882a593Smuzhiyun (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
2537*4882a593Smuzhiyun reset = true;
2538*4882a593Smuzhiyun }
2539*4882a593Smuzhiyun
2540*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2541*4882a593Smuzhiyun en_info(priv, "Turn %s TX vlan strip offload\n",
2542*4882a593Smuzhiyun (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2543*4882a593Smuzhiyun
2544*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX))
2545*4882a593Smuzhiyun en_info(priv, "Turn %s TX S-VLAN strip offload\n",
2546*4882a593Smuzhiyun (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF");
2547*4882a593Smuzhiyun
2548*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2549*4882a593Smuzhiyun en_info(priv, "Turn %s loopback\n",
2550*4882a593Smuzhiyun (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2551*4882a593Smuzhiyun mlx4_en_update_loopback_state(netdev, features);
2552*4882a593Smuzhiyun }
2553*4882a593Smuzhiyun
2554*4882a593Smuzhiyun if (reset) {
2555*4882a593Smuzhiyun ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2556*4882a593Smuzhiyun features);
2557*4882a593Smuzhiyun if (ret)
2558*4882a593Smuzhiyun return ret;
2559*4882a593Smuzhiyun }
2560*4882a593Smuzhiyun
2561*4882a593Smuzhiyun return 0;
2562*4882a593Smuzhiyun }
2563*4882a593Smuzhiyun
mlx4_en_set_vf_mac(struct net_device * dev,int queue,u8 * mac)2564*4882a593Smuzhiyun static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2565*4882a593Smuzhiyun {
2566*4882a593Smuzhiyun struct mlx4_en_priv *en_priv = netdev_priv(dev);
2567*4882a593Smuzhiyun struct mlx4_en_dev *mdev = en_priv->mdev;
2568*4882a593Smuzhiyun
2569*4882a593Smuzhiyun return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac);
2570*4882a593Smuzhiyun }
2571*4882a593Smuzhiyun
mlx4_en_set_vf_vlan(struct net_device * dev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2572*4882a593Smuzhiyun static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2573*4882a593Smuzhiyun __be16 vlan_proto)
2574*4882a593Smuzhiyun {
2575*4882a593Smuzhiyun struct mlx4_en_priv *en_priv = netdev_priv(dev);
2576*4882a593Smuzhiyun struct mlx4_en_dev *mdev = en_priv->mdev;
2577*4882a593Smuzhiyun
2578*4882a593Smuzhiyun return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos,
2579*4882a593Smuzhiyun vlan_proto);
2580*4882a593Smuzhiyun }
2581*4882a593Smuzhiyun
mlx4_en_set_vf_rate(struct net_device * dev,int vf,int min_tx_rate,int max_tx_rate)2582*4882a593Smuzhiyun static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2583*4882a593Smuzhiyun int max_tx_rate)
2584*4882a593Smuzhiyun {
2585*4882a593Smuzhiyun struct mlx4_en_priv *en_priv = netdev_priv(dev);
2586*4882a593Smuzhiyun struct mlx4_en_dev *mdev = en_priv->mdev;
2587*4882a593Smuzhiyun
2588*4882a593Smuzhiyun return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2589*4882a593Smuzhiyun max_tx_rate);
2590*4882a593Smuzhiyun }
2591*4882a593Smuzhiyun
mlx4_en_set_vf_spoofchk(struct net_device * dev,int vf,bool setting)2592*4882a593Smuzhiyun static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2593*4882a593Smuzhiyun {
2594*4882a593Smuzhiyun struct mlx4_en_priv *en_priv = netdev_priv(dev);
2595*4882a593Smuzhiyun struct mlx4_en_dev *mdev = en_priv->mdev;
2596*4882a593Smuzhiyun
2597*4882a593Smuzhiyun return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2598*4882a593Smuzhiyun }
2599*4882a593Smuzhiyun
mlx4_en_get_vf_config(struct net_device * dev,int vf,struct ifla_vf_info * ivf)2600*4882a593Smuzhiyun static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2601*4882a593Smuzhiyun {
2602*4882a593Smuzhiyun struct mlx4_en_priv *en_priv = netdev_priv(dev);
2603*4882a593Smuzhiyun struct mlx4_en_dev *mdev = en_priv->mdev;
2604*4882a593Smuzhiyun
2605*4882a593Smuzhiyun return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2606*4882a593Smuzhiyun }
2607*4882a593Smuzhiyun
mlx4_en_set_vf_link_state(struct net_device * dev,int vf,int link_state)2608*4882a593Smuzhiyun static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2609*4882a593Smuzhiyun {
2610*4882a593Smuzhiyun struct mlx4_en_priv *en_priv = netdev_priv(dev);
2611*4882a593Smuzhiyun struct mlx4_en_dev *mdev = en_priv->mdev;
2612*4882a593Smuzhiyun
2613*4882a593Smuzhiyun return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2614*4882a593Smuzhiyun }
2615*4882a593Smuzhiyun
mlx4_en_get_vf_stats(struct net_device * dev,int vf,struct ifla_vf_stats * vf_stats)2616*4882a593Smuzhiyun static int mlx4_en_get_vf_stats(struct net_device *dev, int vf,
2617*4882a593Smuzhiyun struct ifla_vf_stats *vf_stats)
2618*4882a593Smuzhiyun {
2619*4882a593Smuzhiyun struct mlx4_en_priv *en_priv = netdev_priv(dev);
2620*4882a593Smuzhiyun struct mlx4_en_dev *mdev = en_priv->mdev;
2621*4882a593Smuzhiyun
2622*4882a593Smuzhiyun return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats);
2623*4882a593Smuzhiyun }
2624*4882a593Smuzhiyun
2625*4882a593Smuzhiyun #define PORT_ID_BYTE_LEN 8
mlx4_en_get_phys_port_id(struct net_device * dev,struct netdev_phys_item_id * ppid)2626*4882a593Smuzhiyun static int mlx4_en_get_phys_port_id(struct net_device *dev,
2627*4882a593Smuzhiyun struct netdev_phys_item_id *ppid)
2628*4882a593Smuzhiyun {
2629*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2630*4882a593Smuzhiyun struct mlx4_dev *mdev = priv->mdev->dev;
2631*4882a593Smuzhiyun int i;
2632*4882a593Smuzhiyun u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2633*4882a593Smuzhiyun
2634*4882a593Smuzhiyun if (!phys_port_id)
2635*4882a593Smuzhiyun return -EOPNOTSUPP;
2636*4882a593Smuzhiyun
2637*4882a593Smuzhiyun ppid->id_len = sizeof(phys_port_id);
2638*4882a593Smuzhiyun for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2639*4882a593Smuzhiyun ppid->id[i] = phys_port_id & 0xff;
2640*4882a593Smuzhiyun phys_port_id >>= 8;
2641*4882a593Smuzhiyun }
2642*4882a593Smuzhiyun return 0;
2643*4882a593Smuzhiyun }
2644*4882a593Smuzhiyun
mlx4_udp_tunnel_sync(struct net_device * dev,unsigned int table)2645*4882a593Smuzhiyun static int mlx4_udp_tunnel_sync(struct net_device *dev, unsigned int table)
2646*4882a593Smuzhiyun {
2647*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2648*4882a593Smuzhiyun struct udp_tunnel_info ti;
2649*4882a593Smuzhiyun int ret;
2650*4882a593Smuzhiyun
2651*4882a593Smuzhiyun udp_tunnel_nic_get_port(dev, table, 0, &ti);
2652*4882a593Smuzhiyun priv->vxlan_port = ti.port;
2653*4882a593Smuzhiyun
2654*4882a593Smuzhiyun ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2655*4882a593Smuzhiyun if (ret)
2656*4882a593Smuzhiyun return ret;
2657*4882a593Smuzhiyun
2658*4882a593Smuzhiyun return mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2659*4882a593Smuzhiyun VXLAN_STEER_BY_OUTER_MAC,
2660*4882a593Smuzhiyun !!priv->vxlan_port);
2661*4882a593Smuzhiyun }
2662*4882a593Smuzhiyun
2663*4882a593Smuzhiyun static const struct udp_tunnel_nic_info mlx4_udp_tunnels = {
2664*4882a593Smuzhiyun .sync_table = mlx4_udp_tunnel_sync,
2665*4882a593Smuzhiyun .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
2666*4882a593Smuzhiyun UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
2667*4882a593Smuzhiyun .tables = {
2668*4882a593Smuzhiyun { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
2669*4882a593Smuzhiyun },
2670*4882a593Smuzhiyun };
2671*4882a593Smuzhiyun
mlx4_en_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2672*4882a593Smuzhiyun static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2673*4882a593Smuzhiyun struct net_device *dev,
2674*4882a593Smuzhiyun netdev_features_t features)
2675*4882a593Smuzhiyun {
2676*4882a593Smuzhiyun features = vlan_features_check(skb, features);
2677*4882a593Smuzhiyun features = vxlan_features_check(skb, features);
2678*4882a593Smuzhiyun
2679*4882a593Smuzhiyun /* The ConnectX-3 doesn't support outer IPv6 checksums but it does
2680*4882a593Smuzhiyun * support inner IPv6 checksums and segmentation so we need to
2681*4882a593Smuzhiyun * strip that feature if this is an IPv6 encapsulated frame.
2682*4882a593Smuzhiyun */
2683*4882a593Smuzhiyun if (skb->encapsulation &&
2684*4882a593Smuzhiyun (skb->ip_summed == CHECKSUM_PARTIAL)) {
2685*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2686*4882a593Smuzhiyun
2687*4882a593Smuzhiyun if (!priv->vxlan_port ||
2688*4882a593Smuzhiyun (ip_hdr(skb)->version != 4) ||
2689*4882a593Smuzhiyun (udp_hdr(skb)->dest != priv->vxlan_port))
2690*4882a593Smuzhiyun features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2691*4882a593Smuzhiyun }
2692*4882a593Smuzhiyun
2693*4882a593Smuzhiyun return features;
2694*4882a593Smuzhiyun }
2695*4882a593Smuzhiyun
mlx4_en_set_tx_maxrate(struct net_device * dev,int queue_index,u32 maxrate)2696*4882a593Smuzhiyun static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
2697*4882a593Smuzhiyun {
2698*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2699*4882a593Smuzhiyun struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX][queue_index];
2700*4882a593Smuzhiyun struct mlx4_update_qp_params params;
2701*4882a593Smuzhiyun int err;
2702*4882a593Smuzhiyun
2703*4882a593Smuzhiyun if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2704*4882a593Smuzhiyun return -EOPNOTSUPP;
2705*4882a593Smuzhiyun
2706*4882a593Smuzhiyun /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */
2707*4882a593Smuzhiyun if (maxrate >> 12) {
2708*4882a593Smuzhiyun params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2709*4882a593Smuzhiyun params.rate_val = maxrate / 1000;
2710*4882a593Smuzhiyun } else if (maxrate) {
2711*4882a593Smuzhiyun params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2712*4882a593Smuzhiyun params.rate_val = maxrate;
2713*4882a593Smuzhiyun } else { /* zero serves to revoke the QP rate-limitation */
2714*4882a593Smuzhiyun params.rate_unit = 0;
2715*4882a593Smuzhiyun params.rate_val = 0;
2716*4882a593Smuzhiyun }
2717*4882a593Smuzhiyun
2718*4882a593Smuzhiyun err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2719*4882a593Smuzhiyun ¶ms);
2720*4882a593Smuzhiyun return err;
2721*4882a593Smuzhiyun }
2722*4882a593Smuzhiyun
mlx4_xdp_set(struct net_device * dev,struct bpf_prog * prog)2723*4882a593Smuzhiyun static int mlx4_xdp_set(struct net_device *dev, struct bpf_prog *prog)
2724*4882a593Smuzhiyun {
2725*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2726*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2727*4882a593Smuzhiyun struct mlx4_en_port_profile new_prof;
2728*4882a593Smuzhiyun struct bpf_prog *old_prog;
2729*4882a593Smuzhiyun struct mlx4_en_priv *tmp;
2730*4882a593Smuzhiyun int tx_changed = 0;
2731*4882a593Smuzhiyun int xdp_ring_num;
2732*4882a593Smuzhiyun int port_up = 0;
2733*4882a593Smuzhiyun int err;
2734*4882a593Smuzhiyun int i;
2735*4882a593Smuzhiyun
2736*4882a593Smuzhiyun xdp_ring_num = prog ? priv->rx_ring_num : 0;
2737*4882a593Smuzhiyun
2738*4882a593Smuzhiyun /* No need to reconfigure buffers when simply swapping the
2739*4882a593Smuzhiyun * program for a new one.
2740*4882a593Smuzhiyun */
2741*4882a593Smuzhiyun if (priv->tx_ring_num[TX_XDP] == xdp_ring_num) {
2742*4882a593Smuzhiyun if (prog)
2743*4882a593Smuzhiyun bpf_prog_add(prog, priv->rx_ring_num - 1);
2744*4882a593Smuzhiyun
2745*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
2746*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
2747*4882a593Smuzhiyun old_prog = rcu_dereference_protected(
2748*4882a593Smuzhiyun priv->rx_ring[i]->xdp_prog,
2749*4882a593Smuzhiyun lockdep_is_held(&mdev->state_lock));
2750*4882a593Smuzhiyun rcu_assign_pointer(priv->rx_ring[i]->xdp_prog, prog);
2751*4882a593Smuzhiyun if (old_prog)
2752*4882a593Smuzhiyun bpf_prog_put(old_prog);
2753*4882a593Smuzhiyun }
2754*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
2755*4882a593Smuzhiyun return 0;
2756*4882a593Smuzhiyun }
2757*4882a593Smuzhiyun
2758*4882a593Smuzhiyun if (!mlx4_en_check_xdp_mtu(dev, dev->mtu))
2759*4882a593Smuzhiyun return -EOPNOTSUPP;
2760*4882a593Smuzhiyun
2761*4882a593Smuzhiyun tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
2762*4882a593Smuzhiyun if (!tmp)
2763*4882a593Smuzhiyun return -ENOMEM;
2764*4882a593Smuzhiyun
2765*4882a593Smuzhiyun if (prog)
2766*4882a593Smuzhiyun bpf_prog_add(prog, priv->rx_ring_num - 1);
2767*4882a593Smuzhiyun
2768*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
2769*4882a593Smuzhiyun memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
2770*4882a593Smuzhiyun new_prof.tx_ring_num[TX_XDP] = xdp_ring_num;
2771*4882a593Smuzhiyun
2772*4882a593Smuzhiyun if (priv->tx_ring_num[TX] + xdp_ring_num > MAX_TX_RINGS) {
2773*4882a593Smuzhiyun tx_changed = 1;
2774*4882a593Smuzhiyun new_prof.tx_ring_num[TX] =
2775*4882a593Smuzhiyun MAX_TX_RINGS - ALIGN(xdp_ring_num, priv->prof->num_up);
2776*4882a593Smuzhiyun en_warn(priv, "Reducing the number of TX rings, to not exceed the max total rings number.\n");
2777*4882a593Smuzhiyun }
2778*4882a593Smuzhiyun
2779*4882a593Smuzhiyun err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, false);
2780*4882a593Smuzhiyun if (err) {
2781*4882a593Smuzhiyun if (prog)
2782*4882a593Smuzhiyun bpf_prog_sub(prog, priv->rx_ring_num - 1);
2783*4882a593Smuzhiyun goto unlock_out;
2784*4882a593Smuzhiyun }
2785*4882a593Smuzhiyun
2786*4882a593Smuzhiyun if (priv->port_up) {
2787*4882a593Smuzhiyun port_up = 1;
2788*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
2789*4882a593Smuzhiyun }
2790*4882a593Smuzhiyun
2791*4882a593Smuzhiyun mlx4_en_safe_replace_resources(priv, tmp);
2792*4882a593Smuzhiyun if (tx_changed)
2793*4882a593Smuzhiyun netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
2794*4882a593Smuzhiyun
2795*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
2796*4882a593Smuzhiyun old_prog = rcu_dereference_protected(
2797*4882a593Smuzhiyun priv->rx_ring[i]->xdp_prog,
2798*4882a593Smuzhiyun lockdep_is_held(&mdev->state_lock));
2799*4882a593Smuzhiyun rcu_assign_pointer(priv->rx_ring[i]->xdp_prog, prog);
2800*4882a593Smuzhiyun if (old_prog)
2801*4882a593Smuzhiyun bpf_prog_put(old_prog);
2802*4882a593Smuzhiyun }
2803*4882a593Smuzhiyun
2804*4882a593Smuzhiyun if (port_up) {
2805*4882a593Smuzhiyun err = mlx4_en_start_port(dev);
2806*4882a593Smuzhiyun if (err) {
2807*4882a593Smuzhiyun en_err(priv, "Failed starting port %d for XDP change\n",
2808*4882a593Smuzhiyun priv->port);
2809*4882a593Smuzhiyun if (!test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state))
2810*4882a593Smuzhiyun queue_work(mdev->workqueue, &priv->restart_task);
2811*4882a593Smuzhiyun }
2812*4882a593Smuzhiyun }
2813*4882a593Smuzhiyun
2814*4882a593Smuzhiyun unlock_out:
2815*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
2816*4882a593Smuzhiyun kfree(tmp);
2817*4882a593Smuzhiyun return err;
2818*4882a593Smuzhiyun }
2819*4882a593Smuzhiyun
mlx4_xdp(struct net_device * dev,struct netdev_bpf * xdp)2820*4882a593Smuzhiyun static int mlx4_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2821*4882a593Smuzhiyun {
2822*4882a593Smuzhiyun switch (xdp->command) {
2823*4882a593Smuzhiyun case XDP_SETUP_PROG:
2824*4882a593Smuzhiyun return mlx4_xdp_set(dev, xdp->prog);
2825*4882a593Smuzhiyun default:
2826*4882a593Smuzhiyun return -EINVAL;
2827*4882a593Smuzhiyun }
2828*4882a593Smuzhiyun }
2829*4882a593Smuzhiyun
2830*4882a593Smuzhiyun static const struct net_device_ops mlx4_netdev_ops = {
2831*4882a593Smuzhiyun .ndo_open = mlx4_en_open,
2832*4882a593Smuzhiyun .ndo_stop = mlx4_en_close,
2833*4882a593Smuzhiyun .ndo_start_xmit = mlx4_en_xmit,
2834*4882a593Smuzhiyun .ndo_select_queue = mlx4_en_select_queue,
2835*4882a593Smuzhiyun .ndo_get_stats64 = mlx4_en_get_stats64,
2836*4882a593Smuzhiyun .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2837*4882a593Smuzhiyun .ndo_set_mac_address = mlx4_en_set_mac,
2838*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
2839*4882a593Smuzhiyun .ndo_change_mtu = mlx4_en_change_mtu,
2840*4882a593Smuzhiyun .ndo_do_ioctl = mlx4_en_ioctl,
2841*4882a593Smuzhiyun .ndo_tx_timeout = mlx4_en_tx_timeout,
2842*4882a593Smuzhiyun .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2843*4882a593Smuzhiyun .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2844*4882a593Smuzhiyun .ndo_set_features = mlx4_en_set_features,
2845*4882a593Smuzhiyun .ndo_fix_features = mlx4_en_fix_features,
2846*4882a593Smuzhiyun .ndo_setup_tc = __mlx4_en_setup_tc,
2847*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
2848*4882a593Smuzhiyun .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2849*4882a593Smuzhiyun #endif
2850*4882a593Smuzhiyun .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
2851*4882a593Smuzhiyun .ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
2852*4882a593Smuzhiyun .ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
2853*4882a593Smuzhiyun .ndo_features_check = mlx4_en_features_check,
2854*4882a593Smuzhiyun .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
2855*4882a593Smuzhiyun .ndo_bpf = mlx4_xdp,
2856*4882a593Smuzhiyun };
2857*4882a593Smuzhiyun
2858*4882a593Smuzhiyun static const struct net_device_ops mlx4_netdev_ops_master = {
2859*4882a593Smuzhiyun .ndo_open = mlx4_en_open,
2860*4882a593Smuzhiyun .ndo_stop = mlx4_en_close,
2861*4882a593Smuzhiyun .ndo_start_xmit = mlx4_en_xmit,
2862*4882a593Smuzhiyun .ndo_select_queue = mlx4_en_select_queue,
2863*4882a593Smuzhiyun .ndo_get_stats64 = mlx4_en_get_stats64,
2864*4882a593Smuzhiyun .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2865*4882a593Smuzhiyun .ndo_set_mac_address = mlx4_en_set_mac,
2866*4882a593Smuzhiyun .ndo_validate_addr = eth_validate_addr,
2867*4882a593Smuzhiyun .ndo_change_mtu = mlx4_en_change_mtu,
2868*4882a593Smuzhiyun .ndo_tx_timeout = mlx4_en_tx_timeout,
2869*4882a593Smuzhiyun .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2870*4882a593Smuzhiyun .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2871*4882a593Smuzhiyun .ndo_set_vf_mac = mlx4_en_set_vf_mac,
2872*4882a593Smuzhiyun .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
2873*4882a593Smuzhiyun .ndo_set_vf_rate = mlx4_en_set_vf_rate,
2874*4882a593Smuzhiyun .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
2875*4882a593Smuzhiyun .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2876*4882a593Smuzhiyun .ndo_get_vf_stats = mlx4_en_get_vf_stats,
2877*4882a593Smuzhiyun .ndo_get_vf_config = mlx4_en_get_vf_config,
2878*4882a593Smuzhiyun .ndo_set_features = mlx4_en_set_features,
2879*4882a593Smuzhiyun .ndo_fix_features = mlx4_en_fix_features,
2880*4882a593Smuzhiyun .ndo_setup_tc = __mlx4_en_setup_tc,
2881*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
2882*4882a593Smuzhiyun .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2883*4882a593Smuzhiyun #endif
2884*4882a593Smuzhiyun .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
2885*4882a593Smuzhiyun .ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
2886*4882a593Smuzhiyun .ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
2887*4882a593Smuzhiyun .ndo_features_check = mlx4_en_features_check,
2888*4882a593Smuzhiyun .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
2889*4882a593Smuzhiyun .ndo_bpf = mlx4_xdp,
2890*4882a593Smuzhiyun };
2891*4882a593Smuzhiyun
2892*4882a593Smuzhiyun struct mlx4_en_bond {
2893*4882a593Smuzhiyun struct work_struct work;
2894*4882a593Smuzhiyun struct mlx4_en_priv *priv;
2895*4882a593Smuzhiyun int is_bonded;
2896*4882a593Smuzhiyun struct mlx4_port_map port_map;
2897*4882a593Smuzhiyun };
2898*4882a593Smuzhiyun
mlx4_en_bond_work(struct work_struct * work)2899*4882a593Smuzhiyun static void mlx4_en_bond_work(struct work_struct *work)
2900*4882a593Smuzhiyun {
2901*4882a593Smuzhiyun struct mlx4_en_bond *bond = container_of(work,
2902*4882a593Smuzhiyun struct mlx4_en_bond,
2903*4882a593Smuzhiyun work);
2904*4882a593Smuzhiyun int err = 0;
2905*4882a593Smuzhiyun struct mlx4_dev *dev = bond->priv->mdev->dev;
2906*4882a593Smuzhiyun
2907*4882a593Smuzhiyun if (bond->is_bonded) {
2908*4882a593Smuzhiyun if (!mlx4_is_bonded(dev)) {
2909*4882a593Smuzhiyun err = mlx4_bond(dev);
2910*4882a593Smuzhiyun if (err)
2911*4882a593Smuzhiyun en_err(bond->priv, "Fail to bond device\n");
2912*4882a593Smuzhiyun }
2913*4882a593Smuzhiyun if (!err) {
2914*4882a593Smuzhiyun err = mlx4_port_map_set(dev, &bond->port_map);
2915*4882a593Smuzhiyun if (err)
2916*4882a593Smuzhiyun en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
2917*4882a593Smuzhiyun bond->port_map.port1,
2918*4882a593Smuzhiyun bond->port_map.port2,
2919*4882a593Smuzhiyun err);
2920*4882a593Smuzhiyun }
2921*4882a593Smuzhiyun } else if (mlx4_is_bonded(dev)) {
2922*4882a593Smuzhiyun err = mlx4_unbond(dev);
2923*4882a593Smuzhiyun if (err)
2924*4882a593Smuzhiyun en_err(bond->priv, "Fail to unbond device\n");
2925*4882a593Smuzhiyun }
2926*4882a593Smuzhiyun dev_put(bond->priv->dev);
2927*4882a593Smuzhiyun kfree(bond);
2928*4882a593Smuzhiyun }
2929*4882a593Smuzhiyun
mlx4_en_queue_bond_work(struct mlx4_en_priv * priv,int is_bonded,u8 v2p_p1,u8 v2p_p2)2930*4882a593Smuzhiyun static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
2931*4882a593Smuzhiyun u8 v2p_p1, u8 v2p_p2)
2932*4882a593Smuzhiyun {
2933*4882a593Smuzhiyun struct mlx4_en_bond *bond = NULL;
2934*4882a593Smuzhiyun
2935*4882a593Smuzhiyun bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
2936*4882a593Smuzhiyun if (!bond)
2937*4882a593Smuzhiyun return -ENOMEM;
2938*4882a593Smuzhiyun
2939*4882a593Smuzhiyun INIT_WORK(&bond->work, mlx4_en_bond_work);
2940*4882a593Smuzhiyun bond->priv = priv;
2941*4882a593Smuzhiyun bond->is_bonded = is_bonded;
2942*4882a593Smuzhiyun bond->port_map.port1 = v2p_p1;
2943*4882a593Smuzhiyun bond->port_map.port2 = v2p_p2;
2944*4882a593Smuzhiyun dev_hold(priv->dev);
2945*4882a593Smuzhiyun queue_work(priv->mdev->workqueue, &bond->work);
2946*4882a593Smuzhiyun return 0;
2947*4882a593Smuzhiyun }
2948*4882a593Smuzhiyun
mlx4_en_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)2949*4882a593Smuzhiyun int mlx4_en_netdev_event(struct notifier_block *this,
2950*4882a593Smuzhiyun unsigned long event, void *ptr)
2951*4882a593Smuzhiyun {
2952*4882a593Smuzhiyun struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2953*4882a593Smuzhiyun u8 port = 0;
2954*4882a593Smuzhiyun struct mlx4_en_dev *mdev;
2955*4882a593Smuzhiyun struct mlx4_dev *dev;
2956*4882a593Smuzhiyun int i, num_eth_ports = 0;
2957*4882a593Smuzhiyun bool do_bond = true;
2958*4882a593Smuzhiyun struct mlx4_en_priv *priv;
2959*4882a593Smuzhiyun u8 v2p_port1 = 0;
2960*4882a593Smuzhiyun u8 v2p_port2 = 0;
2961*4882a593Smuzhiyun
2962*4882a593Smuzhiyun if (!net_eq(dev_net(ndev), &init_net))
2963*4882a593Smuzhiyun return NOTIFY_DONE;
2964*4882a593Smuzhiyun
2965*4882a593Smuzhiyun mdev = container_of(this, struct mlx4_en_dev, nb);
2966*4882a593Smuzhiyun dev = mdev->dev;
2967*4882a593Smuzhiyun
2968*4882a593Smuzhiyun /* Go into this mode only when two network devices set on two ports
2969*4882a593Smuzhiyun * of the same mlx4 device are slaves of the same bonding master
2970*4882a593Smuzhiyun */
2971*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
2972*4882a593Smuzhiyun ++num_eth_ports;
2973*4882a593Smuzhiyun if (!port && (mdev->pndev[i] == ndev))
2974*4882a593Smuzhiyun port = i;
2975*4882a593Smuzhiyun mdev->upper[i] = mdev->pndev[i] ?
2976*4882a593Smuzhiyun netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
2977*4882a593Smuzhiyun /* condition not met: network device is a slave */
2978*4882a593Smuzhiyun if (!mdev->upper[i])
2979*4882a593Smuzhiyun do_bond = false;
2980*4882a593Smuzhiyun if (num_eth_ports < 2)
2981*4882a593Smuzhiyun continue;
2982*4882a593Smuzhiyun /* condition not met: same master */
2983*4882a593Smuzhiyun if (mdev->upper[i] != mdev->upper[i-1])
2984*4882a593Smuzhiyun do_bond = false;
2985*4882a593Smuzhiyun }
2986*4882a593Smuzhiyun /* condition not met: 2 salves */
2987*4882a593Smuzhiyun do_bond = (num_eth_ports == 2) ? do_bond : false;
2988*4882a593Smuzhiyun
2989*4882a593Smuzhiyun /* handle only events that come with enough info */
2990*4882a593Smuzhiyun if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
2991*4882a593Smuzhiyun return NOTIFY_DONE;
2992*4882a593Smuzhiyun
2993*4882a593Smuzhiyun priv = netdev_priv(ndev);
2994*4882a593Smuzhiyun if (do_bond) {
2995*4882a593Smuzhiyun struct netdev_notifier_bonding_info *notifier_info = ptr;
2996*4882a593Smuzhiyun struct netdev_bonding_info *bonding_info =
2997*4882a593Smuzhiyun ¬ifier_info->bonding_info;
2998*4882a593Smuzhiyun
2999*4882a593Smuzhiyun /* required mode 1, 2 or 4 */
3000*4882a593Smuzhiyun if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
3001*4882a593Smuzhiyun (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
3002*4882a593Smuzhiyun (bonding_info->master.bond_mode != BOND_MODE_8023AD))
3003*4882a593Smuzhiyun do_bond = false;
3004*4882a593Smuzhiyun
3005*4882a593Smuzhiyun /* require exactly 2 slaves */
3006*4882a593Smuzhiyun if (bonding_info->master.num_slaves != 2)
3007*4882a593Smuzhiyun do_bond = false;
3008*4882a593Smuzhiyun
3009*4882a593Smuzhiyun /* calc v2p */
3010*4882a593Smuzhiyun if (do_bond) {
3011*4882a593Smuzhiyun if (bonding_info->master.bond_mode ==
3012*4882a593Smuzhiyun BOND_MODE_ACTIVEBACKUP) {
3013*4882a593Smuzhiyun /* in active-backup mode virtual ports are
3014*4882a593Smuzhiyun * mapped to the physical port of the active
3015*4882a593Smuzhiyun * slave */
3016*4882a593Smuzhiyun if (bonding_info->slave.state ==
3017*4882a593Smuzhiyun BOND_STATE_BACKUP) {
3018*4882a593Smuzhiyun if (port == 1) {
3019*4882a593Smuzhiyun v2p_port1 = 2;
3020*4882a593Smuzhiyun v2p_port2 = 2;
3021*4882a593Smuzhiyun } else {
3022*4882a593Smuzhiyun v2p_port1 = 1;
3023*4882a593Smuzhiyun v2p_port2 = 1;
3024*4882a593Smuzhiyun }
3025*4882a593Smuzhiyun } else { /* BOND_STATE_ACTIVE */
3026*4882a593Smuzhiyun if (port == 1) {
3027*4882a593Smuzhiyun v2p_port1 = 1;
3028*4882a593Smuzhiyun v2p_port2 = 1;
3029*4882a593Smuzhiyun } else {
3030*4882a593Smuzhiyun v2p_port1 = 2;
3031*4882a593Smuzhiyun v2p_port2 = 2;
3032*4882a593Smuzhiyun }
3033*4882a593Smuzhiyun }
3034*4882a593Smuzhiyun } else { /* Active-Active */
3035*4882a593Smuzhiyun /* in active-active mode a virtual port is
3036*4882a593Smuzhiyun * mapped to the native physical port if and only
3037*4882a593Smuzhiyun * if the physical port is up */
3038*4882a593Smuzhiyun __s8 link = bonding_info->slave.link;
3039*4882a593Smuzhiyun
3040*4882a593Smuzhiyun if (port == 1)
3041*4882a593Smuzhiyun v2p_port2 = 2;
3042*4882a593Smuzhiyun else
3043*4882a593Smuzhiyun v2p_port1 = 1;
3044*4882a593Smuzhiyun if ((link == BOND_LINK_UP) ||
3045*4882a593Smuzhiyun (link == BOND_LINK_FAIL)) {
3046*4882a593Smuzhiyun if (port == 1)
3047*4882a593Smuzhiyun v2p_port1 = 1;
3048*4882a593Smuzhiyun else
3049*4882a593Smuzhiyun v2p_port2 = 2;
3050*4882a593Smuzhiyun } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */
3051*4882a593Smuzhiyun if (port == 1)
3052*4882a593Smuzhiyun v2p_port1 = 2;
3053*4882a593Smuzhiyun else
3054*4882a593Smuzhiyun v2p_port2 = 1;
3055*4882a593Smuzhiyun }
3056*4882a593Smuzhiyun }
3057*4882a593Smuzhiyun }
3058*4882a593Smuzhiyun }
3059*4882a593Smuzhiyun
3060*4882a593Smuzhiyun mlx4_en_queue_bond_work(priv, do_bond,
3061*4882a593Smuzhiyun v2p_port1, v2p_port2);
3062*4882a593Smuzhiyun
3063*4882a593Smuzhiyun return NOTIFY_DONE;
3064*4882a593Smuzhiyun }
3065*4882a593Smuzhiyun
mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev * dev,struct mlx4_en_stats_bitmap * stats_bitmap,u8 rx_ppp,u8 rx_pause,u8 tx_ppp,u8 tx_pause)3066*4882a593Smuzhiyun void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
3067*4882a593Smuzhiyun struct mlx4_en_stats_bitmap *stats_bitmap,
3068*4882a593Smuzhiyun u8 rx_ppp, u8 rx_pause,
3069*4882a593Smuzhiyun u8 tx_ppp, u8 tx_pause)
3070*4882a593Smuzhiyun {
3071*4882a593Smuzhiyun int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS;
3072*4882a593Smuzhiyun
3073*4882a593Smuzhiyun if (!mlx4_is_slave(dev) &&
3074*4882a593Smuzhiyun (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
3075*4882a593Smuzhiyun mutex_lock(&stats_bitmap->mutex);
3076*4882a593Smuzhiyun bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
3077*4882a593Smuzhiyun
3078*4882a593Smuzhiyun if (rx_ppp)
3079*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i,
3080*4882a593Smuzhiyun NUM_FLOW_PRIORITY_STATS_RX);
3081*4882a593Smuzhiyun last_i += NUM_FLOW_PRIORITY_STATS_RX;
3082*4882a593Smuzhiyun
3083*4882a593Smuzhiyun if (rx_pause && !(rx_ppp))
3084*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i,
3085*4882a593Smuzhiyun NUM_FLOW_STATS_RX);
3086*4882a593Smuzhiyun last_i += NUM_FLOW_STATS_RX;
3087*4882a593Smuzhiyun
3088*4882a593Smuzhiyun if (tx_ppp)
3089*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i,
3090*4882a593Smuzhiyun NUM_FLOW_PRIORITY_STATS_TX);
3091*4882a593Smuzhiyun last_i += NUM_FLOW_PRIORITY_STATS_TX;
3092*4882a593Smuzhiyun
3093*4882a593Smuzhiyun if (tx_pause && !(tx_ppp))
3094*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i,
3095*4882a593Smuzhiyun NUM_FLOW_STATS_TX);
3096*4882a593Smuzhiyun last_i += NUM_FLOW_STATS_TX;
3097*4882a593Smuzhiyun
3098*4882a593Smuzhiyun mutex_unlock(&stats_bitmap->mutex);
3099*4882a593Smuzhiyun }
3100*4882a593Smuzhiyun }
3101*4882a593Smuzhiyun
mlx4_en_set_stats_bitmap(struct mlx4_dev * dev,struct mlx4_en_stats_bitmap * stats_bitmap,u8 rx_ppp,u8 rx_pause,u8 tx_ppp,u8 tx_pause)3102*4882a593Smuzhiyun void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
3103*4882a593Smuzhiyun struct mlx4_en_stats_bitmap *stats_bitmap,
3104*4882a593Smuzhiyun u8 rx_ppp, u8 rx_pause,
3105*4882a593Smuzhiyun u8 tx_ppp, u8 tx_pause)
3106*4882a593Smuzhiyun {
3107*4882a593Smuzhiyun int last_i = 0;
3108*4882a593Smuzhiyun
3109*4882a593Smuzhiyun mutex_init(&stats_bitmap->mutex);
3110*4882a593Smuzhiyun bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
3111*4882a593Smuzhiyun
3112*4882a593Smuzhiyun if (mlx4_is_slave(dev)) {
3113*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i +
3114*4882a593Smuzhiyun MLX4_FIND_NETDEV_STAT(rx_packets), 1);
3115*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i +
3116*4882a593Smuzhiyun MLX4_FIND_NETDEV_STAT(tx_packets), 1);
3117*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i +
3118*4882a593Smuzhiyun MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
3119*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i +
3120*4882a593Smuzhiyun MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
3121*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i +
3122*4882a593Smuzhiyun MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
3123*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i +
3124*4882a593Smuzhiyun MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
3125*4882a593Smuzhiyun } else {
3126*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
3127*4882a593Smuzhiyun }
3128*4882a593Smuzhiyun last_i += NUM_MAIN_STATS;
3129*4882a593Smuzhiyun
3130*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
3131*4882a593Smuzhiyun last_i += NUM_PORT_STATS;
3132*4882a593Smuzhiyun
3133*4882a593Smuzhiyun if (mlx4_is_master(dev))
3134*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i,
3135*4882a593Smuzhiyun NUM_PF_STATS);
3136*4882a593Smuzhiyun last_i += NUM_PF_STATS;
3137*4882a593Smuzhiyun
3138*4882a593Smuzhiyun mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
3139*4882a593Smuzhiyun rx_ppp, rx_pause,
3140*4882a593Smuzhiyun tx_ppp, tx_pause);
3141*4882a593Smuzhiyun last_i += NUM_FLOW_STATS;
3142*4882a593Smuzhiyun
3143*4882a593Smuzhiyun if (!mlx4_is_slave(dev))
3144*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
3145*4882a593Smuzhiyun last_i += NUM_PKT_STATS;
3146*4882a593Smuzhiyun
3147*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i, NUM_XDP_STATS);
3148*4882a593Smuzhiyun last_i += NUM_XDP_STATS;
3149*4882a593Smuzhiyun
3150*4882a593Smuzhiyun if (!mlx4_is_slave(dev))
3151*4882a593Smuzhiyun bitmap_set(stats_bitmap->bitmap, last_i, NUM_PHY_STATS);
3152*4882a593Smuzhiyun last_i += NUM_PHY_STATS;
3153*4882a593Smuzhiyun }
3154*4882a593Smuzhiyun
mlx4_en_init_netdev(struct mlx4_en_dev * mdev,int port,struct mlx4_en_port_profile * prof)3155*4882a593Smuzhiyun int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
3156*4882a593Smuzhiyun struct mlx4_en_port_profile *prof)
3157*4882a593Smuzhiyun {
3158*4882a593Smuzhiyun struct net_device *dev;
3159*4882a593Smuzhiyun struct mlx4_en_priv *priv;
3160*4882a593Smuzhiyun int i, t;
3161*4882a593Smuzhiyun int err;
3162*4882a593Smuzhiyun
3163*4882a593Smuzhiyun dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
3164*4882a593Smuzhiyun MAX_TX_RINGS, MAX_RX_RINGS);
3165*4882a593Smuzhiyun if (dev == NULL)
3166*4882a593Smuzhiyun return -ENOMEM;
3167*4882a593Smuzhiyun
3168*4882a593Smuzhiyun netif_set_real_num_tx_queues(dev, prof->tx_ring_num[TX]);
3169*4882a593Smuzhiyun netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
3170*4882a593Smuzhiyun
3171*4882a593Smuzhiyun SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
3172*4882a593Smuzhiyun dev->dev_port = port - 1;
3173*4882a593Smuzhiyun
3174*4882a593Smuzhiyun /*
3175*4882a593Smuzhiyun * Initialize driver private data
3176*4882a593Smuzhiyun */
3177*4882a593Smuzhiyun
3178*4882a593Smuzhiyun priv = netdev_priv(dev);
3179*4882a593Smuzhiyun memset(priv, 0, sizeof(struct mlx4_en_priv));
3180*4882a593Smuzhiyun priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
3181*4882a593Smuzhiyun spin_lock_init(&priv->stats_lock);
3182*4882a593Smuzhiyun INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
3183*4882a593Smuzhiyun INIT_WORK(&priv->restart_task, mlx4_en_restart);
3184*4882a593Smuzhiyun INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
3185*4882a593Smuzhiyun INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
3186*4882a593Smuzhiyun INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
3187*4882a593Smuzhiyun #ifdef CONFIG_RFS_ACCEL
3188*4882a593Smuzhiyun INIT_LIST_HEAD(&priv->filters);
3189*4882a593Smuzhiyun spin_lock_init(&priv->filters_lock);
3190*4882a593Smuzhiyun #endif
3191*4882a593Smuzhiyun
3192*4882a593Smuzhiyun priv->dev = dev;
3193*4882a593Smuzhiyun priv->mdev = mdev;
3194*4882a593Smuzhiyun priv->ddev = &mdev->pdev->dev;
3195*4882a593Smuzhiyun priv->prof = prof;
3196*4882a593Smuzhiyun priv->port = port;
3197*4882a593Smuzhiyun priv->port_up = false;
3198*4882a593Smuzhiyun priv->flags = prof->flags;
3199*4882a593Smuzhiyun priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
3200*4882a593Smuzhiyun priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
3201*4882a593Smuzhiyun MLX4_WQE_CTRL_SOLICITED);
3202*4882a593Smuzhiyun priv->num_tx_rings_p_up = mdev->profile.max_num_tx_rings_p_up;
3203*4882a593Smuzhiyun priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
3204*4882a593Smuzhiyun netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
3205*4882a593Smuzhiyun
3206*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
3207*4882a593Smuzhiyun priv->tx_ring_num[t] = prof->tx_ring_num[t];
3208*4882a593Smuzhiyun if (!priv->tx_ring_num[t])
3209*4882a593Smuzhiyun continue;
3210*4882a593Smuzhiyun
3211*4882a593Smuzhiyun priv->tx_ring[t] = kcalloc(MAX_TX_RINGS,
3212*4882a593Smuzhiyun sizeof(struct mlx4_en_tx_ring *),
3213*4882a593Smuzhiyun GFP_KERNEL);
3214*4882a593Smuzhiyun if (!priv->tx_ring[t]) {
3215*4882a593Smuzhiyun err = -ENOMEM;
3216*4882a593Smuzhiyun goto out;
3217*4882a593Smuzhiyun }
3218*4882a593Smuzhiyun priv->tx_cq[t] = kcalloc(MAX_TX_RINGS,
3219*4882a593Smuzhiyun sizeof(struct mlx4_en_cq *),
3220*4882a593Smuzhiyun GFP_KERNEL);
3221*4882a593Smuzhiyun if (!priv->tx_cq[t]) {
3222*4882a593Smuzhiyun err = -ENOMEM;
3223*4882a593Smuzhiyun goto out;
3224*4882a593Smuzhiyun }
3225*4882a593Smuzhiyun }
3226*4882a593Smuzhiyun priv->rx_ring_num = prof->rx_ring_num;
3227*4882a593Smuzhiyun priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
3228*4882a593Smuzhiyun priv->cqe_size = mdev->dev->caps.cqe_size;
3229*4882a593Smuzhiyun priv->mac_index = -1;
3230*4882a593Smuzhiyun priv->msg_enable = MLX4_EN_MSG_LEVEL;
3231*4882a593Smuzhiyun #ifdef CONFIG_MLX4_EN_DCB
3232*4882a593Smuzhiyun if (!mlx4_is_slave(priv->mdev->dev)) {
3233*4882a593Smuzhiyun u8 prio;
3234*4882a593Smuzhiyun
3235*4882a593Smuzhiyun for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; ++prio) {
3236*4882a593Smuzhiyun priv->ets.prio_tc[prio] = prio;
3237*4882a593Smuzhiyun priv->ets.tc_tsa[prio] = IEEE_8021QAZ_TSA_VENDOR;
3238*4882a593Smuzhiyun }
3239*4882a593Smuzhiyun
3240*4882a593Smuzhiyun priv->dcbx_cap = DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_HOST |
3241*4882a593Smuzhiyun DCB_CAP_DCBX_VER_IEEE;
3242*4882a593Smuzhiyun priv->flags |= MLX4_EN_DCB_ENABLED;
3243*4882a593Smuzhiyun priv->cee_config.pfc_state = false;
3244*4882a593Smuzhiyun
3245*4882a593Smuzhiyun for (i = 0; i < MLX4_EN_NUM_UP_HIGH; i++)
3246*4882a593Smuzhiyun priv->cee_config.dcb_pfc[i] = pfc_disabled;
3247*4882a593Smuzhiyun
3248*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
3249*4882a593Smuzhiyun dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
3250*4882a593Smuzhiyun } else {
3251*4882a593Smuzhiyun en_info(priv, "enabling only PFC DCB ops\n");
3252*4882a593Smuzhiyun dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
3253*4882a593Smuzhiyun }
3254*4882a593Smuzhiyun }
3255*4882a593Smuzhiyun #endif
3256*4882a593Smuzhiyun
3257*4882a593Smuzhiyun for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
3258*4882a593Smuzhiyun INIT_HLIST_HEAD(&priv->mac_hash[i]);
3259*4882a593Smuzhiyun
3260*4882a593Smuzhiyun /* Query for default mac and max mtu */
3261*4882a593Smuzhiyun priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
3262*4882a593Smuzhiyun
3263*4882a593Smuzhiyun if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
3264*4882a593Smuzhiyun MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
3265*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
3266*4882a593Smuzhiyun
3267*4882a593Smuzhiyun /* Set default MAC */
3268*4882a593Smuzhiyun dev->addr_len = ETH_ALEN;
3269*4882a593Smuzhiyun mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
3270*4882a593Smuzhiyun if (!is_valid_ether_addr(dev->dev_addr)) {
3271*4882a593Smuzhiyun en_err(priv, "Port: %d, invalid mac burned: %pM, quitting\n",
3272*4882a593Smuzhiyun priv->port, dev->dev_addr);
3273*4882a593Smuzhiyun err = -EINVAL;
3274*4882a593Smuzhiyun goto out;
3275*4882a593Smuzhiyun } else if (mlx4_is_slave(priv->mdev->dev) &&
3276*4882a593Smuzhiyun (priv->mdev->dev->port_random_macs & 1 << priv->port)) {
3277*4882a593Smuzhiyun /* Random MAC was assigned in mlx4_slave_cap
3278*4882a593Smuzhiyun * in mlx4_core module
3279*4882a593Smuzhiyun */
3280*4882a593Smuzhiyun dev->addr_assign_type |= NET_ADDR_RANDOM;
3281*4882a593Smuzhiyun en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
3282*4882a593Smuzhiyun }
3283*4882a593Smuzhiyun
3284*4882a593Smuzhiyun memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
3285*4882a593Smuzhiyun
3286*4882a593Smuzhiyun priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
3287*4882a593Smuzhiyun DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
3288*4882a593Smuzhiyun err = mlx4_en_alloc_resources(priv);
3289*4882a593Smuzhiyun if (err)
3290*4882a593Smuzhiyun goto out;
3291*4882a593Smuzhiyun
3292*4882a593Smuzhiyun /* Initialize time stamping config */
3293*4882a593Smuzhiyun priv->hwtstamp_config.flags = 0;
3294*4882a593Smuzhiyun priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
3295*4882a593Smuzhiyun priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
3296*4882a593Smuzhiyun
3297*4882a593Smuzhiyun /* Allocate page for receive rings */
3298*4882a593Smuzhiyun err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
3299*4882a593Smuzhiyun MLX4_EN_PAGE_SIZE);
3300*4882a593Smuzhiyun if (err) {
3301*4882a593Smuzhiyun en_err(priv, "Failed to allocate page for rx qps\n");
3302*4882a593Smuzhiyun goto out;
3303*4882a593Smuzhiyun }
3304*4882a593Smuzhiyun priv->allocated = 1;
3305*4882a593Smuzhiyun
3306*4882a593Smuzhiyun /*
3307*4882a593Smuzhiyun * Initialize netdev entry points
3308*4882a593Smuzhiyun */
3309*4882a593Smuzhiyun if (mlx4_is_master(priv->mdev->dev))
3310*4882a593Smuzhiyun dev->netdev_ops = &mlx4_netdev_ops_master;
3311*4882a593Smuzhiyun else
3312*4882a593Smuzhiyun dev->netdev_ops = &mlx4_netdev_ops;
3313*4882a593Smuzhiyun dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
3314*4882a593Smuzhiyun netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
3315*4882a593Smuzhiyun netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3316*4882a593Smuzhiyun
3317*4882a593Smuzhiyun dev->ethtool_ops = &mlx4_en_ethtool_ops;
3318*4882a593Smuzhiyun
3319*4882a593Smuzhiyun /*
3320*4882a593Smuzhiyun * Set driver features
3321*4882a593Smuzhiyun */
3322*4882a593Smuzhiyun dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3323*4882a593Smuzhiyun if (mdev->LSO_support)
3324*4882a593Smuzhiyun dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
3325*4882a593Smuzhiyun
3326*4882a593Smuzhiyun if (mdev->dev->caps.tunnel_offload_mode ==
3327*4882a593Smuzhiyun MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
3328*4882a593Smuzhiyun dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3329*4882a593Smuzhiyun NETIF_F_GSO_UDP_TUNNEL_CSUM |
3330*4882a593Smuzhiyun NETIF_F_GSO_PARTIAL;
3331*4882a593Smuzhiyun dev->features |= NETIF_F_GSO_UDP_TUNNEL |
3332*4882a593Smuzhiyun NETIF_F_GSO_UDP_TUNNEL_CSUM |
3333*4882a593Smuzhiyun NETIF_F_GSO_PARTIAL;
3334*4882a593Smuzhiyun dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3335*4882a593Smuzhiyun dev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3336*4882a593Smuzhiyun NETIF_F_RXCSUM |
3337*4882a593Smuzhiyun NETIF_F_TSO | NETIF_F_TSO6 |
3338*4882a593Smuzhiyun NETIF_F_GSO_UDP_TUNNEL |
3339*4882a593Smuzhiyun NETIF_F_GSO_UDP_TUNNEL_CSUM |
3340*4882a593Smuzhiyun NETIF_F_GSO_PARTIAL;
3341*4882a593Smuzhiyun
3342*4882a593Smuzhiyun dev->udp_tunnel_nic_info = &mlx4_udp_tunnels;
3343*4882a593Smuzhiyun }
3344*4882a593Smuzhiyun
3345*4882a593Smuzhiyun dev->vlan_features = dev->hw_features;
3346*4882a593Smuzhiyun
3347*4882a593Smuzhiyun dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
3348*4882a593Smuzhiyun dev->features = dev->hw_features | NETIF_F_HIGHDMA |
3349*4882a593Smuzhiyun NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3350*4882a593Smuzhiyun NETIF_F_HW_VLAN_CTAG_FILTER;
3351*4882a593Smuzhiyun dev->hw_features |= NETIF_F_LOOPBACK |
3352*4882a593Smuzhiyun NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3353*4882a593Smuzhiyun
3354*4882a593Smuzhiyun if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
3355*4882a593Smuzhiyun dev->features |= NETIF_F_HW_VLAN_STAG_RX |
3356*4882a593Smuzhiyun NETIF_F_HW_VLAN_STAG_FILTER;
3357*4882a593Smuzhiyun dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX;
3358*4882a593Smuzhiyun }
3359*4882a593Smuzhiyun
3360*4882a593Smuzhiyun if (mlx4_is_slave(mdev->dev)) {
3361*4882a593Smuzhiyun bool vlan_offload_disabled;
3362*4882a593Smuzhiyun int phv;
3363*4882a593Smuzhiyun
3364*4882a593Smuzhiyun err = get_phv_bit(mdev->dev, port, &phv);
3365*4882a593Smuzhiyun if (!err && phv) {
3366*4882a593Smuzhiyun dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
3367*4882a593Smuzhiyun priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
3368*4882a593Smuzhiyun }
3369*4882a593Smuzhiyun err = mlx4_get_is_vlan_offload_disabled(mdev->dev, port,
3370*4882a593Smuzhiyun &vlan_offload_disabled);
3371*4882a593Smuzhiyun if (!err && vlan_offload_disabled) {
3372*4882a593Smuzhiyun dev->hw_features &= ~(NETIF_F_HW_VLAN_CTAG_TX |
3373*4882a593Smuzhiyun NETIF_F_HW_VLAN_CTAG_RX |
3374*4882a593Smuzhiyun NETIF_F_HW_VLAN_STAG_TX |
3375*4882a593Smuzhiyun NETIF_F_HW_VLAN_STAG_RX);
3376*4882a593Smuzhiyun dev->features &= ~(NETIF_F_HW_VLAN_CTAG_TX |
3377*4882a593Smuzhiyun NETIF_F_HW_VLAN_CTAG_RX |
3378*4882a593Smuzhiyun NETIF_F_HW_VLAN_STAG_TX |
3379*4882a593Smuzhiyun NETIF_F_HW_VLAN_STAG_RX);
3380*4882a593Smuzhiyun }
3381*4882a593Smuzhiyun } else {
3382*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
3383*4882a593Smuzhiyun !(mdev->dev->caps.flags2 &
3384*4882a593Smuzhiyun MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
3385*4882a593Smuzhiyun dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
3386*4882a593Smuzhiyun }
3387*4882a593Smuzhiyun
3388*4882a593Smuzhiyun if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
3389*4882a593Smuzhiyun dev->hw_features |= NETIF_F_RXFCS;
3390*4882a593Smuzhiyun
3391*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)
3392*4882a593Smuzhiyun dev->hw_features |= NETIF_F_RXALL;
3393*4882a593Smuzhiyun
3394*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode ==
3395*4882a593Smuzhiyun MLX4_STEERING_MODE_DEVICE_MANAGED &&
3396*4882a593Smuzhiyun mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
3397*4882a593Smuzhiyun dev->hw_features |= NETIF_F_NTUPLE;
3398*4882a593Smuzhiyun
3399*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
3400*4882a593Smuzhiyun dev->priv_flags |= IFF_UNICAST_FLT;
3401*4882a593Smuzhiyun
3402*4882a593Smuzhiyun /* Setting a default hash function value */
3403*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
3404*4882a593Smuzhiyun priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3405*4882a593Smuzhiyun } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
3406*4882a593Smuzhiyun priv->rss_hash_fn = ETH_RSS_HASH_XOR;
3407*4882a593Smuzhiyun } else {
3408*4882a593Smuzhiyun en_warn(priv,
3409*4882a593Smuzhiyun "No RSS hash capabilities exposed, using Toeplitz\n");
3410*4882a593Smuzhiyun priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3411*4882a593Smuzhiyun }
3412*4882a593Smuzhiyun
3413*4882a593Smuzhiyun /* MTU range: 68 - hw-specific max */
3414*4882a593Smuzhiyun dev->min_mtu = ETH_MIN_MTU;
3415*4882a593Smuzhiyun dev->max_mtu = priv->max_mtu;
3416*4882a593Smuzhiyun
3417*4882a593Smuzhiyun mdev->pndev[port] = dev;
3418*4882a593Smuzhiyun mdev->upper[port] = NULL;
3419*4882a593Smuzhiyun
3420*4882a593Smuzhiyun netif_carrier_off(dev);
3421*4882a593Smuzhiyun mlx4_en_set_default_moderation(priv);
3422*4882a593Smuzhiyun
3423*4882a593Smuzhiyun en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num[TX]);
3424*4882a593Smuzhiyun en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
3425*4882a593Smuzhiyun
3426*4882a593Smuzhiyun mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
3427*4882a593Smuzhiyun
3428*4882a593Smuzhiyun /* Configure port */
3429*4882a593Smuzhiyun mlx4_en_calc_rx_buf(dev);
3430*4882a593Smuzhiyun err = mlx4_SET_PORT_general(mdev->dev, priv->port,
3431*4882a593Smuzhiyun priv->rx_skb_size + ETH_FCS_LEN,
3432*4882a593Smuzhiyun prof->tx_pause, prof->tx_ppp,
3433*4882a593Smuzhiyun prof->rx_pause, prof->rx_ppp);
3434*4882a593Smuzhiyun if (err) {
3435*4882a593Smuzhiyun en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
3436*4882a593Smuzhiyun priv->port, err);
3437*4882a593Smuzhiyun goto out;
3438*4882a593Smuzhiyun }
3439*4882a593Smuzhiyun
3440*4882a593Smuzhiyun if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
3441*4882a593Smuzhiyun err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
3442*4882a593Smuzhiyun if (err) {
3443*4882a593Smuzhiyun en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
3444*4882a593Smuzhiyun err);
3445*4882a593Smuzhiyun goto out;
3446*4882a593Smuzhiyun }
3447*4882a593Smuzhiyun }
3448*4882a593Smuzhiyun
3449*4882a593Smuzhiyun /* Init port */
3450*4882a593Smuzhiyun en_warn(priv, "Initializing port\n");
3451*4882a593Smuzhiyun err = mlx4_INIT_PORT(mdev->dev, priv->port);
3452*4882a593Smuzhiyun if (err) {
3453*4882a593Smuzhiyun en_err(priv, "Failed Initializing port\n");
3454*4882a593Smuzhiyun goto out;
3455*4882a593Smuzhiyun }
3456*4882a593Smuzhiyun queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
3457*4882a593Smuzhiyun
3458*4882a593Smuzhiyun /* Initialize time stamp mechanism */
3459*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
3460*4882a593Smuzhiyun mlx4_en_init_timestamp(mdev);
3461*4882a593Smuzhiyun
3462*4882a593Smuzhiyun queue_delayed_work(mdev->workqueue, &priv->service_task,
3463*4882a593Smuzhiyun SERVICE_TASK_DELAY);
3464*4882a593Smuzhiyun
3465*4882a593Smuzhiyun mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
3466*4882a593Smuzhiyun mdev->profile.prof[priv->port].rx_ppp,
3467*4882a593Smuzhiyun mdev->profile.prof[priv->port].rx_pause,
3468*4882a593Smuzhiyun mdev->profile.prof[priv->port].tx_ppp,
3469*4882a593Smuzhiyun mdev->profile.prof[priv->port].tx_pause);
3470*4882a593Smuzhiyun
3471*4882a593Smuzhiyun err = register_netdev(dev);
3472*4882a593Smuzhiyun if (err) {
3473*4882a593Smuzhiyun en_err(priv, "Netdev registration failed for port %d\n", port);
3474*4882a593Smuzhiyun goto out;
3475*4882a593Smuzhiyun }
3476*4882a593Smuzhiyun
3477*4882a593Smuzhiyun priv->registered = 1;
3478*4882a593Smuzhiyun devlink_port_type_eth_set(mlx4_get_devlink_port(mdev->dev, priv->port),
3479*4882a593Smuzhiyun dev);
3480*4882a593Smuzhiyun
3481*4882a593Smuzhiyun return 0;
3482*4882a593Smuzhiyun
3483*4882a593Smuzhiyun out:
3484*4882a593Smuzhiyun mlx4_en_destroy_netdev(dev);
3485*4882a593Smuzhiyun return err;
3486*4882a593Smuzhiyun }
3487*4882a593Smuzhiyun
mlx4_en_reset_config(struct net_device * dev,struct hwtstamp_config ts_config,netdev_features_t features)3488*4882a593Smuzhiyun int mlx4_en_reset_config(struct net_device *dev,
3489*4882a593Smuzhiyun struct hwtstamp_config ts_config,
3490*4882a593Smuzhiyun netdev_features_t features)
3491*4882a593Smuzhiyun {
3492*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
3493*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
3494*4882a593Smuzhiyun struct mlx4_en_port_profile new_prof;
3495*4882a593Smuzhiyun struct mlx4_en_priv *tmp;
3496*4882a593Smuzhiyun int port_up = 0;
3497*4882a593Smuzhiyun int err = 0;
3498*4882a593Smuzhiyun
3499*4882a593Smuzhiyun if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
3500*4882a593Smuzhiyun priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
3501*4882a593Smuzhiyun !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3502*4882a593Smuzhiyun !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS))
3503*4882a593Smuzhiyun return 0; /* Nothing to change */
3504*4882a593Smuzhiyun
3505*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3506*4882a593Smuzhiyun (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3507*4882a593Smuzhiyun (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3508*4882a593Smuzhiyun en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3509*4882a593Smuzhiyun return -EINVAL;
3510*4882a593Smuzhiyun }
3511*4882a593Smuzhiyun
3512*4882a593Smuzhiyun tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
3513*4882a593Smuzhiyun if (!tmp)
3514*4882a593Smuzhiyun return -ENOMEM;
3515*4882a593Smuzhiyun
3516*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
3517*4882a593Smuzhiyun
3518*4882a593Smuzhiyun memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
3519*4882a593Smuzhiyun memcpy(&new_prof.hwtstamp_config, &ts_config, sizeof(ts_config));
3520*4882a593Smuzhiyun
3521*4882a593Smuzhiyun err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
3522*4882a593Smuzhiyun if (err)
3523*4882a593Smuzhiyun goto out;
3524*4882a593Smuzhiyun
3525*4882a593Smuzhiyun if (priv->port_up) {
3526*4882a593Smuzhiyun port_up = 1;
3527*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
3528*4882a593Smuzhiyun }
3529*4882a593Smuzhiyun
3530*4882a593Smuzhiyun mlx4_en_safe_replace_resources(priv, tmp);
3531*4882a593Smuzhiyun
3532*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3533*4882a593Smuzhiyun if (features & NETIF_F_HW_VLAN_CTAG_RX)
3534*4882a593Smuzhiyun dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3535*4882a593Smuzhiyun else
3536*4882a593Smuzhiyun dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3537*4882a593Smuzhiyun } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3538*4882a593Smuzhiyun /* RX time-stamping is OFF, update the RX vlan offload
3539*4882a593Smuzhiyun * to the latest wanted state
3540*4882a593Smuzhiyun */
3541*4882a593Smuzhiyun if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3542*4882a593Smuzhiyun dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3543*4882a593Smuzhiyun else
3544*4882a593Smuzhiyun dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3545*4882a593Smuzhiyun }
3546*4882a593Smuzhiyun
3547*4882a593Smuzhiyun if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) {
3548*4882a593Smuzhiyun if (features & NETIF_F_RXFCS)
3549*4882a593Smuzhiyun dev->features |= NETIF_F_RXFCS;
3550*4882a593Smuzhiyun else
3551*4882a593Smuzhiyun dev->features &= ~NETIF_F_RXFCS;
3552*4882a593Smuzhiyun }
3553*4882a593Smuzhiyun
3554*4882a593Smuzhiyun /* RX vlan offload and RX time-stamping can't co-exist !
3555*4882a593Smuzhiyun * Regardless of the caller's choice,
3556*4882a593Smuzhiyun * Turn Off RX vlan offload in case of time-stamping is ON
3557*4882a593Smuzhiyun */
3558*4882a593Smuzhiyun if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3559*4882a593Smuzhiyun if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3560*4882a593Smuzhiyun en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3561*4882a593Smuzhiyun dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3562*4882a593Smuzhiyun }
3563*4882a593Smuzhiyun
3564*4882a593Smuzhiyun if (port_up) {
3565*4882a593Smuzhiyun err = mlx4_en_start_port(dev);
3566*4882a593Smuzhiyun if (err)
3567*4882a593Smuzhiyun en_err(priv, "Failed starting port\n");
3568*4882a593Smuzhiyun }
3569*4882a593Smuzhiyun
3570*4882a593Smuzhiyun if (!err)
3571*4882a593Smuzhiyun err = mlx4_en_moderation_update(priv);
3572*4882a593Smuzhiyun out:
3573*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
3574*4882a593Smuzhiyun kfree(tmp);
3575*4882a593Smuzhiyun if (!err)
3576*4882a593Smuzhiyun netdev_features_change(dev);
3577*4882a593Smuzhiyun return err;
3578*4882a593Smuzhiyun }
3579