1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <linux/cpumask.h>
35*4882a593Smuzhiyun #include <linux/module.h>
36*4882a593Smuzhiyun #include <linux/delay.h>
37*4882a593Smuzhiyun #include <linux/netdevice.h>
38*4882a593Smuzhiyun #include <linux/slab.h>
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #include <linux/mlx4/driver.h>
41*4882a593Smuzhiyun #include <linux/mlx4/device.h>
42*4882a593Smuzhiyun #include <linux/mlx4/cmd.h>
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #include "mlx4_en.h"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun MODULE_AUTHOR("Liran Liss, Yevgeny Petrilin");
47*4882a593Smuzhiyun MODULE_DESCRIPTION("Mellanox ConnectX HCA Ethernet driver");
48*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
49*4882a593Smuzhiyun MODULE_VERSION(DRV_VERSION);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static const char mlx4_en_version[] =
52*4882a593Smuzhiyun DRV_NAME ": Mellanox ConnectX HCA Ethernet driver v"
53*4882a593Smuzhiyun DRV_VERSION "\n";
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define MLX4_EN_PARM_INT(X, def_val, desc) \
56*4882a593Smuzhiyun static unsigned int X = def_val;\
57*4882a593Smuzhiyun module_param(X , uint, 0444); \
58*4882a593Smuzhiyun MODULE_PARM_DESC(X, desc);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Device scope module parameters
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Enable RSS UDP traffic */
66*4882a593Smuzhiyun MLX4_EN_PARM_INT(udp_rss, 1,
67*4882a593Smuzhiyun "Enable RSS for incoming UDP traffic or disabled (0)");
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Priority pausing */
70*4882a593Smuzhiyun MLX4_EN_PARM_INT(pfctx, 0, "Priority based Flow Control policy on TX[7:0]."
71*4882a593Smuzhiyun " Per priority bit mask");
72*4882a593Smuzhiyun MLX4_EN_PARM_INT(pfcrx, 0, "Priority based Flow Control policy on RX[7:0]."
73*4882a593Smuzhiyun " Per priority bit mask");
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun MLX4_EN_PARM_INT(inline_thold, MAX_INLINE,
76*4882a593Smuzhiyun "Threshold for using inline data (range: 17-104, default: 104)");
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define MAX_PFC_TX 0xff
79*4882a593Smuzhiyun #define MAX_PFC_RX 0xff
80*4882a593Smuzhiyun
en_print(const char * level,const struct mlx4_en_priv * priv,const char * format,...)81*4882a593Smuzhiyun void en_print(const char *level, const struct mlx4_en_priv *priv,
82*4882a593Smuzhiyun const char *format, ...)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun va_list args;
85*4882a593Smuzhiyun struct va_format vaf;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun va_start(args, format);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun vaf.fmt = format;
90*4882a593Smuzhiyun vaf.va = &args;
91*4882a593Smuzhiyun if (priv->registered)
92*4882a593Smuzhiyun printk("%s%s: %s: %pV",
93*4882a593Smuzhiyun level, DRV_NAME, priv->dev->name, &vaf);
94*4882a593Smuzhiyun else
95*4882a593Smuzhiyun printk("%s%s: %s: Port %d: %pV",
96*4882a593Smuzhiyun level, DRV_NAME, dev_name(&priv->mdev->pdev->dev),
97*4882a593Smuzhiyun priv->port, &vaf);
98*4882a593Smuzhiyun va_end(args);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
mlx4_en_update_loopback_state(struct net_device * dev,netdev_features_t features)101*4882a593Smuzhiyun void mlx4_en_update_loopback_state(struct net_device *dev,
102*4882a593Smuzhiyun netdev_features_t features)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (features & NETIF_F_LOOPBACK)
107*4882a593Smuzhiyun priv->ctrl_flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
108*4882a593Smuzhiyun else
109*4882a593Smuzhiyun priv->ctrl_flags &= cpu_to_be32(~MLX4_WQE_CTRL_FORCE_LOOPBACK);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun priv->flags &= ~(MLX4_EN_FLAG_RX_FILTER_NEEDED|
112*4882a593Smuzhiyun MLX4_EN_FLAG_ENABLE_HW_LOOPBACK);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Drop the packet if SRIOV is not enabled
115*4882a593Smuzhiyun * and not performing the selftest or flb disabled
116*4882a593Smuzhiyun */
117*4882a593Smuzhiyun if (mlx4_is_mfunc(priv->mdev->dev) &&
118*4882a593Smuzhiyun !(features & NETIF_F_LOOPBACK) && !priv->validate_loopback)
119*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_RX_FILTER_NEEDED;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Set dmac in Tx WQE if we are in SRIOV mode or if loopback selftest
122*4882a593Smuzhiyun * is requested
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun if (mlx4_is_mfunc(priv->mdev->dev) || priv->validate_loopback)
125*4882a593Smuzhiyun priv->flags |= MLX4_EN_FLAG_ENABLE_HW_LOOPBACK;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun mutex_lock(&priv->mdev->state_lock);
128*4882a593Smuzhiyun if ((priv->mdev->dev->caps.flags2 &
129*4882a593Smuzhiyun MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB) &&
130*4882a593Smuzhiyun priv->rss_map.indir_qp && priv->rss_map.indir_qp->qpn) {
131*4882a593Smuzhiyun int i;
132*4882a593Smuzhiyun int err = 0;
133*4882a593Smuzhiyun int loopback = !!(features & NETIF_F_LOOPBACK);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
136*4882a593Smuzhiyun int ret;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun ret = mlx4_en_change_mcast_lb(priv,
139*4882a593Smuzhiyun &priv->rss_map.qps[i],
140*4882a593Smuzhiyun loopback);
141*4882a593Smuzhiyun if (!err)
142*4882a593Smuzhiyun err = ret;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun if (err)
145*4882a593Smuzhiyun mlx4_warn(priv->mdev, "failed to change mcast loopback\n");
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun mutex_unlock(&priv->mdev->state_lock);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
mlx4_en_get_profile(struct mlx4_en_dev * mdev)150*4882a593Smuzhiyun static void mlx4_en_get_profile(struct mlx4_en_dev *mdev)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct mlx4_en_profile *params = &mdev->profile;
153*4882a593Smuzhiyun int i;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun params->udp_rss = udp_rss;
156*4882a593Smuzhiyun params->max_num_tx_rings_p_up = mlx4_low_memory_profile() ?
157*4882a593Smuzhiyun MLX4_EN_MIN_TX_RING_P_UP :
158*4882a593Smuzhiyun min_t(int, num_online_cpus(), MLX4_EN_MAX_TX_RING_P_UP);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (params->udp_rss && !(mdev->dev->caps.flags
161*4882a593Smuzhiyun & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
162*4882a593Smuzhiyun mlx4_warn(mdev, "UDP RSS is not supported on this device\n");
163*4882a593Smuzhiyun params->udp_rss = 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun for (i = 1; i <= MLX4_MAX_PORTS; i++) {
166*4882a593Smuzhiyun params->prof[i].rx_pause = !(pfcrx || pfctx);
167*4882a593Smuzhiyun params->prof[i].rx_ppp = pfcrx;
168*4882a593Smuzhiyun params->prof[i].tx_pause = !(pfcrx || pfctx);
169*4882a593Smuzhiyun params->prof[i].tx_ppp = pfctx;
170*4882a593Smuzhiyun if (mlx4_low_memory_profile()) {
171*4882a593Smuzhiyun params->prof[i].tx_ring_size = MLX4_EN_MIN_TX_SIZE;
172*4882a593Smuzhiyun params->prof[i].rx_ring_size = MLX4_EN_MIN_RX_SIZE;
173*4882a593Smuzhiyun } else {
174*4882a593Smuzhiyun params->prof[i].tx_ring_size = MLX4_EN_DEF_TX_RING_SIZE;
175*4882a593Smuzhiyun params->prof[i].rx_ring_size = MLX4_EN_DEF_RX_RING_SIZE;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun params->prof[i].num_up = MLX4_EN_NUM_UP_LOW;
178*4882a593Smuzhiyun params->prof[i].num_tx_rings_p_up = params->max_num_tx_rings_p_up;
179*4882a593Smuzhiyun params->prof[i].tx_ring_num[TX] = params->max_num_tx_rings_p_up *
180*4882a593Smuzhiyun params->prof[i].num_up;
181*4882a593Smuzhiyun params->prof[i].rss_rings = 0;
182*4882a593Smuzhiyun params->prof[i].inline_thold = inline_thold;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
mlx4_en_get_netdev(struct mlx4_dev * dev,void * ctx,u8 port)186*4882a593Smuzhiyun static void *mlx4_en_get_netdev(struct mlx4_dev *dev, void *ctx, u8 port)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun struct mlx4_en_dev *endev = ctx;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return endev->pndev[port];
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
mlx4_en_event(struct mlx4_dev * dev,void * endev_ptr,enum mlx4_dev_event event,unsigned long port)193*4882a593Smuzhiyun static void mlx4_en_event(struct mlx4_dev *dev, void *endev_ptr,
194*4882a593Smuzhiyun enum mlx4_dev_event event, unsigned long port)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun struct mlx4_en_dev *mdev = (struct mlx4_en_dev *) endev_ptr;
197*4882a593Smuzhiyun struct mlx4_en_priv *priv;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun switch (event) {
200*4882a593Smuzhiyun case MLX4_DEV_EVENT_PORT_UP:
201*4882a593Smuzhiyun case MLX4_DEV_EVENT_PORT_DOWN:
202*4882a593Smuzhiyun if (!mdev->pndev[port])
203*4882a593Smuzhiyun return;
204*4882a593Smuzhiyun priv = netdev_priv(mdev->pndev[port]);
205*4882a593Smuzhiyun /* To prevent races, we poll the link state in a separate
206*4882a593Smuzhiyun task rather than changing it here */
207*4882a593Smuzhiyun priv->link_state = event;
208*4882a593Smuzhiyun queue_work(mdev->workqueue, &priv->linkstate_task);
209*4882a593Smuzhiyun break;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
212*4882a593Smuzhiyun mlx4_err(mdev, "Internal error detected, restarting device\n");
213*4882a593Smuzhiyun break;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun case MLX4_DEV_EVENT_SLAVE_INIT:
216*4882a593Smuzhiyun case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
217*4882a593Smuzhiyun break;
218*4882a593Smuzhiyun default:
219*4882a593Smuzhiyun if (port < 1 || port > dev->caps.num_ports ||
220*4882a593Smuzhiyun !mdev->pndev[port])
221*4882a593Smuzhiyun return;
222*4882a593Smuzhiyun mlx4_warn(mdev, "Unhandled event %d for port %d\n", event,
223*4882a593Smuzhiyun (int) port);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
mlx4_en_remove(struct mlx4_dev * dev,void * endev_ptr)227*4882a593Smuzhiyun static void mlx4_en_remove(struct mlx4_dev *dev, void *endev_ptr)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct mlx4_en_dev *mdev = endev_ptr;
230*4882a593Smuzhiyun int i;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
233*4882a593Smuzhiyun mdev->device_up = false;
234*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
237*4882a593Smuzhiyun if (mdev->pndev[i])
238*4882a593Smuzhiyun mlx4_en_destroy_netdev(mdev->pndev[i]);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun flush_workqueue(mdev->workqueue);
241*4882a593Smuzhiyun destroy_workqueue(mdev->workqueue);
242*4882a593Smuzhiyun (void) mlx4_mr_free(dev, &mdev->mr);
243*4882a593Smuzhiyun iounmap(mdev->uar_map);
244*4882a593Smuzhiyun mlx4_uar_free(dev, &mdev->priv_uar);
245*4882a593Smuzhiyun mlx4_pd_free(dev, mdev->priv_pdn);
246*4882a593Smuzhiyun if (mdev->nb.notifier_call)
247*4882a593Smuzhiyun unregister_netdevice_notifier(&mdev->nb);
248*4882a593Smuzhiyun kfree(mdev);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
mlx4_en_activate(struct mlx4_dev * dev,void * ctx)251*4882a593Smuzhiyun static void mlx4_en_activate(struct mlx4_dev *dev, void *ctx)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun int i;
254*4882a593Smuzhiyun struct mlx4_en_dev *mdev = ctx;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* Create a netdev for each port */
257*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
258*4882a593Smuzhiyun mlx4_info(mdev, "Activating port:%d\n", i);
259*4882a593Smuzhiyun if (mlx4_en_init_netdev(mdev, i, &mdev->profile.prof[i]))
260*4882a593Smuzhiyun mdev->pndev[i] = NULL;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /* register notifier */
264*4882a593Smuzhiyun mdev->nb.notifier_call = mlx4_en_netdev_event;
265*4882a593Smuzhiyun if (register_netdevice_notifier(&mdev->nb)) {
266*4882a593Smuzhiyun mdev->nb.notifier_call = NULL;
267*4882a593Smuzhiyun mlx4_err(mdev, "Failed to create notifier\n");
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
mlx4_en_add(struct mlx4_dev * dev)271*4882a593Smuzhiyun static void *mlx4_en_add(struct mlx4_dev *dev)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct mlx4_en_dev *mdev;
274*4882a593Smuzhiyun int i;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun printk_once(KERN_INFO "%s", mlx4_en_version);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
279*4882a593Smuzhiyun if (!mdev)
280*4882a593Smuzhiyun goto err_free_res;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun if (mlx4_pd_alloc(dev, &mdev->priv_pdn))
283*4882a593Smuzhiyun goto err_free_dev;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if (mlx4_uar_alloc(dev, &mdev->priv_uar))
286*4882a593Smuzhiyun goto err_pd;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun mdev->uar_map = ioremap((phys_addr_t) mdev->priv_uar.pfn << PAGE_SHIFT,
289*4882a593Smuzhiyun PAGE_SIZE);
290*4882a593Smuzhiyun if (!mdev->uar_map)
291*4882a593Smuzhiyun goto err_uar;
292*4882a593Smuzhiyun spin_lock_init(&mdev->uar_lock);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun mdev->dev = dev;
295*4882a593Smuzhiyun mdev->dma_device = &dev->persist->pdev->dev;
296*4882a593Smuzhiyun mdev->pdev = dev->persist->pdev;
297*4882a593Smuzhiyun mdev->device_up = false;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun mdev->LSO_support = !!(dev->caps.flags & (1 << 15));
300*4882a593Smuzhiyun if (!mdev->LSO_support)
301*4882a593Smuzhiyun mlx4_warn(mdev, "LSO not supported, please upgrade to later FW version to enable LSO\n");
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun if (mlx4_mr_alloc(mdev->dev, mdev->priv_pdn, 0, ~0ull,
304*4882a593Smuzhiyun MLX4_PERM_LOCAL_WRITE | MLX4_PERM_LOCAL_READ,
305*4882a593Smuzhiyun 0, 0, &mdev->mr)) {
306*4882a593Smuzhiyun mlx4_err(mdev, "Failed allocating memory region\n");
307*4882a593Smuzhiyun goto err_map;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun if (mlx4_mr_enable(mdev->dev, &mdev->mr)) {
310*4882a593Smuzhiyun mlx4_err(mdev, "Failed enabling memory region\n");
311*4882a593Smuzhiyun goto err_mr;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /* Build device profile according to supplied module parameters */
315*4882a593Smuzhiyun mlx4_en_get_profile(mdev);
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun /* Configure which ports to start according to module parameters */
318*4882a593Smuzhiyun mdev->port_cnt = 0;
319*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
320*4882a593Smuzhiyun mdev->port_cnt++;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* Set default number of RX rings*/
323*4882a593Smuzhiyun mlx4_en_set_num_rx_rings(mdev);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* Create our own workqueue for reset/multicast tasks
326*4882a593Smuzhiyun * Note: we cannot use the shared workqueue because of deadlocks caused
327*4882a593Smuzhiyun * by the rtnl lock */
328*4882a593Smuzhiyun mdev->workqueue = create_singlethread_workqueue("mlx4_en");
329*4882a593Smuzhiyun if (!mdev->workqueue)
330*4882a593Smuzhiyun goto err_mr;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun /* At this stage all non-port specific tasks are complete:
333*4882a593Smuzhiyun * mark the card state as up */
334*4882a593Smuzhiyun mutex_init(&mdev->state_lock);
335*4882a593Smuzhiyun mdev->device_up = true;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun return mdev;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun err_mr:
340*4882a593Smuzhiyun (void) mlx4_mr_free(dev, &mdev->mr);
341*4882a593Smuzhiyun err_map:
342*4882a593Smuzhiyun if (mdev->uar_map)
343*4882a593Smuzhiyun iounmap(mdev->uar_map);
344*4882a593Smuzhiyun err_uar:
345*4882a593Smuzhiyun mlx4_uar_free(dev, &mdev->priv_uar);
346*4882a593Smuzhiyun err_pd:
347*4882a593Smuzhiyun mlx4_pd_free(dev, mdev->priv_pdn);
348*4882a593Smuzhiyun err_free_dev:
349*4882a593Smuzhiyun kfree(mdev);
350*4882a593Smuzhiyun err_free_res:
351*4882a593Smuzhiyun return NULL;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun static struct mlx4_interface mlx4_en_interface = {
355*4882a593Smuzhiyun .add = mlx4_en_add,
356*4882a593Smuzhiyun .remove = mlx4_en_remove,
357*4882a593Smuzhiyun .event = mlx4_en_event,
358*4882a593Smuzhiyun .get_dev = mlx4_en_get_netdev,
359*4882a593Smuzhiyun .protocol = MLX4_PROT_ETH,
360*4882a593Smuzhiyun .activate = mlx4_en_activate,
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun
mlx4_en_verify_params(void)363*4882a593Smuzhiyun static void mlx4_en_verify_params(void)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun if (pfctx > MAX_PFC_TX) {
366*4882a593Smuzhiyun pr_warn("mlx4_en: WARNING: illegal module parameter pfctx 0x%x - should be in range 0-0x%x, will be changed to default (0)\n",
367*4882a593Smuzhiyun pfctx, MAX_PFC_TX);
368*4882a593Smuzhiyun pfctx = 0;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun if (pfcrx > MAX_PFC_RX) {
372*4882a593Smuzhiyun pr_warn("mlx4_en: WARNING: illegal module parameter pfcrx 0x%x - should be in range 0-0x%x, will be changed to default (0)\n",
373*4882a593Smuzhiyun pfcrx, MAX_PFC_RX);
374*4882a593Smuzhiyun pfcrx = 0;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun if (inline_thold < MIN_PKT_LEN || inline_thold > MAX_INLINE) {
378*4882a593Smuzhiyun pr_warn("mlx4_en: WARNING: illegal module parameter inline_thold %d - should be in range %d-%d, will be changed to default (%d)\n",
379*4882a593Smuzhiyun inline_thold, MIN_PKT_LEN, MAX_INLINE, MAX_INLINE);
380*4882a593Smuzhiyun inline_thold = MAX_INLINE;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
mlx4_en_init(void)384*4882a593Smuzhiyun static int __init mlx4_en_init(void)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun mlx4_en_verify_params();
387*4882a593Smuzhiyun mlx4_en_init_ptys2ethtool_map();
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun return mlx4_register_interface(&mlx4_en_interface);
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
mlx4_en_cleanup(void)392*4882a593Smuzhiyun static void __exit mlx4_en_cleanup(void)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun mlx4_unregister_interface(&mlx4_en_interface);
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun module_init(mlx4_en_init);
398*4882a593Smuzhiyun module_exit(mlx4_en_cleanup);
399*4882a593Smuzhiyun
400