1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <linux/kernel.h>
35*4882a593Smuzhiyun #include <linux/ethtool.h>
36*4882a593Smuzhiyun #include <linux/netdevice.h>
37*4882a593Smuzhiyun #include <linux/mlx4/driver.h>
38*4882a593Smuzhiyun #include <linux/mlx4/device.h>
39*4882a593Smuzhiyun #include <linux/in.h>
40*4882a593Smuzhiyun #include <net/ip.h>
41*4882a593Smuzhiyun #include <linux/bitmap.h>
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #include "mlx4_en.h"
44*4882a593Smuzhiyun #include "en_port.h"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define EN_ETHTOOL_QP_ATTACH (1ull << 63)
47*4882a593Smuzhiyun #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48*4882a593Smuzhiyun #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
49*4882a593Smuzhiyun
mlx4_en_moderation_update(struct mlx4_en_priv * priv)50*4882a593Smuzhiyun int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int i, t;
53*4882a593Smuzhiyun int err = 0;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
56*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++) {
57*4882a593Smuzhiyun priv->tx_cq[t][i]->moder_cnt = priv->tx_frames;
58*4882a593Smuzhiyun priv->tx_cq[t][i]->moder_time = priv->tx_usecs;
59*4882a593Smuzhiyun if (priv->port_up) {
60*4882a593Smuzhiyun err = mlx4_en_set_cq_moder(priv,
61*4882a593Smuzhiyun priv->tx_cq[t][i]);
62*4882a593Smuzhiyun if (err)
63*4882a593Smuzhiyun return err;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (priv->adaptive_rx_coal)
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
72*4882a593Smuzhiyun priv->rx_cq[i]->moder_cnt = priv->rx_frames;
73*4882a593Smuzhiyun priv->rx_cq[i]->moder_time = priv->rx_usecs;
74*4882a593Smuzhiyun priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
75*4882a593Smuzhiyun if (priv->port_up) {
76*4882a593Smuzhiyun err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
77*4882a593Smuzhiyun if (err)
78*4882a593Smuzhiyun return err;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return err;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static void
mlx4_en_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)86*4882a593Smuzhiyun mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
89*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
92*4882a593Smuzhiyun strlcpy(drvinfo->version, DRV_VERSION,
93*4882a593Smuzhiyun sizeof(drvinfo->version));
94*4882a593Smuzhiyun snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
95*4882a593Smuzhiyun "%d.%d.%d",
96*4882a593Smuzhiyun (u16) (mdev->dev->caps.fw_ver >> 32),
97*4882a593Smuzhiyun (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
98*4882a593Smuzhiyun (u16) (mdev->dev->caps.fw_ver & 0xffff));
99*4882a593Smuzhiyun strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
100*4882a593Smuzhiyun sizeof(drvinfo->bus_info));
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
104*4882a593Smuzhiyun "blueflame",
105*4882a593Smuzhiyun "phv-bit"
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const char main_strings[][ETH_GSTRING_LEN] = {
109*4882a593Smuzhiyun /* main statistics */
110*4882a593Smuzhiyun "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
111*4882a593Smuzhiyun "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
112*4882a593Smuzhiyun "rx_length_errors", "rx_over_errors", "rx_crc_errors",
113*4882a593Smuzhiyun "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
114*4882a593Smuzhiyun "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
115*4882a593Smuzhiyun "tx_heartbeat_errors", "tx_window_errors",
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* port statistics */
118*4882a593Smuzhiyun "tso_packets",
119*4882a593Smuzhiyun "xmit_more",
120*4882a593Smuzhiyun "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_pages",
121*4882a593Smuzhiyun "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* pf statistics */
124*4882a593Smuzhiyun "pf_rx_packets",
125*4882a593Smuzhiyun "pf_rx_bytes",
126*4882a593Smuzhiyun "pf_tx_packets",
127*4882a593Smuzhiyun "pf_tx_bytes",
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* priority flow control statistics rx */
130*4882a593Smuzhiyun "rx_pause_prio_0", "rx_pause_duration_prio_0",
131*4882a593Smuzhiyun "rx_pause_transition_prio_0",
132*4882a593Smuzhiyun "rx_pause_prio_1", "rx_pause_duration_prio_1",
133*4882a593Smuzhiyun "rx_pause_transition_prio_1",
134*4882a593Smuzhiyun "rx_pause_prio_2", "rx_pause_duration_prio_2",
135*4882a593Smuzhiyun "rx_pause_transition_prio_2",
136*4882a593Smuzhiyun "rx_pause_prio_3", "rx_pause_duration_prio_3",
137*4882a593Smuzhiyun "rx_pause_transition_prio_3",
138*4882a593Smuzhiyun "rx_pause_prio_4", "rx_pause_duration_prio_4",
139*4882a593Smuzhiyun "rx_pause_transition_prio_4",
140*4882a593Smuzhiyun "rx_pause_prio_5", "rx_pause_duration_prio_5",
141*4882a593Smuzhiyun "rx_pause_transition_prio_5",
142*4882a593Smuzhiyun "rx_pause_prio_6", "rx_pause_duration_prio_6",
143*4882a593Smuzhiyun "rx_pause_transition_prio_6",
144*4882a593Smuzhiyun "rx_pause_prio_7", "rx_pause_duration_prio_7",
145*4882a593Smuzhiyun "rx_pause_transition_prio_7",
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* flow control statistics rx */
148*4882a593Smuzhiyun "rx_pause", "rx_pause_duration", "rx_pause_transition",
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* priority flow control statistics tx */
151*4882a593Smuzhiyun "tx_pause_prio_0", "tx_pause_duration_prio_0",
152*4882a593Smuzhiyun "tx_pause_transition_prio_0",
153*4882a593Smuzhiyun "tx_pause_prio_1", "tx_pause_duration_prio_1",
154*4882a593Smuzhiyun "tx_pause_transition_prio_1",
155*4882a593Smuzhiyun "tx_pause_prio_2", "tx_pause_duration_prio_2",
156*4882a593Smuzhiyun "tx_pause_transition_prio_2",
157*4882a593Smuzhiyun "tx_pause_prio_3", "tx_pause_duration_prio_3",
158*4882a593Smuzhiyun "tx_pause_transition_prio_3",
159*4882a593Smuzhiyun "tx_pause_prio_4", "tx_pause_duration_prio_4",
160*4882a593Smuzhiyun "tx_pause_transition_prio_4",
161*4882a593Smuzhiyun "tx_pause_prio_5", "tx_pause_duration_prio_5",
162*4882a593Smuzhiyun "tx_pause_transition_prio_5",
163*4882a593Smuzhiyun "tx_pause_prio_6", "tx_pause_duration_prio_6",
164*4882a593Smuzhiyun "tx_pause_transition_prio_6",
165*4882a593Smuzhiyun "tx_pause_prio_7", "tx_pause_duration_prio_7",
166*4882a593Smuzhiyun "tx_pause_transition_prio_7",
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* flow control statistics tx */
169*4882a593Smuzhiyun "tx_pause", "tx_pause_duration", "tx_pause_transition",
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* packet statistics */
172*4882a593Smuzhiyun "rx_multicast_packets",
173*4882a593Smuzhiyun "rx_broadcast_packets",
174*4882a593Smuzhiyun "rx_jabbers",
175*4882a593Smuzhiyun "rx_in_range_length_error",
176*4882a593Smuzhiyun "rx_out_range_length_error",
177*4882a593Smuzhiyun "tx_multicast_packets",
178*4882a593Smuzhiyun "tx_broadcast_packets",
179*4882a593Smuzhiyun "rx_prio_0_packets", "rx_prio_0_bytes",
180*4882a593Smuzhiyun "rx_prio_1_packets", "rx_prio_1_bytes",
181*4882a593Smuzhiyun "rx_prio_2_packets", "rx_prio_2_bytes",
182*4882a593Smuzhiyun "rx_prio_3_packets", "rx_prio_3_bytes",
183*4882a593Smuzhiyun "rx_prio_4_packets", "rx_prio_4_bytes",
184*4882a593Smuzhiyun "rx_prio_5_packets", "rx_prio_5_bytes",
185*4882a593Smuzhiyun "rx_prio_6_packets", "rx_prio_6_bytes",
186*4882a593Smuzhiyun "rx_prio_7_packets", "rx_prio_7_bytes",
187*4882a593Smuzhiyun "rx_novlan_packets", "rx_novlan_bytes",
188*4882a593Smuzhiyun "tx_prio_0_packets", "tx_prio_0_bytes",
189*4882a593Smuzhiyun "tx_prio_1_packets", "tx_prio_1_bytes",
190*4882a593Smuzhiyun "tx_prio_2_packets", "tx_prio_2_bytes",
191*4882a593Smuzhiyun "tx_prio_3_packets", "tx_prio_3_bytes",
192*4882a593Smuzhiyun "tx_prio_4_packets", "tx_prio_4_bytes",
193*4882a593Smuzhiyun "tx_prio_5_packets", "tx_prio_5_bytes",
194*4882a593Smuzhiyun "tx_prio_6_packets", "tx_prio_6_bytes",
195*4882a593Smuzhiyun "tx_prio_7_packets", "tx_prio_7_bytes",
196*4882a593Smuzhiyun "tx_novlan_packets", "tx_novlan_bytes",
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* xdp statistics */
199*4882a593Smuzhiyun "rx_xdp_drop",
200*4882a593Smuzhiyun "rx_xdp_tx",
201*4882a593Smuzhiyun "rx_xdp_tx_full",
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /* phy statistics */
204*4882a593Smuzhiyun "rx_packets_phy", "rx_bytes_phy",
205*4882a593Smuzhiyun "tx_packets_phy", "tx_bytes_phy",
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
209*4882a593Smuzhiyun "Interrupt Test",
210*4882a593Smuzhiyun "Link Test",
211*4882a593Smuzhiyun "Speed Test",
212*4882a593Smuzhiyun "Register Test",
213*4882a593Smuzhiyun "Loopback Test",
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun
mlx4_en_get_msglevel(struct net_device * dev)216*4882a593Smuzhiyun static u32 mlx4_en_get_msglevel(struct net_device *dev)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
mlx4_en_set_msglevel(struct net_device * dev,u32 val)221*4882a593Smuzhiyun static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
mlx4_en_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)226*4882a593Smuzhiyun static void mlx4_en_get_wol(struct net_device *netdev,
227*4882a593Smuzhiyun struct ethtool_wolinfo *wol)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(netdev);
230*4882a593Smuzhiyun struct mlx4_caps *caps = &priv->mdev->dev->caps;
231*4882a593Smuzhiyun int err = 0;
232*4882a593Smuzhiyun u64 config = 0;
233*4882a593Smuzhiyun u64 mask;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun if ((priv->port < 1) || (priv->port > 2)) {
236*4882a593Smuzhiyun en_err(priv, "Failed to get WoL information\n");
237*4882a593Smuzhiyun return;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
241*4882a593Smuzhiyun MLX4_DEV_CAP_FLAG_WOL_PORT2;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun if (!(caps->flags & mask)) {
244*4882a593Smuzhiyun wol->supported = 0;
245*4882a593Smuzhiyun wol->wolopts = 0;
246*4882a593Smuzhiyun return;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun if (caps->wol_port[priv->port])
250*4882a593Smuzhiyun wol->supported = WAKE_MAGIC;
251*4882a593Smuzhiyun else
252*4882a593Smuzhiyun wol->supported = 0;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
255*4882a593Smuzhiyun if (err) {
256*4882a593Smuzhiyun en_err(priv, "Failed to get WoL information\n");
257*4882a593Smuzhiyun return;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun if ((config & MLX4_EN_WOL_ENABLED) && (config & MLX4_EN_WOL_MAGIC))
261*4882a593Smuzhiyun wol->wolopts = WAKE_MAGIC;
262*4882a593Smuzhiyun else
263*4882a593Smuzhiyun wol->wolopts = 0;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
mlx4_en_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)266*4882a593Smuzhiyun static int mlx4_en_set_wol(struct net_device *netdev,
267*4882a593Smuzhiyun struct ethtool_wolinfo *wol)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(netdev);
270*4882a593Smuzhiyun u64 config = 0;
271*4882a593Smuzhiyun int err = 0;
272*4882a593Smuzhiyun u64 mask;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if ((priv->port < 1) || (priv->port > 2))
275*4882a593Smuzhiyun return -EOPNOTSUPP;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
278*4882a593Smuzhiyun MLX4_DEV_CAP_FLAG_WOL_PORT2;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun if (!(priv->mdev->dev->caps.flags & mask))
281*4882a593Smuzhiyun return -EOPNOTSUPP;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun if (wol->supported & ~WAKE_MAGIC)
284*4882a593Smuzhiyun return -EINVAL;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
287*4882a593Smuzhiyun if (err) {
288*4882a593Smuzhiyun en_err(priv, "Failed to get WoL info, unable to modify\n");
289*4882a593Smuzhiyun return err;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun if (wol->wolopts & WAKE_MAGIC) {
293*4882a593Smuzhiyun config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
294*4882a593Smuzhiyun MLX4_EN_WOL_MAGIC;
295*4882a593Smuzhiyun } else {
296*4882a593Smuzhiyun config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
297*4882a593Smuzhiyun config |= MLX4_EN_WOL_DO_MODIFY;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
301*4882a593Smuzhiyun if (err)
302*4882a593Smuzhiyun en_err(priv, "Failed to set WoL information\n");
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun return err;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun struct bitmap_iterator {
308*4882a593Smuzhiyun unsigned long *stats_bitmap;
309*4882a593Smuzhiyun unsigned int count;
310*4882a593Smuzhiyun unsigned int iterator;
311*4882a593Smuzhiyun bool advance_array; /* if set, force no increments */
312*4882a593Smuzhiyun };
313*4882a593Smuzhiyun
bitmap_iterator_init(struct bitmap_iterator * h,unsigned long * stats_bitmap,int count)314*4882a593Smuzhiyun static inline void bitmap_iterator_init(struct bitmap_iterator *h,
315*4882a593Smuzhiyun unsigned long *stats_bitmap,
316*4882a593Smuzhiyun int count)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun h->iterator = 0;
319*4882a593Smuzhiyun h->advance_array = !bitmap_empty(stats_bitmap, count);
320*4882a593Smuzhiyun h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
321*4882a593Smuzhiyun : count;
322*4882a593Smuzhiyun h->stats_bitmap = stats_bitmap;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
bitmap_iterator_test(struct bitmap_iterator * h)325*4882a593Smuzhiyun static inline int bitmap_iterator_test(struct bitmap_iterator *h)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
bitmap_iterator_inc(struct bitmap_iterator * h)330*4882a593Smuzhiyun static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun return h->iterator++;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun static inline unsigned int
bitmap_iterator_count(struct bitmap_iterator * h)336*4882a593Smuzhiyun bitmap_iterator_count(struct bitmap_iterator *h)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun return h->count;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
mlx4_en_get_sset_count(struct net_device * dev,int sset)341*4882a593Smuzhiyun static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
344*4882a593Smuzhiyun struct bitmap_iterator it;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun switch (sset) {
349*4882a593Smuzhiyun case ETH_SS_STATS:
350*4882a593Smuzhiyun return bitmap_iterator_count(&it) +
351*4882a593Smuzhiyun (priv->tx_ring_num[TX] * 2) +
352*4882a593Smuzhiyun (priv->rx_ring_num * (3 + NUM_XDP_STATS));
353*4882a593Smuzhiyun case ETH_SS_TEST:
354*4882a593Smuzhiyun return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
355*4882a593Smuzhiyun & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
356*4882a593Smuzhiyun case ETH_SS_PRIV_FLAGS:
357*4882a593Smuzhiyun return ARRAY_SIZE(mlx4_en_priv_flags);
358*4882a593Smuzhiyun default:
359*4882a593Smuzhiyun return -EOPNOTSUPP;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
mlx4_en_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,uint64_t * data)363*4882a593Smuzhiyun static void mlx4_en_get_ethtool_stats(struct net_device *dev,
364*4882a593Smuzhiyun struct ethtool_stats *stats, uint64_t *data)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
367*4882a593Smuzhiyun int index = 0;
368*4882a593Smuzhiyun int i;
369*4882a593Smuzhiyun struct bitmap_iterator it;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun spin_lock_bh(&priv->stats_lock);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun mlx4_en_fold_software_stats(dev);
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
378*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
379*4882a593Smuzhiyun data[index++] = ((unsigned long *)&dev->stats)[i];
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
382*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
383*4882a593Smuzhiyun data[index++] = ((unsigned long *)&priv->port_stats)[i];
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it))
386*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
387*4882a593Smuzhiyun data[index++] =
388*4882a593Smuzhiyun ((unsigned long *)&priv->pf_stats)[i];
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
391*4882a593Smuzhiyun i++, bitmap_iterator_inc(&it))
392*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
393*4882a593Smuzhiyun data[index++] =
394*4882a593Smuzhiyun ((u64 *)&priv->rx_priority_flowstats)[i];
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
397*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
398*4882a593Smuzhiyun data[index++] = ((u64 *)&priv->rx_flowstats)[i];
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
401*4882a593Smuzhiyun i++, bitmap_iterator_inc(&it))
402*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
403*4882a593Smuzhiyun data[index++] =
404*4882a593Smuzhiyun ((u64 *)&priv->tx_priority_flowstats)[i];
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
407*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
408*4882a593Smuzhiyun data[index++] = ((u64 *)&priv->tx_flowstats)[i];
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
411*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
412*4882a593Smuzhiyun data[index++] = ((unsigned long *)&priv->pkstats)[i];
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun for (i = 0; i < NUM_XDP_STATS; i++, bitmap_iterator_inc(&it))
415*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
416*4882a593Smuzhiyun data[index++] = ((unsigned long *)&priv->xdp_stats)[i];
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun for (i = 0; i < NUM_PHY_STATS; i++, bitmap_iterator_inc(&it))
419*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
420*4882a593Smuzhiyun data[index++] = ((unsigned long *)&priv->phy_stats)[i];
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[TX]; i++) {
423*4882a593Smuzhiyun data[index++] = priv->tx_ring[TX][i]->packets;
424*4882a593Smuzhiyun data[index++] = priv->tx_ring[TX][i]->bytes;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
427*4882a593Smuzhiyun data[index++] = priv->rx_ring[i]->packets;
428*4882a593Smuzhiyun data[index++] = priv->rx_ring[i]->bytes;
429*4882a593Smuzhiyun data[index++] = priv->rx_ring[i]->dropped;
430*4882a593Smuzhiyun data[index++] = priv->rx_ring[i]->xdp_drop;
431*4882a593Smuzhiyun data[index++] = priv->rx_ring[i]->xdp_tx;
432*4882a593Smuzhiyun data[index++] = priv->rx_ring[i]->xdp_tx_full;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun spin_unlock_bh(&priv->stats_lock);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
mlx4_en_self_test(struct net_device * dev,struct ethtool_test * etest,u64 * buf)438*4882a593Smuzhiyun static void mlx4_en_self_test(struct net_device *dev,
439*4882a593Smuzhiyun struct ethtool_test *etest, u64 *buf)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun mlx4_en_ex_selftest(dev, &etest->flags, buf);
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
mlx4_en_get_strings(struct net_device * dev,uint32_t stringset,uint8_t * data)444*4882a593Smuzhiyun static void mlx4_en_get_strings(struct net_device *dev,
445*4882a593Smuzhiyun uint32_t stringset, uint8_t *data)
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
448*4882a593Smuzhiyun int index = 0;
449*4882a593Smuzhiyun int i, strings = 0;
450*4882a593Smuzhiyun struct bitmap_iterator it;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun switch (stringset) {
455*4882a593Smuzhiyun case ETH_SS_TEST:
456*4882a593Smuzhiyun for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
457*4882a593Smuzhiyun strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
458*4882a593Smuzhiyun if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
459*4882a593Smuzhiyun for (; i < MLX4_EN_NUM_SELF_TEST; i++)
460*4882a593Smuzhiyun strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
461*4882a593Smuzhiyun break;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun case ETH_SS_STATS:
464*4882a593Smuzhiyun /* Add main counters */
465*4882a593Smuzhiyun for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
466*4882a593Smuzhiyun bitmap_iterator_inc(&it))
467*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
468*4882a593Smuzhiyun strcpy(data + (index++) * ETH_GSTRING_LEN,
469*4882a593Smuzhiyun main_strings[strings]);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun for (i = 0; i < NUM_PORT_STATS; i++, strings++,
472*4882a593Smuzhiyun bitmap_iterator_inc(&it))
473*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
474*4882a593Smuzhiyun strcpy(data + (index++) * ETH_GSTRING_LEN,
475*4882a593Smuzhiyun main_strings[strings]);
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun for (i = 0; i < NUM_PF_STATS; i++, strings++,
478*4882a593Smuzhiyun bitmap_iterator_inc(&it))
479*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
480*4882a593Smuzhiyun strcpy(data + (index++) * ETH_GSTRING_LEN,
481*4882a593Smuzhiyun main_strings[strings]);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
484*4882a593Smuzhiyun bitmap_iterator_inc(&it))
485*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
486*4882a593Smuzhiyun strcpy(data + (index++) * ETH_GSTRING_LEN,
487*4882a593Smuzhiyun main_strings[strings]);
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun for (i = 0; i < NUM_PKT_STATS; i++, strings++,
490*4882a593Smuzhiyun bitmap_iterator_inc(&it))
491*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
492*4882a593Smuzhiyun strcpy(data + (index++) * ETH_GSTRING_LEN,
493*4882a593Smuzhiyun main_strings[strings]);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun for (i = 0; i < NUM_XDP_STATS; i++, strings++,
496*4882a593Smuzhiyun bitmap_iterator_inc(&it))
497*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
498*4882a593Smuzhiyun strcpy(data + (index++) * ETH_GSTRING_LEN,
499*4882a593Smuzhiyun main_strings[strings]);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun for (i = 0; i < NUM_PHY_STATS; i++, strings++,
502*4882a593Smuzhiyun bitmap_iterator_inc(&it))
503*4882a593Smuzhiyun if (bitmap_iterator_test(&it))
504*4882a593Smuzhiyun strcpy(data + (index++) * ETH_GSTRING_LEN,
505*4882a593Smuzhiyun main_strings[strings]);
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[TX]; i++) {
508*4882a593Smuzhiyun sprintf(data + (index++) * ETH_GSTRING_LEN,
509*4882a593Smuzhiyun "tx%d_packets", i);
510*4882a593Smuzhiyun sprintf(data + (index++) * ETH_GSTRING_LEN,
511*4882a593Smuzhiyun "tx%d_bytes", i);
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun for (i = 0; i < priv->rx_ring_num; i++) {
514*4882a593Smuzhiyun sprintf(data + (index++) * ETH_GSTRING_LEN,
515*4882a593Smuzhiyun "rx%d_packets", i);
516*4882a593Smuzhiyun sprintf(data + (index++) * ETH_GSTRING_LEN,
517*4882a593Smuzhiyun "rx%d_bytes", i);
518*4882a593Smuzhiyun sprintf(data + (index++) * ETH_GSTRING_LEN,
519*4882a593Smuzhiyun "rx%d_dropped", i);
520*4882a593Smuzhiyun sprintf(data + (index++) * ETH_GSTRING_LEN,
521*4882a593Smuzhiyun "rx%d_xdp_drop", i);
522*4882a593Smuzhiyun sprintf(data + (index++) * ETH_GSTRING_LEN,
523*4882a593Smuzhiyun "rx%d_xdp_tx", i);
524*4882a593Smuzhiyun sprintf(data + (index++) * ETH_GSTRING_LEN,
525*4882a593Smuzhiyun "rx%d_xdp_tx_full", i);
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun break;
528*4882a593Smuzhiyun case ETH_SS_PRIV_FLAGS:
529*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
530*4882a593Smuzhiyun strcpy(data + i * ETH_GSTRING_LEN,
531*4882a593Smuzhiyun mlx4_en_priv_flags[i]);
532*4882a593Smuzhiyun break;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun
mlx4_en_autoneg_get(struct net_device * dev)537*4882a593Smuzhiyun static u32 mlx4_en_autoneg_get(struct net_device *dev)
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
540*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
541*4882a593Smuzhiyun u32 autoneg = AUTONEG_DISABLE;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
544*4882a593Smuzhiyun (priv->port_state.flags & MLX4_EN_PORT_ANE))
545*4882a593Smuzhiyun autoneg = AUTONEG_ENABLE;
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun return autoneg;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
ptys2ethtool_update_supported_port(unsigned long * mask,struct mlx4_ptys_reg * ptys_reg)550*4882a593Smuzhiyun static void ptys2ethtool_update_supported_port(unsigned long *mask,
551*4882a593Smuzhiyun struct mlx4_ptys_reg *ptys_reg)
552*4882a593Smuzhiyun {
553*4882a593Smuzhiyun u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
556*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_1000BASE_T)
557*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
558*4882a593Smuzhiyun __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
559*4882a593Smuzhiyun } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
560*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_10GBASE_SR)
561*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
562*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
563*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
564*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
565*4882a593Smuzhiyun __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask);
566*4882a593Smuzhiyun } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
567*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
568*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
569*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_10GBASE_KR)
570*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
571*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
572*4882a593Smuzhiyun __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask);
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun
ptys_get_active_port(struct mlx4_ptys_reg * ptys_reg)576*4882a593Smuzhiyun static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun if (!eth_proto) /* link down */
581*4882a593Smuzhiyun eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
584*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_1000BASE_T)
585*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
586*4882a593Smuzhiyun return PORT_TP;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
590*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
591*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
592*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
593*4882a593Smuzhiyun return PORT_FIBRE;
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
597*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
598*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
599*4882a593Smuzhiyun return PORT_DA;
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
603*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
604*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
605*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_10GBASE_KR)
606*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
607*4882a593Smuzhiyun | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
608*4882a593Smuzhiyun return PORT_NONE;
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun return PORT_OTHER;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun #define MLX4_LINK_MODES_SZ \
614*4882a593Smuzhiyun (sizeof_field(struct mlx4_ptys_reg, eth_proto_cap) * 8)
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun enum ethtool_report {
617*4882a593Smuzhiyun SUPPORTED = 0,
618*4882a593Smuzhiyun ADVERTISED = 1,
619*4882a593Smuzhiyun };
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun struct ptys2ethtool_config {
622*4882a593Smuzhiyun __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
623*4882a593Smuzhiyun __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
624*4882a593Smuzhiyun u32 speed;
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun
ptys2ethtool_link_mode(struct ptys2ethtool_config * cfg,enum ethtool_report report)627*4882a593Smuzhiyun static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg,
628*4882a593Smuzhiyun enum ethtool_report report)
629*4882a593Smuzhiyun {
630*4882a593Smuzhiyun switch (report) {
631*4882a593Smuzhiyun case SUPPORTED:
632*4882a593Smuzhiyun return cfg->supported;
633*4882a593Smuzhiyun case ADVERTISED:
634*4882a593Smuzhiyun return cfg->advertised;
635*4882a593Smuzhiyun }
636*4882a593Smuzhiyun return NULL;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
640*4882a593Smuzhiyun ({ \
641*4882a593Smuzhiyun struct ptys2ethtool_config *cfg; \
642*4882a593Smuzhiyun static const unsigned int modes[] = { __VA_ARGS__ }; \
643*4882a593Smuzhiyun unsigned int i; \
644*4882a593Smuzhiyun cfg = &ptys2ethtool_map[reg_]; \
645*4882a593Smuzhiyun cfg->speed = speed_; \
646*4882a593Smuzhiyun bitmap_zero(cfg->supported, \
647*4882a593Smuzhiyun __ETHTOOL_LINK_MODE_MASK_NBITS); \
648*4882a593Smuzhiyun bitmap_zero(cfg->advertised, \
649*4882a593Smuzhiyun __ETHTOOL_LINK_MODE_MASK_NBITS); \
650*4882a593Smuzhiyun for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
651*4882a593Smuzhiyun __set_bit(modes[i], cfg->supported); \
652*4882a593Smuzhiyun __set_bit(modes[i], cfg->advertised); \
653*4882a593Smuzhiyun } \
654*4882a593Smuzhiyun })
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
657*4882a593Smuzhiyun static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ];
658*4882a593Smuzhiyun
mlx4_en_init_ptys2ethtool_map(void)659*4882a593Smuzhiyun void __init mlx4_en_init_ptys2ethtool_map(void)
660*4882a593Smuzhiyun {
661*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100,
662*4882a593Smuzhiyun ETHTOOL_LINK_MODE_100baseT_Full_BIT);
663*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000,
664*4882a593Smuzhiyun ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
665*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000,
666*4882a593Smuzhiyun ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
667*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000,
668*4882a593Smuzhiyun ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
669*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000,
670*4882a593Smuzhiyun ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
671*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000,
672*4882a593Smuzhiyun ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
673*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000,
674*4882a593Smuzhiyun ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
675*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000,
676*4882a593Smuzhiyun ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
677*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000,
678*4882a593Smuzhiyun ETHTOOL_LINK_MODE_10000baseCR_Full_BIT);
679*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000,
680*4882a593Smuzhiyun ETHTOOL_LINK_MODE_10000baseSR_Full_BIT);
681*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000,
682*4882a593Smuzhiyun ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT,
683*4882a593Smuzhiyun ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
684*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000,
685*4882a593Smuzhiyun ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
686*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000,
687*4882a593Smuzhiyun ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
688*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000,
689*4882a593Smuzhiyun ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
690*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000,
691*4882a593Smuzhiyun ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
692*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000,
693*4882a593Smuzhiyun ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT);
694*4882a593Smuzhiyun MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000,
695*4882a593Smuzhiyun ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT);
696*4882a593Smuzhiyun };
697*4882a593Smuzhiyun
ptys2ethtool_update_link_modes(unsigned long * link_modes,u32 eth_proto,enum ethtool_report report)698*4882a593Smuzhiyun static void ptys2ethtool_update_link_modes(unsigned long *link_modes,
699*4882a593Smuzhiyun u32 eth_proto,
700*4882a593Smuzhiyun enum ethtool_report report)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun int i;
703*4882a593Smuzhiyun for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
704*4882a593Smuzhiyun if (eth_proto & MLX4_PROT_MASK(i))
705*4882a593Smuzhiyun bitmap_or(link_modes, link_modes,
706*4882a593Smuzhiyun ptys2ethtool_link_mode(&ptys2ethtool_map[i],
707*4882a593Smuzhiyun report),
708*4882a593Smuzhiyun __ETHTOOL_LINK_MODE_MASK_NBITS);
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun
ethtool2ptys_link_modes(const unsigned long * link_modes,enum ethtool_report report)712*4882a593Smuzhiyun static u32 ethtool2ptys_link_modes(const unsigned long *link_modes,
713*4882a593Smuzhiyun enum ethtool_report report)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun int i;
716*4882a593Smuzhiyun u32 ptys_modes = 0;
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
719*4882a593Smuzhiyun if (bitmap_intersects(
720*4882a593Smuzhiyun ptys2ethtool_link_mode(&ptys2ethtool_map[i],
721*4882a593Smuzhiyun report),
722*4882a593Smuzhiyun link_modes,
723*4882a593Smuzhiyun __ETHTOOL_LINK_MODE_MASK_NBITS))
724*4882a593Smuzhiyun ptys_modes |= 1 << i;
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun return ptys_modes;
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun /* Convert actual speed (SPEED_XXX) to ptys link modes */
speed2ptys_link_modes(u32 speed)730*4882a593Smuzhiyun static u32 speed2ptys_link_modes(u32 speed)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun int i;
733*4882a593Smuzhiyun u32 ptys_modes = 0;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
736*4882a593Smuzhiyun if (ptys2ethtool_map[i].speed == speed)
737*4882a593Smuzhiyun ptys_modes |= 1 << i;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun return ptys_modes;
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun static int
ethtool_get_ptys_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * link_ksettings)743*4882a593Smuzhiyun ethtool_get_ptys_link_ksettings(struct net_device *dev,
744*4882a593Smuzhiyun struct ethtool_link_ksettings *link_ksettings)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
747*4882a593Smuzhiyun struct mlx4_ptys_reg ptys_reg;
748*4882a593Smuzhiyun u32 eth_proto;
749*4882a593Smuzhiyun int ret;
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun memset(&ptys_reg, 0, sizeof(ptys_reg));
752*4882a593Smuzhiyun ptys_reg.local_port = priv->port;
753*4882a593Smuzhiyun ptys_reg.proto_mask = MLX4_PTYS_EN;
754*4882a593Smuzhiyun ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
755*4882a593Smuzhiyun MLX4_ACCESS_REG_QUERY, &ptys_reg);
756*4882a593Smuzhiyun if (ret) {
757*4882a593Smuzhiyun en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
758*4882a593Smuzhiyun ret);
759*4882a593Smuzhiyun return ret;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
762*4882a593Smuzhiyun ptys_reg.proto_mask);
763*4882a593Smuzhiyun en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
764*4882a593Smuzhiyun be32_to_cpu(ptys_reg.eth_proto_cap));
765*4882a593Smuzhiyun en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
766*4882a593Smuzhiyun be32_to_cpu(ptys_reg.eth_proto_admin));
767*4882a593Smuzhiyun en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
768*4882a593Smuzhiyun be32_to_cpu(ptys_reg.eth_proto_oper));
769*4882a593Smuzhiyun en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
770*4882a593Smuzhiyun be32_to_cpu(ptys_reg.eth_proto_lp_adv));
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun /* reset supported/advertising masks */
773*4882a593Smuzhiyun ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
774*4882a593Smuzhiyun ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported,
777*4882a593Smuzhiyun &ptys_reg);
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
780*4882a593Smuzhiyun ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported,
781*4882a593Smuzhiyun eth_proto, SUPPORTED);
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
784*4882a593Smuzhiyun ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising,
785*4882a593Smuzhiyun eth_proto, ADVERTISED);
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
788*4882a593Smuzhiyun Pause);
789*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
790*4882a593Smuzhiyun Asym_Pause);
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun if (priv->prof->tx_pause)
793*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
794*4882a593Smuzhiyun advertising, Pause);
795*4882a593Smuzhiyun if (priv->prof->tx_pause ^ priv->prof->rx_pause)
796*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
797*4882a593Smuzhiyun advertising, Asym_Pause);
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun link_ksettings->base.port = ptys_get_active_port(&ptys_reg);
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun if (mlx4_en_autoneg_get(dev)) {
802*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
803*4882a593Smuzhiyun supported, Autoneg);
804*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
805*4882a593Smuzhiyun advertising, Autoneg);
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun link_ksettings->base.autoneg
809*4882a593Smuzhiyun = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
810*4882a593Smuzhiyun AUTONEG_ENABLE : AUTONEG_DISABLE;
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
815*4882a593Smuzhiyun ptys2ethtool_update_link_modes(
816*4882a593Smuzhiyun link_ksettings->link_modes.lp_advertising,
817*4882a593Smuzhiyun eth_proto, ADVERTISED);
818*4882a593Smuzhiyun if (priv->port_state.flags & MLX4_EN_PORT_ANC)
819*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
820*4882a593Smuzhiyun lp_advertising, Autoneg);
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun link_ksettings->base.phy_address = 0;
823*4882a593Smuzhiyun link_ksettings->base.mdio_support = 0;
824*4882a593Smuzhiyun link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
825*4882a593Smuzhiyun link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun return ret;
828*4882a593Smuzhiyun }
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun static void
ethtool_get_default_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * link_ksettings)831*4882a593Smuzhiyun ethtool_get_default_link_ksettings(
832*4882a593Smuzhiyun struct net_device *dev, struct ethtool_link_ksettings *link_ksettings)
833*4882a593Smuzhiyun {
834*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
835*4882a593Smuzhiyun int trans_type;
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun link_ksettings->base.autoneg = AUTONEG_DISABLE;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
840*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
841*4882a593Smuzhiyun 10000baseT_Full);
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
844*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings, advertising,
845*4882a593Smuzhiyun 10000baseT_Full);
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun trans_type = priv->port_state.transceiver;
848*4882a593Smuzhiyun if (trans_type > 0 && trans_type <= 0xC) {
849*4882a593Smuzhiyun link_ksettings->base.port = PORT_FIBRE;
850*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
851*4882a593Smuzhiyun supported, FIBRE);
852*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
853*4882a593Smuzhiyun advertising, FIBRE);
854*4882a593Smuzhiyun } else if (trans_type == 0x80 || trans_type == 0) {
855*4882a593Smuzhiyun link_ksettings->base.port = PORT_TP;
856*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
857*4882a593Smuzhiyun supported, TP);
858*4882a593Smuzhiyun ethtool_link_ksettings_add_link_mode(link_ksettings,
859*4882a593Smuzhiyun advertising, TP);
860*4882a593Smuzhiyun } else {
861*4882a593Smuzhiyun link_ksettings->base.port = -1;
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun }
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun static int
mlx4_en_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * link_ksettings)866*4882a593Smuzhiyun mlx4_en_get_link_ksettings(struct net_device *dev,
867*4882a593Smuzhiyun struct ethtool_link_ksettings *link_ksettings)
868*4882a593Smuzhiyun {
869*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
870*4882a593Smuzhiyun int ret = -EINVAL;
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
873*4882a593Smuzhiyun return -ENOMEM;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
876*4882a593Smuzhiyun priv->port_state.flags & MLX4_EN_PORT_ANC,
877*4882a593Smuzhiyun priv->port_state.flags & MLX4_EN_PORT_ANE);
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
880*4882a593Smuzhiyun ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings);
881*4882a593Smuzhiyun if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
882*4882a593Smuzhiyun ethtool_get_default_link_ksettings(dev, link_ksettings);
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun if (netif_carrier_ok(dev)) {
885*4882a593Smuzhiyun link_ksettings->base.speed = priv->port_state.link_speed;
886*4882a593Smuzhiyun link_ksettings->base.duplex = DUPLEX_FULL;
887*4882a593Smuzhiyun } else {
888*4882a593Smuzhiyun link_ksettings->base.speed = SPEED_UNKNOWN;
889*4882a593Smuzhiyun link_ksettings->base.duplex = DUPLEX_UNKNOWN;
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun return 0;
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
speed_set_ptys_admin(struct mlx4_en_priv * priv,u32 speed,__be32 proto_cap)895*4882a593Smuzhiyun static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
896*4882a593Smuzhiyun __be32 proto_cap)
897*4882a593Smuzhiyun {
898*4882a593Smuzhiyun __be32 proto_admin = 0;
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun if (!speed) { /* Speed = 0 ==> Reset Link modes */
901*4882a593Smuzhiyun proto_admin = proto_cap;
902*4882a593Smuzhiyun en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
903*4882a593Smuzhiyun be32_to_cpu(proto_cap));
904*4882a593Smuzhiyun } else {
905*4882a593Smuzhiyun u32 ptys_link_modes = speed2ptys_link_modes(speed);
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
908*4882a593Smuzhiyun en_info(priv, "Setting Speed to %d\n", speed);
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun return proto_admin;
911*4882a593Smuzhiyun }
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun static int
mlx4_en_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * link_ksettings)914*4882a593Smuzhiyun mlx4_en_set_link_ksettings(struct net_device *dev,
915*4882a593Smuzhiyun const struct ethtool_link_ksettings *link_ksettings)
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
918*4882a593Smuzhiyun struct mlx4_ptys_reg ptys_reg;
919*4882a593Smuzhiyun __be32 proto_admin;
920*4882a593Smuzhiyun u8 cur_autoneg;
921*4882a593Smuzhiyun int ret;
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun u32 ptys_adv = ethtool2ptys_link_modes(
924*4882a593Smuzhiyun link_ksettings->link_modes.advertising, ADVERTISED);
925*4882a593Smuzhiyun const int speed = link_ksettings->base.speed;
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun en_dbg(DRV, priv,
928*4882a593Smuzhiyun "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n",
929*4882a593Smuzhiyun speed, __ETHTOOL_LINK_MODE_MASK_NBITS,
930*4882a593Smuzhiyun link_ksettings->link_modes.advertising,
931*4882a593Smuzhiyun link_ksettings->base.autoneg,
932*4882a593Smuzhiyun link_ksettings->base.duplex);
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun if (!(priv->mdev->dev->caps.flags2 &
935*4882a593Smuzhiyun MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
936*4882a593Smuzhiyun (link_ksettings->base.duplex == DUPLEX_HALF))
937*4882a593Smuzhiyun return -EINVAL;
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun memset(&ptys_reg, 0, sizeof(ptys_reg));
940*4882a593Smuzhiyun ptys_reg.local_port = priv->port;
941*4882a593Smuzhiyun ptys_reg.proto_mask = MLX4_PTYS_EN;
942*4882a593Smuzhiyun ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
943*4882a593Smuzhiyun MLX4_ACCESS_REG_QUERY, &ptys_reg);
944*4882a593Smuzhiyun if (ret) {
945*4882a593Smuzhiyun en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
946*4882a593Smuzhiyun ret);
947*4882a593Smuzhiyun return 0;
948*4882a593Smuzhiyun }
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun cur_autoneg = ptys_reg.flags & MLX4_PTYS_AN_DISABLE_ADMIN ?
951*4882a593Smuzhiyun AUTONEG_DISABLE : AUTONEG_ENABLE;
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun if (link_ksettings->base.autoneg == AUTONEG_DISABLE) {
954*4882a593Smuzhiyun proto_admin = speed_set_ptys_admin(priv, speed,
955*4882a593Smuzhiyun ptys_reg.eth_proto_cap);
956*4882a593Smuzhiyun if ((be32_to_cpu(proto_admin) &
957*4882a593Smuzhiyun (MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII) |
958*4882a593Smuzhiyun MLX4_PROT_MASK(MLX4_1000BASE_KX))) &&
959*4882a593Smuzhiyun (ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP))
960*4882a593Smuzhiyun ptys_reg.flags |= MLX4_PTYS_AN_DISABLE_ADMIN;
961*4882a593Smuzhiyun } else {
962*4882a593Smuzhiyun proto_admin = cpu_to_be32(ptys_adv);
963*4882a593Smuzhiyun ptys_reg.flags &= ~MLX4_PTYS_AN_DISABLE_ADMIN;
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun proto_admin &= ptys_reg.eth_proto_cap;
967*4882a593Smuzhiyun if (!proto_admin) {
968*4882a593Smuzhiyun en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
969*4882a593Smuzhiyun return -EINVAL; /* nothing to change due to bad input */
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun if ((proto_admin == ptys_reg.eth_proto_admin) &&
973*4882a593Smuzhiyun ((ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP) &&
974*4882a593Smuzhiyun (link_ksettings->base.autoneg == cur_autoneg)))
975*4882a593Smuzhiyun return 0; /* Nothing to change */
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
978*4882a593Smuzhiyun be32_to_cpu(proto_admin));
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun ptys_reg.eth_proto_admin = proto_admin;
981*4882a593Smuzhiyun ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
982*4882a593Smuzhiyun &ptys_reg);
983*4882a593Smuzhiyun if (ret) {
984*4882a593Smuzhiyun en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
985*4882a593Smuzhiyun be32_to_cpu(ptys_reg.eth_proto_admin), ret);
986*4882a593Smuzhiyun return ret;
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun mutex_lock(&priv->mdev->state_lock);
990*4882a593Smuzhiyun if (priv->port_up) {
991*4882a593Smuzhiyun en_warn(priv, "Port link mode changed, restarting port...\n");
992*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
993*4882a593Smuzhiyun if (mlx4_en_start_port(dev))
994*4882a593Smuzhiyun en_err(priv, "Failed restarting port %d\n", priv->port);
995*4882a593Smuzhiyun }
996*4882a593Smuzhiyun mutex_unlock(&priv->mdev->state_lock);
997*4882a593Smuzhiyun return 0;
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun
mlx4_en_get_coalesce(struct net_device * dev,struct ethtool_coalesce * coal)1000*4882a593Smuzhiyun static int mlx4_en_get_coalesce(struct net_device *dev,
1001*4882a593Smuzhiyun struct ethtool_coalesce *coal)
1002*4882a593Smuzhiyun {
1003*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun coal->tx_coalesce_usecs = priv->tx_usecs;
1006*4882a593Smuzhiyun coal->tx_max_coalesced_frames = priv->tx_frames;
1007*4882a593Smuzhiyun coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun coal->rx_coalesce_usecs = priv->rx_usecs;
1010*4882a593Smuzhiyun coal->rx_max_coalesced_frames = priv->rx_frames;
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun coal->pkt_rate_low = priv->pkt_rate_low;
1013*4882a593Smuzhiyun coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
1014*4882a593Smuzhiyun coal->pkt_rate_high = priv->pkt_rate_high;
1015*4882a593Smuzhiyun coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
1016*4882a593Smuzhiyun coal->rate_sample_interval = priv->sample_interval;
1017*4882a593Smuzhiyun coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun return 0;
1020*4882a593Smuzhiyun }
1021*4882a593Smuzhiyun
mlx4_en_set_coalesce(struct net_device * dev,struct ethtool_coalesce * coal)1022*4882a593Smuzhiyun static int mlx4_en_set_coalesce(struct net_device *dev,
1023*4882a593Smuzhiyun struct ethtool_coalesce *coal)
1024*4882a593Smuzhiyun {
1025*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun if (!coal->tx_max_coalesced_frames_irq)
1028*4882a593Smuzhiyun return -EINVAL;
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun if (coal->tx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
1031*4882a593Smuzhiyun coal->rx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
1032*4882a593Smuzhiyun coal->rx_coalesce_usecs_low > MLX4_EN_MAX_COAL_TIME ||
1033*4882a593Smuzhiyun coal->rx_coalesce_usecs_high > MLX4_EN_MAX_COAL_TIME) {
1034*4882a593Smuzhiyun netdev_info(dev, "%s: maximum coalesce time supported is %d usecs\n",
1035*4882a593Smuzhiyun __func__, MLX4_EN_MAX_COAL_TIME);
1036*4882a593Smuzhiyun return -ERANGE;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun if (coal->tx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS ||
1040*4882a593Smuzhiyun coal->rx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS) {
1041*4882a593Smuzhiyun netdev_info(dev, "%s: maximum coalesced frames supported is %d\n",
1042*4882a593Smuzhiyun __func__, MLX4_EN_MAX_COAL_PKTS);
1043*4882a593Smuzhiyun return -ERANGE;
1044*4882a593Smuzhiyun }
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun priv->rx_frames = (coal->rx_max_coalesced_frames ==
1047*4882a593Smuzhiyun MLX4_EN_AUTO_CONF) ?
1048*4882a593Smuzhiyun MLX4_EN_RX_COAL_TARGET :
1049*4882a593Smuzhiyun coal->rx_max_coalesced_frames;
1050*4882a593Smuzhiyun priv->rx_usecs = (coal->rx_coalesce_usecs ==
1051*4882a593Smuzhiyun MLX4_EN_AUTO_CONF) ?
1052*4882a593Smuzhiyun MLX4_EN_RX_COAL_TIME :
1053*4882a593Smuzhiyun coal->rx_coalesce_usecs;
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun /* Setting TX coalescing parameters */
1056*4882a593Smuzhiyun if (coal->tx_coalesce_usecs != priv->tx_usecs ||
1057*4882a593Smuzhiyun coal->tx_max_coalesced_frames != priv->tx_frames) {
1058*4882a593Smuzhiyun priv->tx_usecs = coal->tx_coalesce_usecs;
1059*4882a593Smuzhiyun priv->tx_frames = coal->tx_max_coalesced_frames;
1060*4882a593Smuzhiyun }
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun /* Set adaptive coalescing params */
1063*4882a593Smuzhiyun priv->pkt_rate_low = coal->pkt_rate_low;
1064*4882a593Smuzhiyun priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
1065*4882a593Smuzhiyun priv->pkt_rate_high = coal->pkt_rate_high;
1066*4882a593Smuzhiyun priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
1067*4882a593Smuzhiyun priv->sample_interval = coal->rate_sample_interval;
1068*4882a593Smuzhiyun priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
1069*4882a593Smuzhiyun priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun return mlx4_en_moderation_update(priv);
1072*4882a593Smuzhiyun }
1073*4882a593Smuzhiyun
mlx4_en_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)1074*4882a593Smuzhiyun static int mlx4_en_set_pauseparam(struct net_device *dev,
1075*4882a593Smuzhiyun struct ethtool_pauseparam *pause)
1076*4882a593Smuzhiyun {
1077*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1078*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1079*4882a593Smuzhiyun u8 tx_pause, tx_ppp, rx_pause, rx_ppp;
1080*4882a593Smuzhiyun int err;
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun if (pause->autoneg)
1083*4882a593Smuzhiyun return -EINVAL;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun tx_pause = !!(pause->tx_pause);
1086*4882a593Smuzhiyun rx_pause = !!(pause->rx_pause);
1087*4882a593Smuzhiyun rx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->rx_ppp;
1088*4882a593Smuzhiyun tx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->tx_ppp;
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1091*4882a593Smuzhiyun priv->rx_skb_size + ETH_FCS_LEN,
1092*4882a593Smuzhiyun tx_pause, tx_ppp, rx_pause, rx_ppp);
1093*4882a593Smuzhiyun if (err) {
1094*4882a593Smuzhiyun en_err(priv, "Failed setting pause params, err = %d\n", err);
1095*4882a593Smuzhiyun return err;
1096*4882a593Smuzhiyun }
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
1099*4882a593Smuzhiyun rx_ppp, rx_pause, tx_ppp, tx_pause);
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun priv->prof->tx_pause = tx_pause;
1102*4882a593Smuzhiyun priv->prof->rx_pause = rx_pause;
1103*4882a593Smuzhiyun priv->prof->tx_ppp = tx_ppp;
1104*4882a593Smuzhiyun priv->prof->rx_ppp = rx_ppp;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun return err;
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun
mlx4_en_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * stats)1109*4882a593Smuzhiyun static void mlx4_en_get_pause_stats(struct net_device *dev,
1110*4882a593Smuzhiyun struct ethtool_pause_stats *stats)
1111*4882a593Smuzhiyun {
1112*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1113*4882a593Smuzhiyun struct bitmap_iterator it;
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun spin_lock_bh(&priv->stats_lock);
1118*4882a593Smuzhiyun if (test_bit(FLOW_PRIORITY_STATS_IDX_TX_FRAMES,
1119*4882a593Smuzhiyun priv->stats_bitmap.bitmap))
1120*4882a593Smuzhiyun stats->tx_pause_frames = priv->tx_flowstats.tx_pause;
1121*4882a593Smuzhiyun if (test_bit(FLOW_PRIORITY_STATS_IDX_RX_FRAMES,
1122*4882a593Smuzhiyun priv->stats_bitmap.bitmap))
1123*4882a593Smuzhiyun stats->rx_pause_frames = priv->rx_flowstats.rx_pause;
1124*4882a593Smuzhiyun spin_unlock_bh(&priv->stats_lock);
1125*4882a593Smuzhiyun }
1126*4882a593Smuzhiyun
mlx4_en_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)1127*4882a593Smuzhiyun static void mlx4_en_get_pauseparam(struct net_device *dev,
1128*4882a593Smuzhiyun struct ethtool_pauseparam *pause)
1129*4882a593Smuzhiyun {
1130*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun pause->tx_pause = priv->prof->tx_pause;
1133*4882a593Smuzhiyun pause->rx_pause = priv->prof->rx_pause;
1134*4882a593Smuzhiyun }
1135*4882a593Smuzhiyun
mlx4_en_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param)1136*4882a593Smuzhiyun static int mlx4_en_set_ringparam(struct net_device *dev,
1137*4882a593Smuzhiyun struct ethtool_ringparam *param)
1138*4882a593Smuzhiyun {
1139*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1140*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1141*4882a593Smuzhiyun struct mlx4_en_port_profile new_prof;
1142*4882a593Smuzhiyun struct mlx4_en_priv *tmp;
1143*4882a593Smuzhiyun u32 rx_size, tx_size;
1144*4882a593Smuzhiyun int port_up = 0;
1145*4882a593Smuzhiyun int err = 0;
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun if (param->rx_jumbo_pending || param->rx_mini_pending)
1148*4882a593Smuzhiyun return -EINVAL;
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun if (param->rx_pending < MLX4_EN_MIN_RX_SIZE) {
1151*4882a593Smuzhiyun en_warn(priv, "%s: rx_pending (%d) < min (%d)\n",
1152*4882a593Smuzhiyun __func__, param->rx_pending,
1153*4882a593Smuzhiyun MLX4_EN_MIN_RX_SIZE);
1154*4882a593Smuzhiyun return -EINVAL;
1155*4882a593Smuzhiyun }
1156*4882a593Smuzhiyun if (param->tx_pending < MLX4_EN_MIN_TX_SIZE) {
1157*4882a593Smuzhiyun en_warn(priv, "%s: tx_pending (%d) < min (%lu)\n",
1158*4882a593Smuzhiyun __func__, param->tx_pending,
1159*4882a593Smuzhiyun MLX4_EN_MIN_TX_SIZE);
1160*4882a593Smuzhiyun return -EINVAL;
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun rx_size = roundup_pow_of_two(param->rx_pending);
1164*4882a593Smuzhiyun tx_size = roundup_pow_of_two(param->tx_pending);
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
1167*4882a593Smuzhiyun priv->rx_ring[0]->size) &&
1168*4882a593Smuzhiyun tx_size == priv->tx_ring[TX][0]->size)
1169*4882a593Smuzhiyun return 0;
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1172*4882a593Smuzhiyun if (!tmp)
1173*4882a593Smuzhiyun return -ENOMEM;
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
1176*4882a593Smuzhiyun memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1177*4882a593Smuzhiyun new_prof.tx_ring_size = tx_size;
1178*4882a593Smuzhiyun new_prof.rx_ring_size = rx_size;
1179*4882a593Smuzhiyun err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
1180*4882a593Smuzhiyun if (err)
1181*4882a593Smuzhiyun goto out;
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun if (priv->port_up) {
1184*4882a593Smuzhiyun port_up = 1;
1185*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
1186*4882a593Smuzhiyun }
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun mlx4_en_safe_replace_resources(priv, tmp);
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun if (port_up) {
1191*4882a593Smuzhiyun err = mlx4_en_start_port(dev);
1192*4882a593Smuzhiyun if (err)
1193*4882a593Smuzhiyun en_err(priv, "Failed starting port\n");
1194*4882a593Smuzhiyun }
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun err = mlx4_en_moderation_update(priv);
1197*4882a593Smuzhiyun out:
1198*4882a593Smuzhiyun kfree(tmp);
1199*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
1200*4882a593Smuzhiyun return err;
1201*4882a593Smuzhiyun }
1202*4882a593Smuzhiyun
mlx4_en_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param)1203*4882a593Smuzhiyun static void mlx4_en_get_ringparam(struct net_device *dev,
1204*4882a593Smuzhiyun struct ethtool_ringparam *param)
1205*4882a593Smuzhiyun {
1206*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun memset(param, 0, sizeof(*param));
1209*4882a593Smuzhiyun param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
1210*4882a593Smuzhiyun param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
1211*4882a593Smuzhiyun param->rx_pending = priv->port_up ?
1212*4882a593Smuzhiyun priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
1213*4882a593Smuzhiyun param->tx_pending = priv->tx_ring[TX][0]->size;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun
mlx4_en_get_rxfh_indir_size(struct net_device * dev)1216*4882a593Smuzhiyun static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
1217*4882a593Smuzhiyun {
1218*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun return rounddown_pow_of_two(priv->rx_ring_num);
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun
mlx4_en_get_rxfh_key_size(struct net_device * netdev)1223*4882a593Smuzhiyun static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1224*4882a593Smuzhiyun {
1225*4882a593Smuzhiyun return MLX4_EN_RSS_KEY_SIZE;
1226*4882a593Smuzhiyun }
1227*4882a593Smuzhiyun
mlx4_en_check_rxfh_func(struct net_device * dev,u8 hfunc)1228*4882a593Smuzhiyun static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1229*4882a593Smuzhiyun {
1230*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun /* check if requested function is supported by the device */
1233*4882a593Smuzhiyun if (hfunc == ETH_RSS_HASH_TOP) {
1234*4882a593Smuzhiyun if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP))
1235*4882a593Smuzhiyun return -EINVAL;
1236*4882a593Smuzhiyun if (!(dev->features & NETIF_F_RXHASH))
1237*4882a593Smuzhiyun en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1238*4882a593Smuzhiyun return 0;
1239*4882a593Smuzhiyun } else if (hfunc == ETH_RSS_HASH_XOR) {
1240*4882a593Smuzhiyun if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))
1241*4882a593Smuzhiyun return -EINVAL;
1242*4882a593Smuzhiyun if (dev->features & NETIF_F_RXHASH)
1243*4882a593Smuzhiyun en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1244*4882a593Smuzhiyun return 0;
1245*4882a593Smuzhiyun }
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun return -EINVAL;
1248*4882a593Smuzhiyun }
1249*4882a593Smuzhiyun
mlx4_en_get_rxfh(struct net_device * dev,u32 * ring_index,u8 * key,u8 * hfunc)1250*4882a593Smuzhiyun static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1251*4882a593Smuzhiyun u8 *hfunc)
1252*4882a593Smuzhiyun {
1253*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1254*4882a593Smuzhiyun u32 n = mlx4_en_get_rxfh_indir_size(dev);
1255*4882a593Smuzhiyun u32 i, rss_rings;
1256*4882a593Smuzhiyun
1257*4882a593Smuzhiyun rss_rings = priv->prof->rss_rings ?: n;
1258*4882a593Smuzhiyun rss_rings = rounddown_pow_of_two(rss_rings);
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun for (i = 0; i < n; i++) {
1261*4882a593Smuzhiyun if (!ring_index)
1262*4882a593Smuzhiyun break;
1263*4882a593Smuzhiyun ring_index[i] = i % rss_rings;
1264*4882a593Smuzhiyun }
1265*4882a593Smuzhiyun if (key)
1266*4882a593Smuzhiyun memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
1267*4882a593Smuzhiyun if (hfunc)
1268*4882a593Smuzhiyun *hfunc = priv->rss_hash_fn;
1269*4882a593Smuzhiyun return 0;
1270*4882a593Smuzhiyun }
1271*4882a593Smuzhiyun
mlx4_en_set_rxfh(struct net_device * dev,const u32 * ring_index,const u8 * key,const u8 hfunc)1272*4882a593Smuzhiyun static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
1273*4882a593Smuzhiyun const u8 *key, const u8 hfunc)
1274*4882a593Smuzhiyun {
1275*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1276*4882a593Smuzhiyun u32 n = mlx4_en_get_rxfh_indir_size(dev);
1277*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1278*4882a593Smuzhiyun int port_up = 0;
1279*4882a593Smuzhiyun int err = 0;
1280*4882a593Smuzhiyun int i;
1281*4882a593Smuzhiyun int rss_rings = 0;
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun /* Calculate RSS table size and make sure flows are spread evenly
1284*4882a593Smuzhiyun * between rings
1285*4882a593Smuzhiyun */
1286*4882a593Smuzhiyun for (i = 0; i < n; i++) {
1287*4882a593Smuzhiyun if (!ring_index)
1288*4882a593Smuzhiyun break;
1289*4882a593Smuzhiyun if (i > 0 && !ring_index[i] && !rss_rings)
1290*4882a593Smuzhiyun rss_rings = i;
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun if (ring_index[i] != (i % (rss_rings ?: n)))
1293*4882a593Smuzhiyun return -EINVAL;
1294*4882a593Smuzhiyun }
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun if (!rss_rings)
1297*4882a593Smuzhiyun rss_rings = n;
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun /* RSS table size must be an order of 2 */
1300*4882a593Smuzhiyun if (!is_power_of_2(rss_rings))
1301*4882a593Smuzhiyun return -EINVAL;
1302*4882a593Smuzhiyun
1303*4882a593Smuzhiyun if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1304*4882a593Smuzhiyun err = mlx4_en_check_rxfh_func(dev, hfunc);
1305*4882a593Smuzhiyun if (err)
1306*4882a593Smuzhiyun return err;
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
1310*4882a593Smuzhiyun if (priv->port_up) {
1311*4882a593Smuzhiyun port_up = 1;
1312*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
1313*4882a593Smuzhiyun }
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun if (ring_index)
1316*4882a593Smuzhiyun priv->prof->rss_rings = rss_rings;
1317*4882a593Smuzhiyun if (key)
1318*4882a593Smuzhiyun memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
1319*4882a593Smuzhiyun if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1320*4882a593Smuzhiyun priv->rss_hash_fn = hfunc;
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun if (port_up) {
1323*4882a593Smuzhiyun err = mlx4_en_start_port(dev);
1324*4882a593Smuzhiyun if (err)
1325*4882a593Smuzhiyun en_err(priv, "Failed starting port\n");
1326*4882a593Smuzhiyun }
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
1329*4882a593Smuzhiyun return err;
1330*4882a593Smuzhiyun }
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun #define all_zeros_or_all_ones(field) \
1333*4882a593Smuzhiyun ((field) == 0 || (field) == (__force typeof(field))-1)
1334*4882a593Smuzhiyun
mlx4_en_validate_flow(struct net_device * dev,struct ethtool_rxnfc * cmd)1335*4882a593Smuzhiyun static int mlx4_en_validate_flow(struct net_device *dev,
1336*4882a593Smuzhiyun struct ethtool_rxnfc *cmd)
1337*4882a593Smuzhiyun {
1338*4882a593Smuzhiyun struct ethtool_usrip4_spec *l3_mask;
1339*4882a593Smuzhiyun struct ethtool_tcpip4_spec *l4_mask;
1340*4882a593Smuzhiyun struct ethhdr *eth_mask;
1341*4882a593Smuzhiyun
1342*4882a593Smuzhiyun if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1343*4882a593Smuzhiyun return -EINVAL;
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1346*4882a593Smuzhiyun /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1347*4882a593Smuzhiyun if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1348*4882a593Smuzhiyun return -EINVAL;
1349*4882a593Smuzhiyun }
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1352*4882a593Smuzhiyun case TCP_V4_FLOW:
1353*4882a593Smuzhiyun case UDP_V4_FLOW:
1354*4882a593Smuzhiyun if (cmd->fs.m_u.tcp_ip4_spec.tos)
1355*4882a593Smuzhiyun return -EINVAL;
1356*4882a593Smuzhiyun l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1357*4882a593Smuzhiyun /* don't allow mask which isn't all 0 or 1 */
1358*4882a593Smuzhiyun if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1359*4882a593Smuzhiyun !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1360*4882a593Smuzhiyun !all_zeros_or_all_ones(l4_mask->psrc) ||
1361*4882a593Smuzhiyun !all_zeros_or_all_ones(l4_mask->pdst))
1362*4882a593Smuzhiyun return -EINVAL;
1363*4882a593Smuzhiyun break;
1364*4882a593Smuzhiyun case IP_USER_FLOW:
1365*4882a593Smuzhiyun l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1366*4882a593Smuzhiyun if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1367*4882a593Smuzhiyun cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1368*4882a593Smuzhiyun (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1369*4882a593Smuzhiyun !all_zeros_or_all_ones(l3_mask->ip4src) ||
1370*4882a593Smuzhiyun !all_zeros_or_all_ones(l3_mask->ip4dst))
1371*4882a593Smuzhiyun return -EINVAL;
1372*4882a593Smuzhiyun break;
1373*4882a593Smuzhiyun case ETHER_FLOW:
1374*4882a593Smuzhiyun eth_mask = &cmd->fs.m_u.ether_spec;
1375*4882a593Smuzhiyun /* source mac mask must not be set */
1376*4882a593Smuzhiyun if (!is_zero_ether_addr(eth_mask->h_source))
1377*4882a593Smuzhiyun return -EINVAL;
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1380*4882a593Smuzhiyun if (!is_broadcast_ether_addr(eth_mask->h_dest))
1381*4882a593Smuzhiyun return -EINVAL;
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun if (!all_zeros_or_all_ones(eth_mask->h_proto))
1384*4882a593Smuzhiyun return -EINVAL;
1385*4882a593Smuzhiyun break;
1386*4882a593Smuzhiyun default:
1387*4882a593Smuzhiyun return -EINVAL;
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun if ((cmd->fs.flow_type & FLOW_EXT)) {
1391*4882a593Smuzhiyun if (cmd->fs.m_ext.vlan_etype ||
1392*4882a593Smuzhiyun !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1393*4882a593Smuzhiyun 0 ||
1394*4882a593Smuzhiyun (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1395*4882a593Smuzhiyun cpu_to_be16(VLAN_VID_MASK)))
1396*4882a593Smuzhiyun return -EINVAL;
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun if (cmd->fs.m_ext.vlan_tci) {
1399*4882a593Smuzhiyun if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1400*4882a593Smuzhiyun return -EINVAL;
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun }
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun return 0;
1406*4882a593Smuzhiyun }
1407*4882a593Smuzhiyun
mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc * cmd,struct list_head * rule_list_h,struct mlx4_spec_list * spec_l2,unsigned char * mac)1408*4882a593Smuzhiyun static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1409*4882a593Smuzhiyun struct list_head *rule_list_h,
1410*4882a593Smuzhiyun struct mlx4_spec_list *spec_l2,
1411*4882a593Smuzhiyun unsigned char *mac)
1412*4882a593Smuzhiyun {
1413*4882a593Smuzhiyun __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1416*4882a593Smuzhiyun memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1417*4882a593Smuzhiyun memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1418*4882a593Smuzhiyun
1419*4882a593Smuzhiyun if ((cmd->fs.flow_type & FLOW_EXT) &&
1420*4882a593Smuzhiyun (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
1421*4882a593Smuzhiyun spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
1422*4882a593Smuzhiyun spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
1423*4882a593Smuzhiyun }
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun list_add_tail(&spec_l2->list, rule_list_h);
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun return 0;
1428*4882a593Smuzhiyun }
1429*4882a593Smuzhiyun
mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv * priv,struct ethtool_rxnfc * cmd,struct list_head * rule_list_h,struct mlx4_spec_list * spec_l2,__be32 ipv4_dst)1430*4882a593Smuzhiyun static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1431*4882a593Smuzhiyun struct ethtool_rxnfc *cmd,
1432*4882a593Smuzhiyun struct list_head *rule_list_h,
1433*4882a593Smuzhiyun struct mlx4_spec_list *spec_l2,
1434*4882a593Smuzhiyun __be32 ipv4_dst)
1435*4882a593Smuzhiyun {
1436*4882a593Smuzhiyun #ifdef CONFIG_INET
1437*4882a593Smuzhiyun unsigned char mac[ETH_ALEN];
1438*4882a593Smuzhiyun
1439*4882a593Smuzhiyun if (!ipv4_is_multicast(ipv4_dst)) {
1440*4882a593Smuzhiyun if (cmd->fs.flow_type & FLOW_MAC_EXT)
1441*4882a593Smuzhiyun memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
1442*4882a593Smuzhiyun else
1443*4882a593Smuzhiyun memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
1444*4882a593Smuzhiyun } else {
1445*4882a593Smuzhiyun ip_eth_mc_map(ipv4_dst, mac);
1446*4882a593Smuzhiyun }
1447*4882a593Smuzhiyun
1448*4882a593Smuzhiyun return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
1449*4882a593Smuzhiyun #else
1450*4882a593Smuzhiyun return -EINVAL;
1451*4882a593Smuzhiyun #endif
1452*4882a593Smuzhiyun }
1453*4882a593Smuzhiyun
add_ip_rule(struct mlx4_en_priv * priv,struct ethtool_rxnfc * cmd,struct list_head * list_h)1454*4882a593Smuzhiyun static int add_ip_rule(struct mlx4_en_priv *priv,
1455*4882a593Smuzhiyun struct ethtool_rxnfc *cmd,
1456*4882a593Smuzhiyun struct list_head *list_h)
1457*4882a593Smuzhiyun {
1458*4882a593Smuzhiyun int err;
1459*4882a593Smuzhiyun struct mlx4_spec_list *spec_l2 = NULL;
1460*4882a593Smuzhiyun struct mlx4_spec_list *spec_l3 = NULL;
1461*4882a593Smuzhiyun struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1462*4882a593Smuzhiyun
1463*4882a593Smuzhiyun spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1464*4882a593Smuzhiyun spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1465*4882a593Smuzhiyun if (!spec_l2 || !spec_l3) {
1466*4882a593Smuzhiyun err = -ENOMEM;
1467*4882a593Smuzhiyun goto free_spec;
1468*4882a593Smuzhiyun }
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1471*4882a593Smuzhiyun cmd->fs.h_u.
1472*4882a593Smuzhiyun usr_ip4_spec.ip4dst);
1473*4882a593Smuzhiyun if (err)
1474*4882a593Smuzhiyun goto free_spec;
1475*4882a593Smuzhiyun spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1476*4882a593Smuzhiyun spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1477*4882a593Smuzhiyun if (l3_mask->ip4src)
1478*4882a593Smuzhiyun spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1479*4882a593Smuzhiyun spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1480*4882a593Smuzhiyun if (l3_mask->ip4dst)
1481*4882a593Smuzhiyun spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1482*4882a593Smuzhiyun list_add_tail(&spec_l3->list, list_h);
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun return 0;
1485*4882a593Smuzhiyun
1486*4882a593Smuzhiyun free_spec:
1487*4882a593Smuzhiyun kfree(spec_l2);
1488*4882a593Smuzhiyun kfree(spec_l3);
1489*4882a593Smuzhiyun return err;
1490*4882a593Smuzhiyun }
1491*4882a593Smuzhiyun
add_tcp_udp_rule(struct mlx4_en_priv * priv,struct ethtool_rxnfc * cmd,struct list_head * list_h,int proto)1492*4882a593Smuzhiyun static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1493*4882a593Smuzhiyun struct ethtool_rxnfc *cmd,
1494*4882a593Smuzhiyun struct list_head *list_h, int proto)
1495*4882a593Smuzhiyun {
1496*4882a593Smuzhiyun int err;
1497*4882a593Smuzhiyun struct mlx4_spec_list *spec_l2 = NULL;
1498*4882a593Smuzhiyun struct mlx4_spec_list *spec_l3 = NULL;
1499*4882a593Smuzhiyun struct mlx4_spec_list *spec_l4 = NULL;
1500*4882a593Smuzhiyun struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1501*4882a593Smuzhiyun
1502*4882a593Smuzhiyun spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1503*4882a593Smuzhiyun spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1504*4882a593Smuzhiyun spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1505*4882a593Smuzhiyun if (!spec_l2 || !spec_l3 || !spec_l4) {
1506*4882a593Smuzhiyun err = -ENOMEM;
1507*4882a593Smuzhiyun goto free_spec;
1508*4882a593Smuzhiyun }
1509*4882a593Smuzhiyun
1510*4882a593Smuzhiyun spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun if (proto == TCP_V4_FLOW) {
1513*4882a593Smuzhiyun err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1514*4882a593Smuzhiyun spec_l2,
1515*4882a593Smuzhiyun cmd->fs.h_u.
1516*4882a593Smuzhiyun tcp_ip4_spec.ip4dst);
1517*4882a593Smuzhiyun if (err)
1518*4882a593Smuzhiyun goto free_spec;
1519*4882a593Smuzhiyun spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1520*4882a593Smuzhiyun spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1521*4882a593Smuzhiyun spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1522*4882a593Smuzhiyun spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1523*4882a593Smuzhiyun spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1524*4882a593Smuzhiyun } else {
1525*4882a593Smuzhiyun err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1526*4882a593Smuzhiyun spec_l2,
1527*4882a593Smuzhiyun cmd->fs.h_u.
1528*4882a593Smuzhiyun udp_ip4_spec.ip4dst);
1529*4882a593Smuzhiyun if (err)
1530*4882a593Smuzhiyun goto free_spec;
1531*4882a593Smuzhiyun spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1532*4882a593Smuzhiyun spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1533*4882a593Smuzhiyun spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1534*4882a593Smuzhiyun spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1535*4882a593Smuzhiyun spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1536*4882a593Smuzhiyun }
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun if (l4_mask->ip4src)
1539*4882a593Smuzhiyun spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1540*4882a593Smuzhiyun if (l4_mask->ip4dst)
1541*4882a593Smuzhiyun spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1542*4882a593Smuzhiyun
1543*4882a593Smuzhiyun if (l4_mask->psrc)
1544*4882a593Smuzhiyun spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1545*4882a593Smuzhiyun if (l4_mask->pdst)
1546*4882a593Smuzhiyun spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun list_add_tail(&spec_l3->list, list_h);
1549*4882a593Smuzhiyun list_add_tail(&spec_l4->list, list_h);
1550*4882a593Smuzhiyun
1551*4882a593Smuzhiyun return 0;
1552*4882a593Smuzhiyun
1553*4882a593Smuzhiyun free_spec:
1554*4882a593Smuzhiyun kfree(spec_l2);
1555*4882a593Smuzhiyun kfree(spec_l3);
1556*4882a593Smuzhiyun kfree(spec_l4);
1557*4882a593Smuzhiyun return err;
1558*4882a593Smuzhiyun }
1559*4882a593Smuzhiyun
mlx4_en_ethtool_to_net_trans_rule(struct net_device * dev,struct ethtool_rxnfc * cmd,struct list_head * rule_list_h)1560*4882a593Smuzhiyun static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1561*4882a593Smuzhiyun struct ethtool_rxnfc *cmd,
1562*4882a593Smuzhiyun struct list_head *rule_list_h)
1563*4882a593Smuzhiyun {
1564*4882a593Smuzhiyun int err;
1565*4882a593Smuzhiyun struct ethhdr *eth_spec;
1566*4882a593Smuzhiyun struct mlx4_spec_list *spec_l2;
1567*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1568*4882a593Smuzhiyun
1569*4882a593Smuzhiyun err = mlx4_en_validate_flow(dev, cmd);
1570*4882a593Smuzhiyun if (err)
1571*4882a593Smuzhiyun return err;
1572*4882a593Smuzhiyun
1573*4882a593Smuzhiyun switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1574*4882a593Smuzhiyun case ETHER_FLOW:
1575*4882a593Smuzhiyun spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1576*4882a593Smuzhiyun if (!spec_l2)
1577*4882a593Smuzhiyun return -ENOMEM;
1578*4882a593Smuzhiyun
1579*4882a593Smuzhiyun eth_spec = &cmd->fs.h_u.ether_spec;
1580*4882a593Smuzhiyun mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1581*4882a593Smuzhiyun ð_spec->h_dest[0]);
1582*4882a593Smuzhiyun spec_l2->eth.ether_type = eth_spec->h_proto;
1583*4882a593Smuzhiyun if (eth_spec->h_proto)
1584*4882a593Smuzhiyun spec_l2->eth.ether_type_enable = 1;
1585*4882a593Smuzhiyun break;
1586*4882a593Smuzhiyun case IP_USER_FLOW:
1587*4882a593Smuzhiyun err = add_ip_rule(priv, cmd, rule_list_h);
1588*4882a593Smuzhiyun break;
1589*4882a593Smuzhiyun case TCP_V4_FLOW:
1590*4882a593Smuzhiyun err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1591*4882a593Smuzhiyun break;
1592*4882a593Smuzhiyun case UDP_V4_FLOW:
1593*4882a593Smuzhiyun err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1594*4882a593Smuzhiyun break;
1595*4882a593Smuzhiyun }
1596*4882a593Smuzhiyun
1597*4882a593Smuzhiyun return err;
1598*4882a593Smuzhiyun }
1599*4882a593Smuzhiyun
mlx4_en_flow_replace(struct net_device * dev,struct ethtool_rxnfc * cmd)1600*4882a593Smuzhiyun static int mlx4_en_flow_replace(struct net_device *dev,
1601*4882a593Smuzhiyun struct ethtool_rxnfc *cmd)
1602*4882a593Smuzhiyun {
1603*4882a593Smuzhiyun int err;
1604*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1605*4882a593Smuzhiyun struct ethtool_flow_id *loc_rule;
1606*4882a593Smuzhiyun struct mlx4_spec_list *spec, *tmp_spec;
1607*4882a593Smuzhiyun u32 qpn;
1608*4882a593Smuzhiyun u64 reg_id;
1609*4882a593Smuzhiyun
1610*4882a593Smuzhiyun struct mlx4_net_trans_rule rule = {
1611*4882a593Smuzhiyun .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1612*4882a593Smuzhiyun .exclusive = 0,
1613*4882a593Smuzhiyun .allow_loopback = 1,
1614*4882a593Smuzhiyun .promisc_mode = MLX4_FS_REGULAR,
1615*4882a593Smuzhiyun };
1616*4882a593Smuzhiyun
1617*4882a593Smuzhiyun rule.port = priv->port;
1618*4882a593Smuzhiyun rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1619*4882a593Smuzhiyun INIT_LIST_HEAD(&rule.list);
1620*4882a593Smuzhiyun
1621*4882a593Smuzhiyun /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1622*4882a593Smuzhiyun if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
1623*4882a593Smuzhiyun qpn = priv->drop_qp.qpn;
1624*4882a593Smuzhiyun else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1625*4882a593Smuzhiyun qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1626*4882a593Smuzhiyun } else {
1627*4882a593Smuzhiyun if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1628*4882a593Smuzhiyun en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
1629*4882a593Smuzhiyun cmd->fs.ring_cookie);
1630*4882a593Smuzhiyun return -EINVAL;
1631*4882a593Smuzhiyun }
1632*4882a593Smuzhiyun qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1633*4882a593Smuzhiyun if (!qpn) {
1634*4882a593Smuzhiyun en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
1635*4882a593Smuzhiyun cmd->fs.ring_cookie);
1636*4882a593Smuzhiyun return -EINVAL;
1637*4882a593Smuzhiyun }
1638*4882a593Smuzhiyun }
1639*4882a593Smuzhiyun rule.qpn = qpn;
1640*4882a593Smuzhiyun err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1641*4882a593Smuzhiyun if (err)
1642*4882a593Smuzhiyun goto out_free_list;
1643*4882a593Smuzhiyun
1644*4882a593Smuzhiyun loc_rule = &priv->ethtool_rules[cmd->fs.location];
1645*4882a593Smuzhiyun if (loc_rule->id) {
1646*4882a593Smuzhiyun err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1647*4882a593Smuzhiyun if (err) {
1648*4882a593Smuzhiyun en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1649*4882a593Smuzhiyun cmd->fs.location, loc_rule->id);
1650*4882a593Smuzhiyun goto out_free_list;
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun loc_rule->id = 0;
1653*4882a593Smuzhiyun memset(&loc_rule->flow_spec, 0,
1654*4882a593Smuzhiyun sizeof(struct ethtool_rx_flow_spec));
1655*4882a593Smuzhiyun list_del(&loc_rule->list);
1656*4882a593Smuzhiyun }
1657*4882a593Smuzhiyun err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id);
1658*4882a593Smuzhiyun if (err) {
1659*4882a593Smuzhiyun en_err(priv, "Fail to attach network rule at location %d\n",
1660*4882a593Smuzhiyun cmd->fs.location);
1661*4882a593Smuzhiyun goto out_free_list;
1662*4882a593Smuzhiyun }
1663*4882a593Smuzhiyun loc_rule->id = reg_id;
1664*4882a593Smuzhiyun memcpy(&loc_rule->flow_spec, &cmd->fs,
1665*4882a593Smuzhiyun sizeof(struct ethtool_rx_flow_spec));
1666*4882a593Smuzhiyun list_add_tail(&loc_rule->list, &priv->ethtool_list);
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun out_free_list:
1669*4882a593Smuzhiyun list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1670*4882a593Smuzhiyun list_del(&spec->list);
1671*4882a593Smuzhiyun kfree(spec);
1672*4882a593Smuzhiyun }
1673*4882a593Smuzhiyun return err;
1674*4882a593Smuzhiyun }
1675*4882a593Smuzhiyun
mlx4_en_flow_detach(struct net_device * dev,struct ethtool_rxnfc * cmd)1676*4882a593Smuzhiyun static int mlx4_en_flow_detach(struct net_device *dev,
1677*4882a593Smuzhiyun struct ethtool_rxnfc *cmd)
1678*4882a593Smuzhiyun {
1679*4882a593Smuzhiyun int err = 0;
1680*4882a593Smuzhiyun struct ethtool_flow_id *rule;
1681*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1682*4882a593Smuzhiyun
1683*4882a593Smuzhiyun if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1684*4882a593Smuzhiyun return -EINVAL;
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun rule = &priv->ethtool_rules[cmd->fs.location];
1687*4882a593Smuzhiyun if (!rule->id) {
1688*4882a593Smuzhiyun err = -ENOENT;
1689*4882a593Smuzhiyun goto out;
1690*4882a593Smuzhiyun }
1691*4882a593Smuzhiyun
1692*4882a593Smuzhiyun err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1693*4882a593Smuzhiyun if (err) {
1694*4882a593Smuzhiyun en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1695*4882a593Smuzhiyun cmd->fs.location, rule->id);
1696*4882a593Smuzhiyun goto out;
1697*4882a593Smuzhiyun }
1698*4882a593Smuzhiyun rule->id = 0;
1699*4882a593Smuzhiyun memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
1700*4882a593Smuzhiyun list_del(&rule->list);
1701*4882a593Smuzhiyun out:
1702*4882a593Smuzhiyun return err;
1703*4882a593Smuzhiyun
1704*4882a593Smuzhiyun }
1705*4882a593Smuzhiyun
mlx4_en_get_flow(struct net_device * dev,struct ethtool_rxnfc * cmd,int loc)1706*4882a593Smuzhiyun static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1707*4882a593Smuzhiyun int loc)
1708*4882a593Smuzhiyun {
1709*4882a593Smuzhiyun int err = 0;
1710*4882a593Smuzhiyun struct ethtool_flow_id *rule;
1711*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1712*4882a593Smuzhiyun
1713*4882a593Smuzhiyun if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1714*4882a593Smuzhiyun return -EINVAL;
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun rule = &priv->ethtool_rules[loc];
1717*4882a593Smuzhiyun if (rule->id)
1718*4882a593Smuzhiyun memcpy(&cmd->fs, &rule->flow_spec,
1719*4882a593Smuzhiyun sizeof(struct ethtool_rx_flow_spec));
1720*4882a593Smuzhiyun else
1721*4882a593Smuzhiyun err = -ENOENT;
1722*4882a593Smuzhiyun
1723*4882a593Smuzhiyun return err;
1724*4882a593Smuzhiyun }
1725*4882a593Smuzhiyun
mlx4_en_get_num_flows(struct mlx4_en_priv * priv)1726*4882a593Smuzhiyun static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1727*4882a593Smuzhiyun {
1728*4882a593Smuzhiyun
1729*4882a593Smuzhiyun int i, res = 0;
1730*4882a593Smuzhiyun for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1731*4882a593Smuzhiyun if (priv->ethtool_rules[i].id)
1732*4882a593Smuzhiyun res++;
1733*4882a593Smuzhiyun }
1734*4882a593Smuzhiyun return res;
1735*4882a593Smuzhiyun
1736*4882a593Smuzhiyun }
1737*4882a593Smuzhiyun
mlx4_en_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1738*4882a593Smuzhiyun static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1739*4882a593Smuzhiyun u32 *rule_locs)
1740*4882a593Smuzhiyun {
1741*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1742*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1743*4882a593Smuzhiyun int err = 0;
1744*4882a593Smuzhiyun int i = 0, priority = 0;
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1747*4882a593Smuzhiyun cmd->cmd == ETHTOOL_GRXCLSRULE ||
1748*4882a593Smuzhiyun cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
1749*4882a593Smuzhiyun (mdev->dev->caps.steering_mode !=
1750*4882a593Smuzhiyun MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
1751*4882a593Smuzhiyun return -EINVAL;
1752*4882a593Smuzhiyun
1753*4882a593Smuzhiyun switch (cmd->cmd) {
1754*4882a593Smuzhiyun case ETHTOOL_GRXRINGS:
1755*4882a593Smuzhiyun cmd->data = priv->rx_ring_num;
1756*4882a593Smuzhiyun break;
1757*4882a593Smuzhiyun case ETHTOOL_GRXCLSRLCNT:
1758*4882a593Smuzhiyun cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1759*4882a593Smuzhiyun break;
1760*4882a593Smuzhiyun case ETHTOOL_GRXCLSRULE:
1761*4882a593Smuzhiyun err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1762*4882a593Smuzhiyun break;
1763*4882a593Smuzhiyun case ETHTOOL_GRXCLSRLALL:
1764*4882a593Smuzhiyun cmd->data = MAX_NUM_OF_FS_RULES;
1765*4882a593Smuzhiyun while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1766*4882a593Smuzhiyun err = mlx4_en_get_flow(dev, cmd, i);
1767*4882a593Smuzhiyun if (!err)
1768*4882a593Smuzhiyun rule_locs[priority++] = i;
1769*4882a593Smuzhiyun i++;
1770*4882a593Smuzhiyun }
1771*4882a593Smuzhiyun err = 0;
1772*4882a593Smuzhiyun break;
1773*4882a593Smuzhiyun default:
1774*4882a593Smuzhiyun err = -EOPNOTSUPP;
1775*4882a593Smuzhiyun break;
1776*4882a593Smuzhiyun }
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun return err;
1779*4882a593Smuzhiyun }
1780*4882a593Smuzhiyun
mlx4_en_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1781*4882a593Smuzhiyun static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1782*4882a593Smuzhiyun {
1783*4882a593Smuzhiyun int err = 0;
1784*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1785*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1786*4882a593Smuzhiyun
1787*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode !=
1788*4882a593Smuzhiyun MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
1789*4882a593Smuzhiyun return -EINVAL;
1790*4882a593Smuzhiyun
1791*4882a593Smuzhiyun switch (cmd->cmd) {
1792*4882a593Smuzhiyun case ETHTOOL_SRXCLSRLINS:
1793*4882a593Smuzhiyun err = mlx4_en_flow_replace(dev, cmd);
1794*4882a593Smuzhiyun break;
1795*4882a593Smuzhiyun case ETHTOOL_SRXCLSRLDEL:
1796*4882a593Smuzhiyun err = mlx4_en_flow_detach(dev, cmd);
1797*4882a593Smuzhiyun break;
1798*4882a593Smuzhiyun default:
1799*4882a593Smuzhiyun en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1800*4882a593Smuzhiyun return -EINVAL;
1801*4882a593Smuzhiyun }
1802*4882a593Smuzhiyun
1803*4882a593Smuzhiyun return err;
1804*4882a593Smuzhiyun }
1805*4882a593Smuzhiyun
mlx4_en_get_max_num_rx_rings(struct net_device * dev)1806*4882a593Smuzhiyun static int mlx4_en_get_max_num_rx_rings(struct net_device *dev)
1807*4882a593Smuzhiyun {
1808*4882a593Smuzhiyun return min_t(int, num_online_cpus(), MAX_RX_RINGS);
1809*4882a593Smuzhiyun }
1810*4882a593Smuzhiyun
mlx4_en_get_channels(struct net_device * dev,struct ethtool_channels * channel)1811*4882a593Smuzhiyun static void mlx4_en_get_channels(struct net_device *dev,
1812*4882a593Smuzhiyun struct ethtool_channels *channel)
1813*4882a593Smuzhiyun {
1814*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1815*4882a593Smuzhiyun
1816*4882a593Smuzhiyun channel->max_rx = mlx4_en_get_max_num_rx_rings(dev);
1817*4882a593Smuzhiyun channel->max_tx = priv->mdev->profile.max_num_tx_rings_p_up;
1818*4882a593Smuzhiyun
1819*4882a593Smuzhiyun channel->rx_count = priv->rx_ring_num;
1820*4882a593Smuzhiyun channel->tx_count = priv->tx_ring_num[TX] /
1821*4882a593Smuzhiyun priv->prof->num_up;
1822*4882a593Smuzhiyun }
1823*4882a593Smuzhiyun
mlx4_en_set_channels(struct net_device * dev,struct ethtool_channels * channel)1824*4882a593Smuzhiyun static int mlx4_en_set_channels(struct net_device *dev,
1825*4882a593Smuzhiyun struct ethtool_channels *channel)
1826*4882a593Smuzhiyun {
1827*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1828*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1829*4882a593Smuzhiyun struct mlx4_en_port_profile new_prof;
1830*4882a593Smuzhiyun struct mlx4_en_priv *tmp;
1831*4882a593Smuzhiyun int total_tx_count;
1832*4882a593Smuzhiyun int port_up = 0;
1833*4882a593Smuzhiyun int xdp_count;
1834*4882a593Smuzhiyun int err = 0;
1835*4882a593Smuzhiyun u8 up;
1836*4882a593Smuzhiyun
1837*4882a593Smuzhiyun if (!channel->tx_count || !channel->rx_count)
1838*4882a593Smuzhiyun return -EINVAL;
1839*4882a593Smuzhiyun
1840*4882a593Smuzhiyun tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1841*4882a593Smuzhiyun if (!tmp)
1842*4882a593Smuzhiyun return -ENOMEM;
1843*4882a593Smuzhiyun
1844*4882a593Smuzhiyun mutex_lock(&mdev->state_lock);
1845*4882a593Smuzhiyun xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0;
1846*4882a593Smuzhiyun total_tx_count = channel->tx_count * priv->prof->num_up + xdp_count;
1847*4882a593Smuzhiyun if (total_tx_count > MAX_TX_RINGS) {
1848*4882a593Smuzhiyun err = -EINVAL;
1849*4882a593Smuzhiyun en_err(priv,
1850*4882a593Smuzhiyun "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n",
1851*4882a593Smuzhiyun total_tx_count, MAX_TX_RINGS);
1852*4882a593Smuzhiyun goto out;
1853*4882a593Smuzhiyun }
1854*4882a593Smuzhiyun
1855*4882a593Smuzhiyun memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1856*4882a593Smuzhiyun new_prof.num_tx_rings_p_up = channel->tx_count;
1857*4882a593Smuzhiyun new_prof.tx_ring_num[TX] = channel->tx_count * priv->prof->num_up;
1858*4882a593Smuzhiyun new_prof.tx_ring_num[TX_XDP] = xdp_count;
1859*4882a593Smuzhiyun new_prof.rx_ring_num = channel->rx_count;
1860*4882a593Smuzhiyun
1861*4882a593Smuzhiyun err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
1862*4882a593Smuzhiyun if (err)
1863*4882a593Smuzhiyun goto out;
1864*4882a593Smuzhiyun
1865*4882a593Smuzhiyun if (priv->port_up) {
1866*4882a593Smuzhiyun port_up = 1;
1867*4882a593Smuzhiyun mlx4_en_stop_port(dev, 1);
1868*4882a593Smuzhiyun }
1869*4882a593Smuzhiyun
1870*4882a593Smuzhiyun mlx4_en_safe_replace_resources(priv, tmp);
1871*4882a593Smuzhiyun
1872*4882a593Smuzhiyun netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun up = (priv->prof->num_up == MLX4_EN_NUM_UP_LOW) ?
1875*4882a593Smuzhiyun 0 : priv->prof->num_up;
1876*4882a593Smuzhiyun mlx4_en_setup_tc(dev, up);
1877*4882a593Smuzhiyun
1878*4882a593Smuzhiyun en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]);
1879*4882a593Smuzhiyun en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1880*4882a593Smuzhiyun
1881*4882a593Smuzhiyun if (port_up) {
1882*4882a593Smuzhiyun err = mlx4_en_start_port(dev);
1883*4882a593Smuzhiyun if (err)
1884*4882a593Smuzhiyun en_err(priv, "Failed starting port\n");
1885*4882a593Smuzhiyun }
1886*4882a593Smuzhiyun
1887*4882a593Smuzhiyun err = mlx4_en_moderation_update(priv);
1888*4882a593Smuzhiyun out:
1889*4882a593Smuzhiyun mutex_unlock(&mdev->state_lock);
1890*4882a593Smuzhiyun kfree(tmp);
1891*4882a593Smuzhiyun return err;
1892*4882a593Smuzhiyun }
1893*4882a593Smuzhiyun
mlx4_en_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)1894*4882a593Smuzhiyun static int mlx4_en_get_ts_info(struct net_device *dev,
1895*4882a593Smuzhiyun struct ethtool_ts_info *info)
1896*4882a593Smuzhiyun {
1897*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1898*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1899*4882a593Smuzhiyun int ret;
1900*4882a593Smuzhiyun
1901*4882a593Smuzhiyun ret = ethtool_op_get_ts_info(dev, info);
1902*4882a593Smuzhiyun if (ret)
1903*4882a593Smuzhiyun return ret;
1904*4882a593Smuzhiyun
1905*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1906*4882a593Smuzhiyun info->so_timestamping |=
1907*4882a593Smuzhiyun SOF_TIMESTAMPING_TX_HARDWARE |
1908*4882a593Smuzhiyun SOF_TIMESTAMPING_RX_HARDWARE |
1909*4882a593Smuzhiyun SOF_TIMESTAMPING_RAW_HARDWARE;
1910*4882a593Smuzhiyun
1911*4882a593Smuzhiyun info->tx_types =
1912*4882a593Smuzhiyun (1 << HWTSTAMP_TX_OFF) |
1913*4882a593Smuzhiyun (1 << HWTSTAMP_TX_ON);
1914*4882a593Smuzhiyun
1915*4882a593Smuzhiyun info->rx_filters =
1916*4882a593Smuzhiyun (1 << HWTSTAMP_FILTER_NONE) |
1917*4882a593Smuzhiyun (1 << HWTSTAMP_FILTER_ALL);
1918*4882a593Smuzhiyun
1919*4882a593Smuzhiyun if (mdev->ptp_clock)
1920*4882a593Smuzhiyun info->phc_index = ptp_clock_index(mdev->ptp_clock);
1921*4882a593Smuzhiyun }
1922*4882a593Smuzhiyun
1923*4882a593Smuzhiyun return ret;
1924*4882a593Smuzhiyun }
1925*4882a593Smuzhiyun
mlx4_en_set_priv_flags(struct net_device * dev,u32 flags)1926*4882a593Smuzhiyun static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
1927*4882a593Smuzhiyun {
1928*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1929*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
1930*4882a593Smuzhiyun bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1931*4882a593Smuzhiyun bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1932*4882a593Smuzhiyun bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV);
1933*4882a593Smuzhiyun bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV);
1934*4882a593Smuzhiyun int i;
1935*4882a593Smuzhiyun int ret = 0;
1936*4882a593Smuzhiyun
1937*4882a593Smuzhiyun if (bf_enabled_new != bf_enabled_old) {
1938*4882a593Smuzhiyun int t;
1939*4882a593Smuzhiyun
1940*4882a593Smuzhiyun if (bf_enabled_new) {
1941*4882a593Smuzhiyun bool bf_supported = true;
1942*4882a593Smuzhiyun
1943*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1944*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++)
1945*4882a593Smuzhiyun bf_supported &=
1946*4882a593Smuzhiyun priv->tx_ring[t][i]->bf_alloced;
1947*4882a593Smuzhiyun
1948*4882a593Smuzhiyun if (!bf_supported) {
1949*4882a593Smuzhiyun en_err(priv, "BlueFlame is not supported\n");
1950*4882a593Smuzhiyun return -EINVAL;
1951*4882a593Smuzhiyun }
1952*4882a593Smuzhiyun
1953*4882a593Smuzhiyun priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1954*4882a593Smuzhiyun } else {
1955*4882a593Smuzhiyun priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1956*4882a593Smuzhiyun }
1957*4882a593Smuzhiyun
1958*4882a593Smuzhiyun for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1959*4882a593Smuzhiyun for (i = 0; i < priv->tx_ring_num[t]; i++)
1960*4882a593Smuzhiyun priv->tx_ring[t][i]->bf_enabled =
1961*4882a593Smuzhiyun bf_enabled_new;
1962*4882a593Smuzhiyun
1963*4882a593Smuzhiyun en_info(priv, "BlueFlame %s\n",
1964*4882a593Smuzhiyun bf_enabled_new ? "Enabled" : "Disabled");
1965*4882a593Smuzhiyun }
1966*4882a593Smuzhiyun
1967*4882a593Smuzhiyun if (phv_enabled_new != phv_enabled_old) {
1968*4882a593Smuzhiyun ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new);
1969*4882a593Smuzhiyun if (ret)
1970*4882a593Smuzhiyun return ret;
1971*4882a593Smuzhiyun else if (phv_enabled_new)
1972*4882a593Smuzhiyun priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
1973*4882a593Smuzhiyun else
1974*4882a593Smuzhiyun priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV;
1975*4882a593Smuzhiyun en_info(priv, "PHV bit %s\n",
1976*4882a593Smuzhiyun phv_enabled_new ? "Enabled" : "Disabled");
1977*4882a593Smuzhiyun }
1978*4882a593Smuzhiyun return 0;
1979*4882a593Smuzhiyun }
1980*4882a593Smuzhiyun
mlx4_en_get_priv_flags(struct net_device * dev)1981*4882a593Smuzhiyun static u32 mlx4_en_get_priv_flags(struct net_device *dev)
1982*4882a593Smuzhiyun {
1983*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
1984*4882a593Smuzhiyun
1985*4882a593Smuzhiyun return priv->pflags;
1986*4882a593Smuzhiyun }
1987*4882a593Smuzhiyun
mlx4_en_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1988*4882a593Smuzhiyun static int mlx4_en_get_tunable(struct net_device *dev,
1989*4882a593Smuzhiyun const struct ethtool_tunable *tuna,
1990*4882a593Smuzhiyun void *data)
1991*4882a593Smuzhiyun {
1992*4882a593Smuzhiyun const struct mlx4_en_priv *priv = netdev_priv(dev);
1993*4882a593Smuzhiyun int ret = 0;
1994*4882a593Smuzhiyun
1995*4882a593Smuzhiyun switch (tuna->id) {
1996*4882a593Smuzhiyun case ETHTOOL_TX_COPYBREAK:
1997*4882a593Smuzhiyun *(u32 *)data = priv->prof->inline_thold;
1998*4882a593Smuzhiyun break;
1999*4882a593Smuzhiyun default:
2000*4882a593Smuzhiyun ret = -EINVAL;
2001*4882a593Smuzhiyun break;
2002*4882a593Smuzhiyun }
2003*4882a593Smuzhiyun
2004*4882a593Smuzhiyun return ret;
2005*4882a593Smuzhiyun }
2006*4882a593Smuzhiyun
mlx4_en_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)2007*4882a593Smuzhiyun static int mlx4_en_set_tunable(struct net_device *dev,
2008*4882a593Smuzhiyun const struct ethtool_tunable *tuna,
2009*4882a593Smuzhiyun const void *data)
2010*4882a593Smuzhiyun {
2011*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2012*4882a593Smuzhiyun int val, ret = 0;
2013*4882a593Smuzhiyun
2014*4882a593Smuzhiyun switch (tuna->id) {
2015*4882a593Smuzhiyun case ETHTOOL_TX_COPYBREAK:
2016*4882a593Smuzhiyun val = *(u32 *)data;
2017*4882a593Smuzhiyun if (val < MIN_PKT_LEN || val > MAX_INLINE)
2018*4882a593Smuzhiyun ret = -EINVAL;
2019*4882a593Smuzhiyun else
2020*4882a593Smuzhiyun priv->prof->inline_thold = val;
2021*4882a593Smuzhiyun break;
2022*4882a593Smuzhiyun default:
2023*4882a593Smuzhiyun ret = -EINVAL;
2024*4882a593Smuzhiyun break;
2025*4882a593Smuzhiyun }
2026*4882a593Smuzhiyun
2027*4882a593Smuzhiyun return ret;
2028*4882a593Smuzhiyun }
2029*4882a593Smuzhiyun
mlx4_en_get_module_info(struct net_device * dev,struct ethtool_modinfo * modinfo)2030*4882a593Smuzhiyun static int mlx4_en_get_module_info(struct net_device *dev,
2031*4882a593Smuzhiyun struct ethtool_modinfo *modinfo)
2032*4882a593Smuzhiyun {
2033*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2034*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2035*4882a593Smuzhiyun int ret;
2036*4882a593Smuzhiyun u8 data[4];
2037*4882a593Smuzhiyun
2038*4882a593Smuzhiyun /* Read first 2 bytes to get Module & REV ID */
2039*4882a593Smuzhiyun ret = mlx4_get_module_info(mdev->dev, priv->port,
2040*4882a593Smuzhiyun 0/*offset*/, 2/*size*/, data);
2041*4882a593Smuzhiyun if (ret < 2)
2042*4882a593Smuzhiyun return -EIO;
2043*4882a593Smuzhiyun
2044*4882a593Smuzhiyun switch (data[0] /* identifier */) {
2045*4882a593Smuzhiyun case MLX4_MODULE_ID_QSFP:
2046*4882a593Smuzhiyun modinfo->type = ETH_MODULE_SFF_8436;
2047*4882a593Smuzhiyun modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2048*4882a593Smuzhiyun break;
2049*4882a593Smuzhiyun case MLX4_MODULE_ID_QSFP_PLUS:
2050*4882a593Smuzhiyun if (data[1] >= 0x3) { /* revision id */
2051*4882a593Smuzhiyun modinfo->type = ETH_MODULE_SFF_8636;
2052*4882a593Smuzhiyun modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2053*4882a593Smuzhiyun } else {
2054*4882a593Smuzhiyun modinfo->type = ETH_MODULE_SFF_8436;
2055*4882a593Smuzhiyun modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2056*4882a593Smuzhiyun }
2057*4882a593Smuzhiyun break;
2058*4882a593Smuzhiyun case MLX4_MODULE_ID_QSFP28:
2059*4882a593Smuzhiyun modinfo->type = ETH_MODULE_SFF_8636;
2060*4882a593Smuzhiyun modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2061*4882a593Smuzhiyun break;
2062*4882a593Smuzhiyun case MLX4_MODULE_ID_SFP:
2063*4882a593Smuzhiyun modinfo->type = ETH_MODULE_SFF_8472;
2064*4882a593Smuzhiyun modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2065*4882a593Smuzhiyun break;
2066*4882a593Smuzhiyun default:
2067*4882a593Smuzhiyun return -EINVAL;
2068*4882a593Smuzhiyun }
2069*4882a593Smuzhiyun
2070*4882a593Smuzhiyun return 0;
2071*4882a593Smuzhiyun }
2072*4882a593Smuzhiyun
mlx4_en_get_module_eeprom(struct net_device * dev,struct ethtool_eeprom * ee,u8 * data)2073*4882a593Smuzhiyun static int mlx4_en_get_module_eeprom(struct net_device *dev,
2074*4882a593Smuzhiyun struct ethtool_eeprom *ee,
2075*4882a593Smuzhiyun u8 *data)
2076*4882a593Smuzhiyun {
2077*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2078*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2079*4882a593Smuzhiyun int offset = ee->offset;
2080*4882a593Smuzhiyun int i = 0, ret;
2081*4882a593Smuzhiyun
2082*4882a593Smuzhiyun if (ee->len == 0)
2083*4882a593Smuzhiyun return -EINVAL;
2084*4882a593Smuzhiyun
2085*4882a593Smuzhiyun memset(data, 0, ee->len);
2086*4882a593Smuzhiyun
2087*4882a593Smuzhiyun while (i < ee->len) {
2088*4882a593Smuzhiyun en_dbg(DRV, priv,
2089*4882a593Smuzhiyun "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
2090*4882a593Smuzhiyun i, offset, ee->len - i);
2091*4882a593Smuzhiyun
2092*4882a593Smuzhiyun ret = mlx4_get_module_info(mdev->dev, priv->port,
2093*4882a593Smuzhiyun offset, ee->len - i, data + i);
2094*4882a593Smuzhiyun
2095*4882a593Smuzhiyun if (!ret) /* Done reading */
2096*4882a593Smuzhiyun return 0;
2097*4882a593Smuzhiyun
2098*4882a593Smuzhiyun if (ret < 0) {
2099*4882a593Smuzhiyun en_err(priv,
2100*4882a593Smuzhiyun "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
2101*4882a593Smuzhiyun i, offset, ee->len - i, ret);
2102*4882a593Smuzhiyun return ret;
2103*4882a593Smuzhiyun }
2104*4882a593Smuzhiyun
2105*4882a593Smuzhiyun i += ret;
2106*4882a593Smuzhiyun offset += ret;
2107*4882a593Smuzhiyun }
2108*4882a593Smuzhiyun return 0;
2109*4882a593Smuzhiyun }
2110*4882a593Smuzhiyun
mlx4_en_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)2111*4882a593Smuzhiyun static int mlx4_en_set_phys_id(struct net_device *dev,
2112*4882a593Smuzhiyun enum ethtool_phys_id_state state)
2113*4882a593Smuzhiyun {
2114*4882a593Smuzhiyun int err;
2115*4882a593Smuzhiyun u16 beacon_duration;
2116*4882a593Smuzhiyun struct mlx4_en_priv *priv = netdev_priv(dev);
2117*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
2118*4882a593Smuzhiyun
2119*4882a593Smuzhiyun if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
2120*4882a593Smuzhiyun return -EOPNOTSUPP;
2121*4882a593Smuzhiyun
2122*4882a593Smuzhiyun switch (state) {
2123*4882a593Smuzhiyun case ETHTOOL_ID_ACTIVE:
2124*4882a593Smuzhiyun beacon_duration = PORT_BEACON_MAX_LIMIT;
2125*4882a593Smuzhiyun break;
2126*4882a593Smuzhiyun case ETHTOOL_ID_INACTIVE:
2127*4882a593Smuzhiyun beacon_duration = 0;
2128*4882a593Smuzhiyun break;
2129*4882a593Smuzhiyun default:
2130*4882a593Smuzhiyun return -EOPNOTSUPP;
2131*4882a593Smuzhiyun }
2132*4882a593Smuzhiyun
2133*4882a593Smuzhiyun err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
2134*4882a593Smuzhiyun return err;
2135*4882a593Smuzhiyun }
2136*4882a593Smuzhiyun
2137*4882a593Smuzhiyun const struct ethtool_ops mlx4_en_ethtool_ops = {
2138*4882a593Smuzhiyun .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2139*4882a593Smuzhiyun ETHTOOL_COALESCE_MAX_FRAMES |
2140*4882a593Smuzhiyun ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ |
2141*4882a593Smuzhiyun ETHTOOL_COALESCE_PKT_RATE_RX_USECS,
2142*4882a593Smuzhiyun .get_drvinfo = mlx4_en_get_drvinfo,
2143*4882a593Smuzhiyun .get_link_ksettings = mlx4_en_get_link_ksettings,
2144*4882a593Smuzhiyun .set_link_ksettings = mlx4_en_set_link_ksettings,
2145*4882a593Smuzhiyun .get_link = ethtool_op_get_link,
2146*4882a593Smuzhiyun .get_strings = mlx4_en_get_strings,
2147*4882a593Smuzhiyun .get_sset_count = mlx4_en_get_sset_count,
2148*4882a593Smuzhiyun .get_ethtool_stats = mlx4_en_get_ethtool_stats,
2149*4882a593Smuzhiyun .self_test = mlx4_en_self_test,
2150*4882a593Smuzhiyun .set_phys_id = mlx4_en_set_phys_id,
2151*4882a593Smuzhiyun .get_wol = mlx4_en_get_wol,
2152*4882a593Smuzhiyun .set_wol = mlx4_en_set_wol,
2153*4882a593Smuzhiyun .get_msglevel = mlx4_en_get_msglevel,
2154*4882a593Smuzhiyun .set_msglevel = mlx4_en_set_msglevel,
2155*4882a593Smuzhiyun .get_coalesce = mlx4_en_get_coalesce,
2156*4882a593Smuzhiyun .set_coalesce = mlx4_en_set_coalesce,
2157*4882a593Smuzhiyun .get_pause_stats = mlx4_en_get_pause_stats,
2158*4882a593Smuzhiyun .get_pauseparam = mlx4_en_get_pauseparam,
2159*4882a593Smuzhiyun .set_pauseparam = mlx4_en_set_pauseparam,
2160*4882a593Smuzhiyun .get_ringparam = mlx4_en_get_ringparam,
2161*4882a593Smuzhiyun .set_ringparam = mlx4_en_set_ringparam,
2162*4882a593Smuzhiyun .get_rxnfc = mlx4_en_get_rxnfc,
2163*4882a593Smuzhiyun .set_rxnfc = mlx4_en_set_rxnfc,
2164*4882a593Smuzhiyun .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
2165*4882a593Smuzhiyun .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
2166*4882a593Smuzhiyun .get_rxfh = mlx4_en_get_rxfh,
2167*4882a593Smuzhiyun .set_rxfh = mlx4_en_set_rxfh,
2168*4882a593Smuzhiyun .get_channels = mlx4_en_get_channels,
2169*4882a593Smuzhiyun .set_channels = mlx4_en_set_channels,
2170*4882a593Smuzhiyun .get_ts_info = mlx4_en_get_ts_info,
2171*4882a593Smuzhiyun .set_priv_flags = mlx4_en_set_priv_flags,
2172*4882a593Smuzhiyun .get_priv_flags = mlx4_en_get_priv_flags,
2173*4882a593Smuzhiyun .get_tunable = mlx4_en_get_tunable,
2174*4882a593Smuzhiyun .set_tunable = mlx4_en_set_tunable,
2175*4882a593Smuzhiyun .get_module_info = mlx4_en_get_module_info,
2176*4882a593Smuzhiyun .get_module_eeprom = mlx4_en_get_module_eeprom
2177*4882a593Smuzhiyun };
2178*4882a593Smuzhiyun
2179*4882a593Smuzhiyun
2180*4882a593Smuzhiyun
2181*4882a593Smuzhiyun
2182*4882a593Smuzhiyun
2183