1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <linux/mlx4/cq.h>
35*4882a593Smuzhiyun #include <linux/mlx4/qp.h>
36*4882a593Smuzhiyun #include <linux/mlx4/cmd.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include "mlx4_en.h"
39*4882a593Smuzhiyun
mlx4_en_cq_event(struct mlx4_cq * cq,enum mlx4_event event)40*4882a593Smuzhiyun static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun return;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun
mlx4_en_create_cq(struct mlx4_en_priv * priv,struct mlx4_en_cq ** pcq,int entries,int ring,enum cq_type mode,int node)46*4882a593Smuzhiyun int mlx4_en_create_cq(struct mlx4_en_priv *priv,
47*4882a593Smuzhiyun struct mlx4_en_cq **pcq,
48*4882a593Smuzhiyun int entries, int ring, enum cq_type mode,
49*4882a593Smuzhiyun int node)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
52*4882a593Smuzhiyun struct mlx4_en_cq *cq;
53*4882a593Smuzhiyun int err;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun cq = kzalloc_node(sizeof(*cq), GFP_KERNEL, node);
56*4882a593Smuzhiyun if (!cq) {
57*4882a593Smuzhiyun en_err(priv, "Failed to allocate CQ structure\n");
58*4882a593Smuzhiyun return -ENOMEM;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun cq->size = entries;
62*4882a593Smuzhiyun cq->buf_size = cq->size * mdev->dev->caps.cqe_size;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun cq->ring = ring;
65*4882a593Smuzhiyun cq->type = mode;
66*4882a593Smuzhiyun cq->vector = mdev->dev->caps.num_comp_vectors;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Allocate HW buffers on provided NUMA node.
69*4882a593Smuzhiyun * dev->numa_node is used in mtt range allocation flow.
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun set_dev_node(&mdev->dev->persist->pdev->dev, node);
72*4882a593Smuzhiyun err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres,
73*4882a593Smuzhiyun cq->buf_size);
74*4882a593Smuzhiyun set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
75*4882a593Smuzhiyun if (err)
76*4882a593Smuzhiyun goto err_cq;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun cq->buf = (struct mlx4_cqe *)cq->wqres.buf.direct.buf;
79*4882a593Smuzhiyun *pcq = cq;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun err_cq:
84*4882a593Smuzhiyun kfree(cq);
85*4882a593Smuzhiyun *pcq = NULL;
86*4882a593Smuzhiyun return err;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
mlx4_en_activate_cq(struct mlx4_en_priv * priv,struct mlx4_en_cq * cq,int cq_idx)89*4882a593Smuzhiyun int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
90*4882a593Smuzhiyun int cq_idx)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
93*4882a593Smuzhiyun int err = 0;
94*4882a593Smuzhiyun int timestamp_en = 0;
95*4882a593Smuzhiyun bool assigned_eq = false;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun cq->dev = mdev->pndev[priv->port];
98*4882a593Smuzhiyun cq->mcq.set_ci_db = cq->wqres.db.db;
99*4882a593Smuzhiyun cq->mcq.arm_db = cq->wqres.db.db + 1;
100*4882a593Smuzhiyun *cq->mcq.set_ci_db = 0;
101*4882a593Smuzhiyun *cq->mcq.arm_db = 0;
102*4882a593Smuzhiyun memset(cq->buf, 0, cq->buf_size);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (cq->type == RX) {
105*4882a593Smuzhiyun if (!mlx4_is_eq_vector_valid(mdev->dev, priv->port,
106*4882a593Smuzhiyun cq->vector)) {
107*4882a593Smuzhiyun cq->vector = cpumask_first(priv->rx_ring[cq->ring]->affinity_mask);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun err = mlx4_assign_eq(mdev->dev, priv->port,
110*4882a593Smuzhiyun &cq->vector);
111*4882a593Smuzhiyun if (err) {
112*4882a593Smuzhiyun mlx4_err(mdev, "Failed assigning an EQ to CQ vector %d\n",
113*4882a593Smuzhiyun cq->vector);
114*4882a593Smuzhiyun goto free_eq;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun assigned_eq = true;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun cq->irq_desc =
121*4882a593Smuzhiyun irq_to_desc(mlx4_eq_get_irq(mdev->dev,
122*4882a593Smuzhiyun cq->vector));
123*4882a593Smuzhiyun } else {
124*4882a593Smuzhiyun /* For TX we use the same irq per
125*4882a593Smuzhiyun ring we assigned for the RX */
126*4882a593Smuzhiyun struct mlx4_en_cq *rx_cq;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun cq_idx = cq_idx % priv->rx_ring_num;
129*4882a593Smuzhiyun rx_cq = priv->rx_cq[cq_idx];
130*4882a593Smuzhiyun cq->vector = rx_cq->vector;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun if (cq->type == RX)
134*4882a593Smuzhiyun cq->size = priv->rx_ring[cq->ring]->actual_size;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if ((cq->type != RX && priv->hwtstamp_config.tx_type) ||
137*4882a593Smuzhiyun (cq->type == RX && priv->hwtstamp_config.rx_filter))
138*4882a593Smuzhiyun timestamp_en = 1;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun cq->mcq.usage = MLX4_RES_USAGE_DRIVER;
141*4882a593Smuzhiyun err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt,
142*4882a593Smuzhiyun &mdev->priv_uar, cq->wqres.db.dma, &cq->mcq,
143*4882a593Smuzhiyun cq->vector, 0, timestamp_en, &cq->wqres.buf, false);
144*4882a593Smuzhiyun if (err)
145*4882a593Smuzhiyun goto free_eq;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun cq->mcq.event = mlx4_en_cq_event;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun switch (cq->type) {
150*4882a593Smuzhiyun case TX:
151*4882a593Smuzhiyun cq->mcq.comp = mlx4_en_tx_irq;
152*4882a593Smuzhiyun netif_tx_napi_add(cq->dev, &cq->napi, mlx4_en_poll_tx_cq,
153*4882a593Smuzhiyun NAPI_POLL_WEIGHT);
154*4882a593Smuzhiyun napi_enable(&cq->napi);
155*4882a593Smuzhiyun break;
156*4882a593Smuzhiyun case RX:
157*4882a593Smuzhiyun cq->mcq.comp = mlx4_en_rx_irq;
158*4882a593Smuzhiyun netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq, 64);
159*4882a593Smuzhiyun napi_enable(&cq->napi);
160*4882a593Smuzhiyun break;
161*4882a593Smuzhiyun case TX_XDP:
162*4882a593Smuzhiyun /* nothing regarding napi, it's shared with rx ring */
163*4882a593Smuzhiyun cq->xdp_busy = false;
164*4882a593Smuzhiyun break;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return 0;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun free_eq:
170*4882a593Smuzhiyun if (assigned_eq)
171*4882a593Smuzhiyun mlx4_release_eq(mdev->dev, cq->vector);
172*4882a593Smuzhiyun cq->vector = mdev->dev->caps.num_comp_vectors;
173*4882a593Smuzhiyun return err;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
mlx4_en_destroy_cq(struct mlx4_en_priv * priv,struct mlx4_en_cq ** pcq)176*4882a593Smuzhiyun void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun struct mlx4_en_dev *mdev = priv->mdev;
179*4882a593Smuzhiyun struct mlx4_en_cq *cq = *pcq;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
182*4882a593Smuzhiyun if (mlx4_is_eq_vector_valid(mdev->dev, priv->port, cq->vector) &&
183*4882a593Smuzhiyun cq->type == RX)
184*4882a593Smuzhiyun mlx4_release_eq(priv->mdev->dev, cq->vector);
185*4882a593Smuzhiyun cq->vector = 0;
186*4882a593Smuzhiyun cq->buf_size = 0;
187*4882a593Smuzhiyun cq->buf = NULL;
188*4882a593Smuzhiyun kfree(cq);
189*4882a593Smuzhiyun *pcq = NULL;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
mlx4_en_deactivate_cq(struct mlx4_en_priv * priv,struct mlx4_en_cq * cq)192*4882a593Smuzhiyun void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun if (cq->type != TX_XDP) {
195*4882a593Smuzhiyun napi_disable(&cq->napi);
196*4882a593Smuzhiyun netif_napi_del(&cq->napi);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun mlx4_cq_free(priv->mdev->dev, &cq->mcq);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /* Set rx cq moderation parameters */
mlx4_en_set_cq_moder(struct mlx4_en_priv * priv,struct mlx4_en_cq * cq)203*4882a593Smuzhiyun int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun return mlx4_cq_modify(priv->mdev->dev, &cq->mcq,
206*4882a593Smuzhiyun cq->moder_cnt, cq->moder_time);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
mlx4_en_arm_cq(struct mlx4_en_priv * priv,struct mlx4_en_cq * cq)209*4882a593Smuzhiyun void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map,
212*4882a593Smuzhiyun &priv->mdev->uar_lock);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun
216