1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2018-2019 MediaTek Inc.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /* A library for MediaTek SGMII circuit
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Sean Wang <sean.wang@mediatek.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "mtk_eth_soc.h"
15*4882a593Smuzhiyun
mtk_sgmii_init(struct mtk_sgmii * ss,struct device_node * r,u32 ana_rgc3)16*4882a593Smuzhiyun int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun struct device_node *np;
19*4882a593Smuzhiyun int i;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun ss->ana_rgc3 = ana_rgc3;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun for (i = 0; i < MTK_MAX_DEVS; i++) {
24*4882a593Smuzhiyun np = of_parse_phandle(r, "mediatek,sgmiisys", i);
25*4882a593Smuzhiyun if (!np)
26*4882a593Smuzhiyun break;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun ss->regmap[i] = syscon_node_to_regmap(np);
29*4882a593Smuzhiyun of_node_put(np);
30*4882a593Smuzhiyun if (IS_ERR(ss->regmap[i]))
31*4882a593Smuzhiyun return PTR_ERR(ss->regmap[i]);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return 0;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
mtk_sgmii_setup_mode_an(struct mtk_sgmii * ss,int id)37*4882a593Smuzhiyun int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun unsigned int val;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun if (!ss->regmap[id])
42*4882a593Smuzhiyun return -EINVAL;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Setup the link timer and QPHY power up inside SGMIISYS */
45*4882a593Smuzhiyun regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER,
46*4882a593Smuzhiyun SGMII_LINK_TIMER_DEFAULT);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
49*4882a593Smuzhiyun val |= SGMII_REMOTE_FAULT_DIS;
50*4882a593Smuzhiyun regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
53*4882a593Smuzhiyun val |= SGMII_AN_RESTART;
54*4882a593Smuzhiyun regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
57*4882a593Smuzhiyun val &= ~SGMII_PHYA_PWD;
58*4882a593Smuzhiyun regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
mtk_sgmii_setup_mode_force(struct mtk_sgmii * ss,int id,const struct phylink_link_state * state)63*4882a593Smuzhiyun int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
64*4882a593Smuzhiyun const struct phylink_link_state *state)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun unsigned int val;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (!ss->regmap[id])
69*4882a593Smuzhiyun return -EINVAL;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
72*4882a593Smuzhiyun val &= ~RG_PHY_SPEED_MASK;
73*4882a593Smuzhiyun if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
74*4882a593Smuzhiyun val |= RG_PHY_SPEED_3_125G;
75*4882a593Smuzhiyun regmap_write(ss->regmap[id], ss->ana_rgc3, val);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Disable SGMII AN */
78*4882a593Smuzhiyun regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
79*4882a593Smuzhiyun val &= ~SGMII_AN_ENABLE;
80*4882a593Smuzhiyun regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* SGMII force mode setting */
83*4882a593Smuzhiyun regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
84*4882a593Smuzhiyun val &= ~SGMII_IF_MODE_MASK;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun switch (state->speed) {
87*4882a593Smuzhiyun case SPEED_10:
88*4882a593Smuzhiyun val |= SGMII_SPEED_10;
89*4882a593Smuzhiyun break;
90*4882a593Smuzhiyun case SPEED_100:
91*4882a593Smuzhiyun val |= SGMII_SPEED_100;
92*4882a593Smuzhiyun break;
93*4882a593Smuzhiyun case SPEED_2500:
94*4882a593Smuzhiyun case SPEED_1000:
95*4882a593Smuzhiyun val |= SGMII_SPEED_1000;
96*4882a593Smuzhiyun break;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun if (state->duplex == DUPLEX_FULL)
100*4882a593Smuzhiyun val |= SGMII_DUPLEX_FULL;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* Release PHYA power down state */
105*4882a593Smuzhiyun regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
106*4882a593Smuzhiyun val &= ~SGMII_PHYA_PWD;
107*4882a593Smuzhiyun regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
mtk_sgmii_restart_an(struct mtk_eth * eth,int mac_id)112*4882a593Smuzhiyun void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun struct mtk_sgmii *ss = eth->sgmii;
115*4882a593Smuzhiyun unsigned int val, sid;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Decide how GMAC and SGMIISYS be mapped */
118*4882a593Smuzhiyun sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
119*4882a593Smuzhiyun 0 : mac_id;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun if (!ss->regmap[sid])
122*4882a593Smuzhiyun return;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val);
125*4882a593Smuzhiyun val |= SGMII_AN_RESTART;
126*4882a593Smuzhiyun regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val);
127*4882a593Smuzhiyun }
128