1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9 #include <linux/of_device.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/regmap.h>
14 #include <linux/clk.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/if_vlan.h>
17 #include <linux/reset.h>
18 #include <linux/tcp.h>
19 #include <linux/interrupt.h>
20 #include <linux/pinctrl/devinfo.h>
21 #include <linux/phylink.h>
22
23 #include "mtk_eth_soc.h"
24
25 static int mtk_msg_level = -1;
26 module_param_named(msg_level, mtk_msg_level, int, 0);
27 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
28
29 #define MTK_ETHTOOL_STAT(x) { #x, \
30 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
31
32 /* strings used by ethtool */
33 static const struct mtk_ethtool_stats {
34 char str[ETH_GSTRING_LEN];
35 u32 offset;
36 } mtk_ethtool_stats[] = {
37 MTK_ETHTOOL_STAT(tx_bytes),
38 MTK_ETHTOOL_STAT(tx_packets),
39 MTK_ETHTOOL_STAT(tx_skip),
40 MTK_ETHTOOL_STAT(tx_collisions),
41 MTK_ETHTOOL_STAT(rx_bytes),
42 MTK_ETHTOOL_STAT(rx_packets),
43 MTK_ETHTOOL_STAT(rx_overflow),
44 MTK_ETHTOOL_STAT(rx_fcs_errors),
45 MTK_ETHTOOL_STAT(rx_short_errors),
46 MTK_ETHTOOL_STAT(rx_long_errors),
47 MTK_ETHTOOL_STAT(rx_checksum_errors),
48 MTK_ETHTOOL_STAT(rx_flow_control_packets),
49 };
50
51 static const char * const mtk_clks_source_name[] = {
52 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
53 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
54 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
55 "sgmii_ck", "eth2pll",
56 };
57
mtk_w32(struct mtk_eth * eth,u32 val,unsigned reg)58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
59 {
60 __raw_writel(val, eth->base + reg);
61 }
62
mtk_r32(struct mtk_eth * eth,unsigned reg)63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
64 {
65 return __raw_readl(eth->base + reg);
66 }
67
mtk_m32(struct mtk_eth * eth,u32 mask,u32 set,unsigned reg)68 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
69 {
70 u32 val;
71
72 val = mtk_r32(eth, reg);
73 val &= ~mask;
74 val |= set;
75 mtk_w32(eth, val, reg);
76 return reg;
77 }
78
mtk_mdio_busy_wait(struct mtk_eth * eth)79 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
80 {
81 unsigned long t_start = jiffies;
82
83 while (1) {
84 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
85 return 0;
86 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
87 break;
88 usleep_range(10, 20);
89 }
90
91 dev_err(eth->dev, "mdio: MDIO timeout\n");
92 return -1;
93 }
94
_mtk_mdio_write(struct mtk_eth * eth,u32 phy_addr,u32 phy_register,u32 write_data)95 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
96 u32 phy_register, u32 write_data)
97 {
98 if (mtk_mdio_busy_wait(eth))
99 return -1;
100
101 write_data &= 0xffff;
102
103 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
104 (phy_register << PHY_IAC_REG_SHIFT) |
105 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
106 MTK_PHY_IAC);
107
108 if (mtk_mdio_busy_wait(eth))
109 return -1;
110
111 return 0;
112 }
113
_mtk_mdio_read(struct mtk_eth * eth,int phy_addr,int phy_reg)114 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
115 {
116 u32 d;
117
118 if (mtk_mdio_busy_wait(eth))
119 return 0xffff;
120
121 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
122 (phy_reg << PHY_IAC_REG_SHIFT) |
123 (phy_addr << PHY_IAC_ADDR_SHIFT),
124 MTK_PHY_IAC);
125
126 if (mtk_mdio_busy_wait(eth))
127 return 0xffff;
128
129 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
130
131 return d;
132 }
133
mtk_mdio_write(struct mii_bus * bus,int phy_addr,int phy_reg,u16 val)134 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
135 int phy_reg, u16 val)
136 {
137 struct mtk_eth *eth = bus->priv;
138
139 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
140 }
141
mtk_mdio_read(struct mii_bus * bus,int phy_addr,int phy_reg)142 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
143 {
144 struct mtk_eth *eth = bus->priv;
145
146 return _mtk_mdio_read(eth, phy_addr, phy_reg);
147 }
148
mt7621_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)149 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
150 phy_interface_t interface)
151 {
152 u32 val;
153
154 /* Check DDR memory type.
155 * Currently TRGMII mode with DDR2 memory is not supported.
156 */
157 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
158 if (interface == PHY_INTERFACE_MODE_TRGMII &&
159 val & SYSCFG_DRAM_TYPE_DDR2) {
160 dev_err(eth->dev,
161 "TRGMII mode with DDR2 memory is not supported!\n");
162 return -EOPNOTSUPP;
163 }
164
165 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
166 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
167
168 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
169 ETHSYS_TRGMII_MT7621_MASK, val);
170
171 return 0;
172 }
173
mtk_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface,int speed)174 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
175 phy_interface_t interface, int speed)
176 {
177 u32 val;
178 int ret;
179
180 if (interface == PHY_INTERFACE_MODE_TRGMII) {
181 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
182 val = 500000000;
183 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
184 if (ret)
185 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
186 return;
187 }
188
189 val = (speed == SPEED_1000) ?
190 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
191 mtk_w32(eth, val, INTF_MODE);
192
193 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
194 ETHSYS_TRGMII_CLK_SEL362_5,
195 ETHSYS_TRGMII_CLK_SEL362_5);
196
197 val = (speed == SPEED_1000) ? 250000000 : 500000000;
198 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
199 if (ret)
200 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
201
202 val = (speed == SPEED_1000) ?
203 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
204 mtk_w32(eth, val, TRGMII_RCK_CTRL);
205
206 val = (speed == SPEED_1000) ?
207 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
208 mtk_w32(eth, val, TRGMII_TCK_CTRL);
209 }
210
mtk_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)211 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
212 const struct phylink_link_state *state)
213 {
214 struct mtk_mac *mac = container_of(config, struct mtk_mac,
215 phylink_config);
216 struct mtk_eth *eth = mac->hw;
217 u32 mcr_cur, mcr_new, sid, i;
218 int val, ge_mode, err = 0;
219
220 /* MT76x8 has no hardware settings between for the MAC */
221 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
222 mac->interface != state->interface) {
223 /* Setup soc pin functions */
224 switch (state->interface) {
225 case PHY_INTERFACE_MODE_TRGMII:
226 if (mac->id)
227 goto err_phy;
228 if (!MTK_HAS_CAPS(mac->hw->soc->caps,
229 MTK_GMAC1_TRGMII))
230 goto err_phy;
231 fallthrough;
232 case PHY_INTERFACE_MODE_RGMII_TXID:
233 case PHY_INTERFACE_MODE_RGMII_RXID:
234 case PHY_INTERFACE_MODE_RGMII_ID:
235 case PHY_INTERFACE_MODE_RGMII:
236 case PHY_INTERFACE_MODE_MII:
237 case PHY_INTERFACE_MODE_REVMII:
238 case PHY_INTERFACE_MODE_RMII:
239 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
240 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
241 if (err)
242 goto init_err;
243 }
244 break;
245 case PHY_INTERFACE_MODE_1000BASEX:
246 case PHY_INTERFACE_MODE_2500BASEX:
247 case PHY_INTERFACE_MODE_SGMII:
248 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
249 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
250 if (err)
251 goto init_err;
252 }
253 break;
254 case PHY_INTERFACE_MODE_GMII:
255 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
256 err = mtk_gmac_gephy_path_setup(eth, mac->id);
257 if (err)
258 goto init_err;
259 }
260 break;
261 default:
262 goto err_phy;
263 }
264
265 /* Setup clock for 1st gmac */
266 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
267 !phy_interface_mode_is_8023z(state->interface) &&
268 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
269 if (MTK_HAS_CAPS(mac->hw->soc->caps,
270 MTK_TRGMII_MT7621_CLK)) {
271 if (mt7621_gmac0_rgmii_adjust(mac->hw,
272 state->interface))
273 goto err_phy;
274 } else {
275 mtk_gmac0_rgmii_adjust(mac->hw,
276 state->interface,
277 state->speed);
278
279 /* mt7623_pad_clk_setup */
280 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
281 mtk_w32(mac->hw,
282 TD_DM_DRVP(8) | TD_DM_DRVN(8),
283 TRGMII_TD_ODT(i));
284
285 /* Assert/release MT7623 RXC reset */
286 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
287 TRGMII_RCK_CTRL);
288 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
289 }
290 }
291
292 ge_mode = 0;
293 switch (state->interface) {
294 case PHY_INTERFACE_MODE_MII:
295 case PHY_INTERFACE_MODE_GMII:
296 ge_mode = 1;
297 break;
298 case PHY_INTERFACE_MODE_REVMII:
299 ge_mode = 2;
300 break;
301 case PHY_INTERFACE_MODE_RMII:
302 if (mac->id)
303 goto err_phy;
304 ge_mode = 3;
305 break;
306 default:
307 break;
308 }
309
310 /* put the gmac into the right mode */
311 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
312 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
313 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
314 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
315
316 mac->interface = state->interface;
317 }
318
319 /* SGMII */
320 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
321 phy_interface_mode_is_8023z(state->interface)) {
322 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
323 * being setup done.
324 */
325 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
326
327 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
328 SYSCFG0_SGMII_MASK,
329 ~(u32)SYSCFG0_SGMII_MASK);
330
331 /* Decide how GMAC and SGMIISYS be mapped */
332 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
333 0 : mac->id;
334
335 /* Setup SGMIISYS with the determined property */
336 if (state->interface != PHY_INTERFACE_MODE_SGMII)
337 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid,
338 state);
339 else if (phylink_autoneg_inband(mode))
340 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
341
342 if (err)
343 goto init_err;
344
345 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
346 SYSCFG0_SGMII_MASK, val);
347 } else if (phylink_autoneg_inband(mode)) {
348 dev_err(eth->dev,
349 "In-band mode not supported in non SGMII mode!\n");
350 return;
351 }
352
353 /* Setup gmac */
354 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
355 mcr_new = mcr_cur;
356 mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
357 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
358
359 /* Only update control register when needed! */
360 if (mcr_new != mcr_cur)
361 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
362
363 return;
364
365 err_phy:
366 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
367 mac->id, phy_modes(state->interface));
368 return;
369
370 init_err:
371 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
372 mac->id, phy_modes(state->interface), err);
373 }
374
mtk_mac_pcs_get_state(struct phylink_config * config,struct phylink_link_state * state)375 static void mtk_mac_pcs_get_state(struct phylink_config *config,
376 struct phylink_link_state *state)
377 {
378 struct mtk_mac *mac = container_of(config, struct mtk_mac,
379 phylink_config);
380 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
381
382 state->link = (pmsr & MAC_MSR_LINK);
383 state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
384
385 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
386 case 0:
387 state->speed = SPEED_10;
388 break;
389 case MAC_MSR_SPEED_100:
390 state->speed = SPEED_100;
391 break;
392 case MAC_MSR_SPEED_1000:
393 state->speed = SPEED_1000;
394 break;
395 default:
396 state->speed = SPEED_UNKNOWN;
397 break;
398 }
399
400 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
401 if (pmsr & MAC_MSR_RX_FC)
402 state->pause |= MLO_PAUSE_RX;
403 if (pmsr & MAC_MSR_TX_FC)
404 state->pause |= MLO_PAUSE_TX;
405 }
406
mtk_mac_an_restart(struct phylink_config * config)407 static void mtk_mac_an_restart(struct phylink_config *config)
408 {
409 struct mtk_mac *mac = container_of(config, struct mtk_mac,
410 phylink_config);
411
412 mtk_sgmii_restart_an(mac->hw, mac->id);
413 }
414
mtk_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)415 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
416 phy_interface_t interface)
417 {
418 struct mtk_mac *mac = container_of(config, struct mtk_mac,
419 phylink_config);
420 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
421
422 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
423 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
424 }
425
mtk_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)426 static void mtk_mac_link_up(struct phylink_config *config,
427 struct phy_device *phy,
428 unsigned int mode, phy_interface_t interface,
429 int speed, int duplex, bool tx_pause, bool rx_pause)
430 {
431 struct mtk_mac *mac = container_of(config, struct mtk_mac,
432 phylink_config);
433 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
434
435 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
436 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
437 MAC_MCR_FORCE_RX_FC);
438
439 /* Configure speed */
440 switch (speed) {
441 case SPEED_2500:
442 case SPEED_1000:
443 mcr |= MAC_MCR_SPEED_1000;
444 break;
445 case SPEED_100:
446 mcr |= MAC_MCR_SPEED_100;
447 break;
448 }
449
450 /* Configure duplex */
451 if (duplex == DUPLEX_FULL)
452 mcr |= MAC_MCR_FORCE_DPX;
453
454 /* Configure pause modes - phylink will avoid these for half duplex */
455 if (tx_pause)
456 mcr |= MAC_MCR_FORCE_TX_FC;
457 if (rx_pause)
458 mcr |= MAC_MCR_FORCE_RX_FC;
459
460 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
461 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
462 }
463
mtk_validate(struct phylink_config * config,unsigned long * supported,struct phylink_link_state * state)464 static void mtk_validate(struct phylink_config *config,
465 unsigned long *supported,
466 struct phylink_link_state *state)
467 {
468 struct mtk_mac *mac = container_of(config, struct mtk_mac,
469 phylink_config);
470 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
471
472 if (state->interface != PHY_INTERFACE_MODE_NA &&
473 state->interface != PHY_INTERFACE_MODE_MII &&
474 state->interface != PHY_INTERFACE_MODE_GMII &&
475 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) &&
476 phy_interface_mode_is_rgmii(state->interface)) &&
477 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) &&
478 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) &&
479 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) &&
480 (state->interface == PHY_INTERFACE_MODE_SGMII ||
481 phy_interface_mode_is_8023z(state->interface)))) {
482 linkmode_zero(supported);
483 return;
484 }
485
486 phylink_set_port_modes(mask);
487 phylink_set(mask, Autoneg);
488
489 switch (state->interface) {
490 case PHY_INTERFACE_MODE_TRGMII:
491 phylink_set(mask, 1000baseT_Full);
492 break;
493 case PHY_INTERFACE_MODE_1000BASEX:
494 case PHY_INTERFACE_MODE_2500BASEX:
495 phylink_set(mask, 1000baseX_Full);
496 phylink_set(mask, 2500baseX_Full);
497 break;
498 case PHY_INTERFACE_MODE_GMII:
499 case PHY_INTERFACE_MODE_RGMII:
500 case PHY_INTERFACE_MODE_RGMII_ID:
501 case PHY_INTERFACE_MODE_RGMII_RXID:
502 case PHY_INTERFACE_MODE_RGMII_TXID:
503 phylink_set(mask, 1000baseT_Half);
504 fallthrough;
505 case PHY_INTERFACE_MODE_SGMII:
506 phylink_set(mask, 1000baseT_Full);
507 phylink_set(mask, 1000baseX_Full);
508 fallthrough;
509 case PHY_INTERFACE_MODE_MII:
510 case PHY_INTERFACE_MODE_RMII:
511 case PHY_INTERFACE_MODE_REVMII:
512 case PHY_INTERFACE_MODE_NA:
513 default:
514 phylink_set(mask, 10baseT_Half);
515 phylink_set(mask, 10baseT_Full);
516 phylink_set(mask, 100baseT_Half);
517 phylink_set(mask, 100baseT_Full);
518 break;
519 }
520
521 if (state->interface == PHY_INTERFACE_MODE_NA) {
522 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
523 phylink_set(mask, 1000baseT_Full);
524 phylink_set(mask, 1000baseX_Full);
525 phylink_set(mask, 2500baseX_Full);
526 }
527 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) {
528 phylink_set(mask, 1000baseT_Full);
529 phylink_set(mask, 1000baseT_Half);
530 phylink_set(mask, 1000baseX_Full);
531 }
532 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) {
533 phylink_set(mask, 1000baseT_Full);
534 phylink_set(mask, 1000baseT_Half);
535 }
536 }
537
538 phylink_set(mask, Pause);
539 phylink_set(mask, Asym_Pause);
540
541 linkmode_and(supported, supported, mask);
542 linkmode_and(state->advertising, state->advertising, mask);
543
544 /* We can only operate at 2500BaseX or 1000BaseX. If requested
545 * to advertise both, only report advertising at 2500BaseX.
546 */
547 phylink_helper_basex_speed(state);
548 }
549
550 static const struct phylink_mac_ops mtk_phylink_ops = {
551 .validate = mtk_validate,
552 .mac_pcs_get_state = mtk_mac_pcs_get_state,
553 .mac_an_restart = mtk_mac_an_restart,
554 .mac_config = mtk_mac_config,
555 .mac_link_down = mtk_mac_link_down,
556 .mac_link_up = mtk_mac_link_up,
557 };
558
mtk_mdio_init(struct mtk_eth * eth)559 static int mtk_mdio_init(struct mtk_eth *eth)
560 {
561 struct device_node *mii_np;
562 int ret;
563
564 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
565 if (!mii_np) {
566 dev_err(eth->dev, "no %s child node found", "mdio-bus");
567 return -ENODEV;
568 }
569
570 if (!of_device_is_available(mii_np)) {
571 ret = -ENODEV;
572 goto err_put_node;
573 }
574
575 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
576 if (!eth->mii_bus) {
577 ret = -ENOMEM;
578 goto err_put_node;
579 }
580
581 eth->mii_bus->name = "mdio";
582 eth->mii_bus->read = mtk_mdio_read;
583 eth->mii_bus->write = mtk_mdio_write;
584 eth->mii_bus->priv = eth;
585 eth->mii_bus->parent = eth->dev;
586
587 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
588 ret = of_mdiobus_register(eth->mii_bus, mii_np);
589
590 err_put_node:
591 of_node_put(mii_np);
592 return ret;
593 }
594
mtk_mdio_cleanup(struct mtk_eth * eth)595 static void mtk_mdio_cleanup(struct mtk_eth *eth)
596 {
597 if (!eth->mii_bus)
598 return;
599
600 mdiobus_unregister(eth->mii_bus);
601 }
602
mtk_tx_irq_disable(struct mtk_eth * eth,u32 mask)603 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
604 {
605 unsigned long flags;
606 u32 val;
607
608 spin_lock_irqsave(ð->tx_irq_lock, flags);
609 val = mtk_r32(eth, eth->tx_int_mask_reg);
610 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);
611 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
612 }
613
mtk_tx_irq_enable(struct mtk_eth * eth,u32 mask)614 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
615 {
616 unsigned long flags;
617 u32 val;
618
619 spin_lock_irqsave(ð->tx_irq_lock, flags);
620 val = mtk_r32(eth, eth->tx_int_mask_reg);
621 mtk_w32(eth, val | mask, eth->tx_int_mask_reg);
622 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
623 }
624
mtk_rx_irq_disable(struct mtk_eth * eth,u32 mask)625 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
626 {
627 unsigned long flags;
628 u32 val;
629
630 spin_lock_irqsave(ð->rx_irq_lock, flags);
631 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
632 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
633 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
634 }
635
mtk_rx_irq_enable(struct mtk_eth * eth,u32 mask)636 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
637 {
638 unsigned long flags;
639 u32 val;
640
641 spin_lock_irqsave(ð->rx_irq_lock, flags);
642 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
643 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
644 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
645 }
646
mtk_set_mac_address(struct net_device * dev,void * p)647 static int mtk_set_mac_address(struct net_device *dev, void *p)
648 {
649 int ret = eth_mac_addr(dev, p);
650 struct mtk_mac *mac = netdev_priv(dev);
651 struct mtk_eth *eth = mac->hw;
652 const char *macaddr = dev->dev_addr;
653
654 if (ret)
655 return ret;
656
657 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
658 return -EBUSY;
659
660 spin_lock_bh(&mac->hw->page_lock);
661 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
662 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
663 MT7628_SDM_MAC_ADRH);
664 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
665 (macaddr[4] << 8) | macaddr[5],
666 MT7628_SDM_MAC_ADRL);
667 } else {
668 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
669 MTK_GDMA_MAC_ADRH(mac->id));
670 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
671 (macaddr[4] << 8) | macaddr[5],
672 MTK_GDMA_MAC_ADRL(mac->id));
673 }
674 spin_unlock_bh(&mac->hw->page_lock);
675
676 return 0;
677 }
678
mtk_stats_update_mac(struct mtk_mac * mac)679 void mtk_stats_update_mac(struct mtk_mac *mac)
680 {
681 struct mtk_hw_stats *hw_stats = mac->hw_stats;
682 struct mtk_eth *eth = mac->hw;
683
684 u64_stats_update_begin(&hw_stats->syncp);
685
686 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
687 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
688 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
689 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
690 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
691 hw_stats->rx_checksum_errors +=
692 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
693 } else {
694 unsigned int offs = hw_stats->reg_offset;
695 u64 stats;
696
697 hw_stats->rx_bytes += mtk_r32(mac->hw,
698 MTK_GDM1_RX_GBCNT_L + offs);
699 stats = mtk_r32(mac->hw, MTK_GDM1_RX_GBCNT_H + offs);
700 if (stats)
701 hw_stats->rx_bytes += (stats << 32);
702 hw_stats->rx_packets +=
703 mtk_r32(mac->hw, MTK_GDM1_RX_GPCNT + offs);
704 hw_stats->rx_overflow +=
705 mtk_r32(mac->hw, MTK_GDM1_RX_OERCNT + offs);
706 hw_stats->rx_fcs_errors +=
707 mtk_r32(mac->hw, MTK_GDM1_RX_FERCNT + offs);
708 hw_stats->rx_short_errors +=
709 mtk_r32(mac->hw, MTK_GDM1_RX_SERCNT + offs);
710 hw_stats->rx_long_errors +=
711 mtk_r32(mac->hw, MTK_GDM1_RX_LENCNT + offs);
712 hw_stats->rx_checksum_errors +=
713 mtk_r32(mac->hw, MTK_GDM1_RX_CERCNT + offs);
714 hw_stats->rx_flow_control_packets +=
715 mtk_r32(mac->hw, MTK_GDM1_RX_FCCNT + offs);
716 hw_stats->tx_skip +=
717 mtk_r32(mac->hw, MTK_GDM1_TX_SKIPCNT + offs);
718 hw_stats->tx_collisions +=
719 mtk_r32(mac->hw, MTK_GDM1_TX_COLCNT + offs);
720 hw_stats->tx_bytes +=
721 mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_L + offs);
722 stats = mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_H + offs);
723 if (stats)
724 hw_stats->tx_bytes += (stats << 32);
725 hw_stats->tx_packets +=
726 mtk_r32(mac->hw, MTK_GDM1_TX_GPCNT + offs);
727 }
728
729 u64_stats_update_end(&hw_stats->syncp);
730 }
731
mtk_stats_update(struct mtk_eth * eth)732 static void mtk_stats_update(struct mtk_eth *eth)
733 {
734 int i;
735
736 for (i = 0; i < MTK_MAC_COUNT; i++) {
737 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
738 continue;
739 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
740 mtk_stats_update_mac(eth->mac[i]);
741 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
742 }
743 }
744 }
745
mtk_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)746 static void mtk_get_stats64(struct net_device *dev,
747 struct rtnl_link_stats64 *storage)
748 {
749 struct mtk_mac *mac = netdev_priv(dev);
750 struct mtk_hw_stats *hw_stats = mac->hw_stats;
751 unsigned int start;
752
753 if (netif_running(dev) && netif_device_present(dev)) {
754 if (spin_trylock_bh(&hw_stats->stats_lock)) {
755 mtk_stats_update_mac(mac);
756 spin_unlock_bh(&hw_stats->stats_lock);
757 }
758 }
759
760 do {
761 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
762 storage->rx_packets = hw_stats->rx_packets;
763 storage->tx_packets = hw_stats->tx_packets;
764 storage->rx_bytes = hw_stats->rx_bytes;
765 storage->tx_bytes = hw_stats->tx_bytes;
766 storage->collisions = hw_stats->tx_collisions;
767 storage->rx_length_errors = hw_stats->rx_short_errors +
768 hw_stats->rx_long_errors;
769 storage->rx_over_errors = hw_stats->rx_overflow;
770 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
771 storage->rx_errors = hw_stats->rx_checksum_errors;
772 storage->tx_aborted_errors = hw_stats->tx_skip;
773 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
774
775 storage->tx_errors = dev->stats.tx_errors;
776 storage->rx_dropped = dev->stats.rx_dropped;
777 storage->tx_dropped = dev->stats.tx_dropped;
778 }
779
mtk_max_frag_size(int mtu)780 static inline int mtk_max_frag_size(int mtu)
781 {
782 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
783 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
784 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
785
786 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
787 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
788 }
789
mtk_max_buf_size(int frag_size)790 static inline int mtk_max_buf_size(int frag_size)
791 {
792 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
793 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
794
795 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
796
797 return buf_size;
798 }
799
mtk_rx_get_desc(struct mtk_rx_dma * rxd,struct mtk_rx_dma * dma_rxd)800 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
801 struct mtk_rx_dma *dma_rxd)
802 {
803 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
804 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
805 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
806 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
807 }
808
mtk_max_lro_buf_alloc(gfp_t gfp_mask)809 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
810 {
811 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
812 unsigned long data;
813
814 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
815 get_order(size));
816
817 return (void *)data;
818 }
819
820 /* the qdma core needs scratch memory to be setup */
mtk_init_fq_dma(struct mtk_eth * eth)821 static int mtk_init_fq_dma(struct mtk_eth *eth)
822 {
823 dma_addr_t phy_ring_tail;
824 int cnt = MTK_DMA_SIZE;
825 dma_addr_t dma_addr;
826 int i;
827
828 eth->scratch_ring = dma_alloc_coherent(eth->dev,
829 cnt * sizeof(struct mtk_tx_dma),
830 ð->phy_scratch_ring,
831 GFP_ATOMIC);
832 if (unlikely(!eth->scratch_ring))
833 return -ENOMEM;
834
835 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
836 GFP_KERNEL);
837 if (unlikely(!eth->scratch_head))
838 return -ENOMEM;
839
840 dma_addr = dma_map_single(eth->dev,
841 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
842 DMA_FROM_DEVICE);
843 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
844 return -ENOMEM;
845
846 phy_ring_tail = eth->phy_scratch_ring +
847 (sizeof(struct mtk_tx_dma) * (cnt - 1));
848
849 for (i = 0; i < cnt; i++) {
850 eth->scratch_ring[i].txd1 =
851 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
852 if (i < cnt - 1)
853 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
854 ((i + 1) * sizeof(struct mtk_tx_dma)));
855 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
856 }
857
858 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
859 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
860 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
861 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
862
863 return 0;
864 }
865
mtk_qdma_phys_to_virt(struct mtk_tx_ring * ring,u32 desc)866 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
867 {
868 void *ret = ring->dma;
869
870 return ret + (desc - ring->phys);
871 }
872
mtk_desc_to_tx_buf(struct mtk_tx_ring * ring,struct mtk_tx_dma * txd)873 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
874 struct mtk_tx_dma *txd)
875 {
876 int idx = txd - ring->dma;
877
878 return &ring->buf[idx];
879 }
880
qdma_to_pdma(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)881 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
882 struct mtk_tx_dma *dma)
883 {
884 return ring->dma_pdma - ring->dma + dma;
885 }
886
txd_to_idx(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)887 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma)
888 {
889 return ((void *)dma - (void *)ring->dma) / sizeof(*dma);
890 }
891
mtk_tx_unmap(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf)892 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
893 {
894 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
895 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
896 dma_unmap_single(eth->dev,
897 dma_unmap_addr(tx_buf, dma_addr0),
898 dma_unmap_len(tx_buf, dma_len0),
899 DMA_TO_DEVICE);
900 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
901 dma_unmap_page(eth->dev,
902 dma_unmap_addr(tx_buf, dma_addr0),
903 dma_unmap_len(tx_buf, dma_len0),
904 DMA_TO_DEVICE);
905 }
906 } else {
907 if (dma_unmap_len(tx_buf, dma_len0)) {
908 dma_unmap_page(eth->dev,
909 dma_unmap_addr(tx_buf, dma_addr0),
910 dma_unmap_len(tx_buf, dma_len0),
911 DMA_TO_DEVICE);
912 }
913
914 if (dma_unmap_len(tx_buf, dma_len1)) {
915 dma_unmap_page(eth->dev,
916 dma_unmap_addr(tx_buf, dma_addr1),
917 dma_unmap_len(tx_buf, dma_len1),
918 DMA_TO_DEVICE);
919 }
920 }
921
922 tx_buf->flags = 0;
923 if (tx_buf->skb &&
924 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
925 dev_kfree_skb_any(tx_buf->skb);
926 tx_buf->skb = NULL;
927 }
928
setup_tx_buf(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct mtk_tx_dma * txd,dma_addr_t mapped_addr,size_t size,int idx)929 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
930 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
931 size_t size, int idx)
932 {
933 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
934 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
935 dma_unmap_len_set(tx_buf, dma_len0, size);
936 } else {
937 if (idx & 1) {
938 txd->txd3 = mapped_addr;
939 txd->txd2 |= TX_DMA_PLEN1(size);
940 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
941 dma_unmap_len_set(tx_buf, dma_len1, size);
942 } else {
943 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
944 txd->txd1 = mapped_addr;
945 txd->txd2 = TX_DMA_PLEN0(size);
946 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
947 dma_unmap_len_set(tx_buf, dma_len0, size);
948 }
949 }
950 }
951
mtk_tx_map(struct sk_buff * skb,struct net_device * dev,int tx_num,struct mtk_tx_ring * ring,bool gso)952 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
953 int tx_num, struct mtk_tx_ring *ring, bool gso)
954 {
955 struct mtk_mac *mac = netdev_priv(dev);
956 struct mtk_eth *eth = mac->hw;
957 struct mtk_tx_dma *itxd, *txd;
958 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
959 struct mtk_tx_buf *itx_buf, *tx_buf;
960 dma_addr_t mapped_addr;
961 unsigned int nr_frags;
962 int i, n_desc = 1;
963 u32 txd4 = 0, fport;
964 int k = 0;
965
966 itxd = ring->next_free;
967 itxd_pdma = qdma_to_pdma(ring, itxd);
968 if (itxd == ring->last_free)
969 return -ENOMEM;
970
971 /* set the forward port */
972 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
973 txd4 |= fport;
974
975 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
976 memset(itx_buf, 0, sizeof(*itx_buf));
977
978 if (gso)
979 txd4 |= TX_DMA_TSO;
980
981 /* TX Checksum offload */
982 if (skb->ip_summed == CHECKSUM_PARTIAL)
983 txd4 |= TX_DMA_CHKSUM;
984
985 /* VLAN header offload */
986 if (skb_vlan_tag_present(skb))
987 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
988
989 mapped_addr = dma_map_single(eth->dev, skb->data,
990 skb_headlen(skb), DMA_TO_DEVICE);
991 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
992 return -ENOMEM;
993
994 WRITE_ONCE(itxd->txd1, mapped_addr);
995 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
996 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
997 MTK_TX_FLAGS_FPORT1;
998 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb),
999 k++);
1000
1001 /* TX SG offload */
1002 txd = itxd;
1003 txd_pdma = qdma_to_pdma(ring, txd);
1004 nr_frags = skb_shinfo(skb)->nr_frags;
1005
1006 for (i = 0; i < nr_frags; i++) {
1007 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1008 unsigned int offset = 0;
1009 int frag_size = skb_frag_size(frag);
1010
1011 while (frag_size) {
1012 bool last_frag = false;
1013 unsigned int frag_map_size;
1014 bool new_desc = true;
1015
1016 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) ||
1017 (i & 0x1)) {
1018 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1019 txd_pdma = qdma_to_pdma(ring, txd);
1020 if (txd == ring->last_free)
1021 goto err_dma;
1022
1023 n_desc++;
1024 } else {
1025 new_desc = false;
1026 }
1027
1028
1029 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
1030 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
1031 frag_map_size,
1032 DMA_TO_DEVICE);
1033 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
1034 goto err_dma;
1035
1036 if (i == nr_frags - 1 &&
1037 (frag_size - frag_map_size) == 0)
1038 last_frag = true;
1039
1040 WRITE_ONCE(txd->txd1, mapped_addr);
1041 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
1042 TX_DMA_PLEN0(frag_map_size) |
1043 last_frag * TX_DMA_LS0));
1044 WRITE_ONCE(txd->txd4, fport);
1045
1046 tx_buf = mtk_desc_to_tx_buf(ring, txd);
1047 if (new_desc)
1048 memset(tx_buf, 0, sizeof(*tx_buf));
1049 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
1050 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1051 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1052 MTK_TX_FLAGS_FPORT1;
1053
1054 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr,
1055 frag_map_size, k++);
1056
1057 frag_size -= frag_map_size;
1058 offset += frag_map_size;
1059 }
1060 }
1061
1062 /* store skb to cleanup */
1063 itx_buf->skb = skb;
1064
1065 WRITE_ONCE(itxd->txd4, txd4);
1066 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
1067 (!nr_frags * TX_DMA_LS0)));
1068 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1069 if (k & 0x1)
1070 txd_pdma->txd2 |= TX_DMA_LS0;
1071 else
1072 txd_pdma->txd2 |= TX_DMA_LS1;
1073 }
1074
1075 netdev_sent_queue(dev, skb->len);
1076 skb_tx_timestamp(skb);
1077
1078 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1079 atomic_sub(n_desc, &ring->free_count);
1080
1081 /* make sure that all changes to the dma ring are flushed before we
1082 * continue
1083 */
1084 wmb();
1085
1086 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1087 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
1088 !netdev_xmit_more())
1089 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
1090 } else {
1091 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd),
1092 ring->dma_size);
1093 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1094 }
1095
1096 return 0;
1097
1098 err_dma:
1099 do {
1100 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
1101
1102 /* unmap dma */
1103 mtk_tx_unmap(eth, tx_buf);
1104
1105 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1106 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1107 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1108
1109 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1110 itxd_pdma = qdma_to_pdma(ring, itxd);
1111 } while (itxd != txd);
1112
1113 return -ENOMEM;
1114 }
1115
mtk_cal_txd_req(struct sk_buff * skb)1116 static inline int mtk_cal_txd_req(struct sk_buff *skb)
1117 {
1118 int i, nfrags;
1119 skb_frag_t *frag;
1120
1121 nfrags = 1;
1122 if (skb_is_gso(skb)) {
1123 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1124 frag = &skb_shinfo(skb)->frags[i];
1125 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1126 MTK_TX_DMA_BUF_LEN);
1127 }
1128 } else {
1129 nfrags += skb_shinfo(skb)->nr_frags;
1130 }
1131
1132 return nfrags;
1133 }
1134
mtk_queue_stopped(struct mtk_eth * eth)1135 static int mtk_queue_stopped(struct mtk_eth *eth)
1136 {
1137 int i;
1138
1139 for (i = 0; i < MTK_MAC_COUNT; i++) {
1140 if (!eth->netdev[i])
1141 continue;
1142 if (netif_queue_stopped(eth->netdev[i]))
1143 return 1;
1144 }
1145
1146 return 0;
1147 }
1148
mtk_wake_queue(struct mtk_eth * eth)1149 static void mtk_wake_queue(struct mtk_eth *eth)
1150 {
1151 int i;
1152
1153 for (i = 0; i < MTK_MAC_COUNT; i++) {
1154 if (!eth->netdev[i])
1155 continue;
1156 netif_wake_queue(eth->netdev[i]);
1157 }
1158 }
1159
mtk_stop_queue(struct mtk_eth * eth)1160 static void mtk_stop_queue(struct mtk_eth *eth)
1161 {
1162 int i;
1163
1164 for (i = 0; i < MTK_MAC_COUNT; i++) {
1165 if (!eth->netdev[i])
1166 continue;
1167 netif_stop_queue(eth->netdev[i]);
1168 }
1169 }
1170
mtk_start_xmit(struct sk_buff * skb,struct net_device * dev)1171 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1172 {
1173 struct mtk_mac *mac = netdev_priv(dev);
1174 struct mtk_eth *eth = mac->hw;
1175 struct mtk_tx_ring *ring = ð->tx_ring;
1176 struct net_device_stats *stats = &dev->stats;
1177 bool gso = false;
1178 int tx_num;
1179
1180 /* normally we can rely on the stack not calling this more than once,
1181 * however we have 2 queues running on the same ring so we need to lock
1182 * the ring access
1183 */
1184 spin_lock(ð->page_lock);
1185
1186 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1187 goto drop;
1188
1189 tx_num = mtk_cal_txd_req(skb);
1190 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1191 mtk_stop_queue(eth);
1192 netif_err(eth, tx_queued, dev,
1193 "Tx Ring full when queue awake!\n");
1194 spin_unlock(ð->page_lock);
1195 return NETDEV_TX_BUSY;
1196 }
1197
1198 /* TSO: fill MSS info in tcp checksum field */
1199 if (skb_is_gso(skb)) {
1200 if (skb_cow_head(skb, 0)) {
1201 netif_warn(eth, tx_err, dev,
1202 "GSO expand head fail.\n");
1203 goto drop;
1204 }
1205
1206 if (skb_shinfo(skb)->gso_type &
1207 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1208 gso = true;
1209 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1210 }
1211 }
1212
1213 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1214 goto drop;
1215
1216 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1217 mtk_stop_queue(eth);
1218
1219 spin_unlock(ð->page_lock);
1220
1221 return NETDEV_TX_OK;
1222
1223 drop:
1224 spin_unlock(ð->page_lock);
1225 stats->tx_dropped++;
1226 dev_kfree_skb_any(skb);
1227 return NETDEV_TX_OK;
1228 }
1229
mtk_get_rx_ring(struct mtk_eth * eth)1230 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1231 {
1232 int i;
1233 struct mtk_rx_ring *ring;
1234 int idx;
1235
1236 if (!eth->hwlro)
1237 return ð->rx_ring[0];
1238
1239 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1240 ring = ð->rx_ring[i];
1241 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1242 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
1243 ring->calc_idx_update = true;
1244 return ring;
1245 }
1246 }
1247
1248 return NULL;
1249 }
1250
mtk_update_rx_cpu_idx(struct mtk_eth * eth)1251 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1252 {
1253 struct mtk_rx_ring *ring;
1254 int i;
1255
1256 if (!eth->hwlro) {
1257 ring = ð->rx_ring[0];
1258 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1259 } else {
1260 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1261 ring = ð->rx_ring[i];
1262 if (ring->calc_idx_update) {
1263 ring->calc_idx_update = false;
1264 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1265 }
1266 }
1267 }
1268 }
1269
mtk_poll_rx(struct napi_struct * napi,int budget,struct mtk_eth * eth)1270 static int mtk_poll_rx(struct napi_struct *napi, int budget,
1271 struct mtk_eth *eth)
1272 {
1273 struct mtk_rx_ring *ring;
1274 int idx;
1275 struct sk_buff *skb;
1276 u8 *data, *new_data;
1277 struct mtk_rx_dma *rxd, trxd;
1278 int done = 0;
1279
1280 while (done < budget) {
1281 struct net_device *netdev;
1282 unsigned int pktlen;
1283 dma_addr_t dma_addr;
1284 int mac;
1285
1286 ring = mtk_get_rx_ring(eth);
1287 if (unlikely(!ring))
1288 goto rx_done;
1289
1290 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1291 rxd = &ring->dma[idx];
1292 data = ring->data[idx];
1293
1294 mtk_rx_get_desc(&trxd, rxd);
1295 if (!(trxd.rxd2 & RX_DMA_DONE))
1296 break;
1297
1298 /* find out which mac the packet come from. values start at 1 */
1299 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
1300 mac = 0;
1301 } else {
1302 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
1303 RX_DMA_FPORT_MASK;
1304 mac--;
1305 }
1306
1307 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1308 !eth->netdev[mac]))
1309 goto release_desc;
1310
1311 netdev = eth->netdev[mac];
1312
1313 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1314 goto release_desc;
1315
1316 /* alloc new buffer */
1317 if (ring->frag_size <= PAGE_SIZE)
1318 new_data = napi_alloc_frag(ring->frag_size);
1319 else
1320 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
1321 if (unlikely(!new_data)) {
1322 netdev->stats.rx_dropped++;
1323 goto release_desc;
1324 }
1325 dma_addr = dma_map_single(eth->dev,
1326 new_data + NET_SKB_PAD +
1327 eth->ip_align,
1328 ring->buf_size,
1329 DMA_FROM_DEVICE);
1330 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
1331 skb_free_frag(new_data);
1332 netdev->stats.rx_dropped++;
1333 goto release_desc;
1334 }
1335
1336 /* receive data */
1337 skb = build_skb(data, ring->frag_size);
1338 if (unlikely(!skb)) {
1339 skb_free_frag(new_data);
1340 netdev->stats.rx_dropped++;
1341 goto release_desc;
1342 }
1343 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1344
1345 dma_unmap_single(eth->dev, trxd.rxd1,
1346 ring->buf_size, DMA_FROM_DEVICE);
1347 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1348 skb->dev = netdev;
1349 skb_put(skb, pktlen);
1350 if (trxd.rxd4 & eth->rx_dma_l4_valid)
1351 skb->ip_summed = CHECKSUM_UNNECESSARY;
1352 else
1353 skb_checksum_none_assert(skb);
1354 skb->protocol = eth_type_trans(skb, netdev);
1355
1356 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1357 (trxd.rxd2 & RX_DMA_VTAG))
1358 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1359 RX_DMA_VID(trxd.rxd3));
1360 skb_record_rx_queue(skb, 0);
1361 napi_gro_receive(napi, skb);
1362
1363 ring->data[idx] = new_data;
1364 rxd->rxd1 = (unsigned int)dma_addr;
1365
1366 release_desc:
1367 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1368 rxd->rxd2 = RX_DMA_LSO;
1369 else
1370 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1371
1372 ring->calc_idx = idx;
1373
1374 done++;
1375 }
1376
1377 rx_done:
1378 if (done) {
1379 /* make sure that all changes to the dma ring are flushed before
1380 * we continue
1381 */
1382 wmb();
1383 mtk_update_rx_cpu_idx(eth);
1384 }
1385
1386 return done;
1387 }
1388
mtk_poll_tx_qdma(struct mtk_eth * eth,int budget,unsigned int * done,unsigned int * bytes)1389 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
1390 unsigned int *done, unsigned int *bytes)
1391 {
1392 struct mtk_tx_ring *ring = ð->tx_ring;
1393 struct mtk_tx_dma *desc;
1394 struct sk_buff *skb;
1395 struct mtk_tx_buf *tx_buf;
1396 u32 cpu, dma;
1397
1398 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1399 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1400
1401 desc = mtk_qdma_phys_to_virt(ring, cpu);
1402
1403 while ((cpu != dma) && budget) {
1404 u32 next_cpu = desc->txd2;
1405 int mac = 0;
1406
1407 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1408 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1409 break;
1410
1411 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1412 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1413 mac = 1;
1414
1415 skb = tx_buf->skb;
1416 if (!skb)
1417 break;
1418
1419 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1420 bytes[mac] += skb->len;
1421 done[mac]++;
1422 budget--;
1423 }
1424 mtk_tx_unmap(eth, tx_buf);
1425
1426 ring->last_free = desc;
1427 atomic_inc(&ring->free_count);
1428
1429 cpu = next_cpu;
1430 }
1431
1432 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1433
1434 return budget;
1435 }
1436
mtk_poll_tx_pdma(struct mtk_eth * eth,int budget,unsigned int * done,unsigned int * bytes)1437 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
1438 unsigned int *done, unsigned int *bytes)
1439 {
1440 struct mtk_tx_ring *ring = ð->tx_ring;
1441 struct mtk_tx_dma *desc;
1442 struct sk_buff *skb;
1443 struct mtk_tx_buf *tx_buf;
1444 u32 cpu, dma;
1445
1446 cpu = ring->cpu_idx;
1447 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
1448
1449 while ((cpu != dma) && budget) {
1450 tx_buf = &ring->buf[cpu];
1451 skb = tx_buf->skb;
1452 if (!skb)
1453 break;
1454
1455 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1456 bytes[0] += skb->len;
1457 done[0]++;
1458 budget--;
1459 }
1460
1461 mtk_tx_unmap(eth, tx_buf);
1462
1463 desc = &ring->dma[cpu];
1464 ring->last_free = desc;
1465 atomic_inc(&ring->free_count);
1466
1467 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
1468 }
1469
1470 ring->cpu_idx = cpu;
1471
1472 return budget;
1473 }
1474
mtk_poll_tx(struct mtk_eth * eth,int budget)1475 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1476 {
1477 struct mtk_tx_ring *ring = ð->tx_ring;
1478 unsigned int done[MTK_MAX_DEVS];
1479 unsigned int bytes[MTK_MAX_DEVS];
1480 int total = 0, i;
1481
1482 memset(done, 0, sizeof(done));
1483 memset(bytes, 0, sizeof(bytes));
1484
1485 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1486 budget = mtk_poll_tx_qdma(eth, budget, done, bytes);
1487 else
1488 budget = mtk_poll_tx_pdma(eth, budget, done, bytes);
1489
1490 for (i = 0; i < MTK_MAC_COUNT; i++) {
1491 if (!eth->netdev[i] || !done[i])
1492 continue;
1493 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1494 total += done[i];
1495 }
1496
1497 if (mtk_queue_stopped(eth) &&
1498 (atomic_read(&ring->free_count) > ring->thresh))
1499 mtk_wake_queue(eth);
1500
1501 return total;
1502 }
1503
mtk_handle_status_irq(struct mtk_eth * eth)1504 static void mtk_handle_status_irq(struct mtk_eth *eth)
1505 {
1506 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1507
1508 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1509 mtk_stats_update(eth);
1510 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1511 MTK_INT_STATUS2);
1512 }
1513 }
1514
mtk_napi_tx(struct napi_struct * napi,int budget)1515 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1516 {
1517 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1518 u32 status, mask;
1519 int tx_done = 0;
1520
1521 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1522 mtk_handle_status_irq(eth);
1523 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg);
1524 tx_done = mtk_poll_tx(eth, budget);
1525
1526 if (unlikely(netif_msg_intr(eth))) {
1527 status = mtk_r32(eth, eth->tx_int_status_reg);
1528 mask = mtk_r32(eth, eth->tx_int_mask_reg);
1529 dev_info(eth->dev,
1530 "done tx %d, intr 0x%08x/0x%x\n",
1531 tx_done, status, mask);
1532 }
1533
1534 if (tx_done == budget)
1535 return budget;
1536
1537 status = mtk_r32(eth, eth->tx_int_status_reg);
1538 if (status & MTK_TX_DONE_INT)
1539 return budget;
1540
1541 napi_complete(napi);
1542 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1543
1544 return tx_done;
1545 }
1546
mtk_napi_rx(struct napi_struct * napi,int budget)1547 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1548 {
1549 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1550 u32 status, mask;
1551 int rx_done = 0;
1552 int remain_budget = budget;
1553
1554 mtk_handle_status_irq(eth);
1555
1556 poll_again:
1557 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1558 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1559
1560 if (unlikely(netif_msg_intr(eth))) {
1561 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1562 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1563 dev_info(eth->dev,
1564 "done rx %d, intr 0x%08x/0x%x\n",
1565 rx_done, status, mask);
1566 }
1567 if (rx_done == remain_budget)
1568 return budget;
1569
1570 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1571 if (status & MTK_RX_DONE_INT) {
1572 remain_budget -= rx_done;
1573 goto poll_again;
1574 }
1575 napi_complete(napi);
1576 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1577
1578 return rx_done + budget - remain_budget;
1579 }
1580
mtk_tx_alloc(struct mtk_eth * eth)1581 static int mtk_tx_alloc(struct mtk_eth *eth)
1582 {
1583 struct mtk_tx_ring *ring = ð->tx_ring;
1584 int i, sz = sizeof(*ring->dma);
1585
1586 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1587 GFP_KERNEL);
1588 if (!ring->buf)
1589 goto no_tx_mem;
1590
1591 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1592 &ring->phys, GFP_ATOMIC);
1593 if (!ring->dma)
1594 goto no_tx_mem;
1595
1596 for (i = 0; i < MTK_DMA_SIZE; i++) {
1597 int next = (i + 1) % MTK_DMA_SIZE;
1598 u32 next_ptr = ring->phys + next * sz;
1599
1600 ring->dma[i].txd2 = next_ptr;
1601 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1602 }
1603
1604 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
1605 * only as the framework. The real HW descriptors are the PDMA
1606 * descriptors in ring->dma_pdma.
1607 */
1608 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1609 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1610 &ring->phys_pdma,
1611 GFP_ATOMIC);
1612 if (!ring->dma_pdma)
1613 goto no_tx_mem;
1614
1615 for (i = 0; i < MTK_DMA_SIZE; i++) {
1616 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
1617 ring->dma_pdma[i].txd4 = 0;
1618 }
1619 }
1620
1621 ring->dma_size = MTK_DMA_SIZE;
1622 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1623 ring->next_free = &ring->dma[0];
1624 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1625 ring->thresh = MAX_SKB_FRAGS;
1626
1627 /* make sure that all changes to the dma ring are flushed before we
1628 * continue
1629 */
1630 wmb();
1631
1632 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1633 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1634 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1635 mtk_w32(eth,
1636 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1637 MTK_QTX_CRX_PTR);
1638 mtk_w32(eth,
1639 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1640 MTK_QTX_DRX_PTR);
1641 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,
1642 MTK_QTX_CFG(0));
1643 } else {
1644 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
1645 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0);
1646 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
1647 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX);
1648 }
1649
1650 return 0;
1651
1652 no_tx_mem:
1653 return -ENOMEM;
1654 }
1655
mtk_tx_clean(struct mtk_eth * eth)1656 static void mtk_tx_clean(struct mtk_eth *eth)
1657 {
1658 struct mtk_tx_ring *ring = ð->tx_ring;
1659 int i;
1660
1661 if (ring->buf) {
1662 for (i = 0; i < MTK_DMA_SIZE; i++)
1663 mtk_tx_unmap(eth, &ring->buf[i]);
1664 kfree(ring->buf);
1665 ring->buf = NULL;
1666 }
1667
1668 if (ring->dma) {
1669 dma_free_coherent(eth->dev,
1670 MTK_DMA_SIZE * sizeof(*ring->dma),
1671 ring->dma,
1672 ring->phys);
1673 ring->dma = NULL;
1674 }
1675
1676 if (ring->dma_pdma) {
1677 dma_free_coherent(eth->dev,
1678 MTK_DMA_SIZE * sizeof(*ring->dma_pdma),
1679 ring->dma_pdma,
1680 ring->phys_pdma);
1681 ring->dma_pdma = NULL;
1682 }
1683 }
1684
mtk_rx_alloc(struct mtk_eth * eth,int ring_no,int rx_flag)1685 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1686 {
1687 struct mtk_rx_ring *ring;
1688 int rx_data_len, rx_dma_size;
1689 int i;
1690 u32 offset = 0;
1691
1692 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1693 if (ring_no)
1694 return -EINVAL;
1695 ring = ð->rx_ring_qdma;
1696 offset = 0x1000;
1697 } else {
1698 ring = ð->rx_ring[ring_no];
1699 }
1700
1701 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1702 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1703 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1704 } else {
1705 rx_data_len = ETH_DATA_LEN;
1706 rx_dma_size = MTK_DMA_SIZE;
1707 }
1708
1709 ring->frag_size = mtk_max_frag_size(rx_data_len);
1710 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1711 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1712 GFP_KERNEL);
1713 if (!ring->data)
1714 return -ENOMEM;
1715
1716 for (i = 0; i < rx_dma_size; i++) {
1717 if (ring->frag_size <= PAGE_SIZE)
1718 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1719 else
1720 ring->data[i] = mtk_max_lro_buf_alloc(GFP_KERNEL);
1721 if (!ring->data[i])
1722 return -ENOMEM;
1723 }
1724
1725 ring->dma = dma_alloc_coherent(eth->dev,
1726 rx_dma_size * sizeof(*ring->dma),
1727 &ring->phys, GFP_ATOMIC);
1728 if (!ring->dma)
1729 return -ENOMEM;
1730
1731 for (i = 0; i < rx_dma_size; i++) {
1732 dma_addr_t dma_addr = dma_map_single(eth->dev,
1733 ring->data[i] + NET_SKB_PAD + eth->ip_align,
1734 ring->buf_size,
1735 DMA_FROM_DEVICE);
1736 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1737 return -ENOMEM;
1738 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1739
1740 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1741 ring->dma[i].rxd2 = RX_DMA_LSO;
1742 else
1743 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1744 }
1745 ring->dma_size = rx_dma_size;
1746 ring->calc_idx_update = false;
1747 ring->calc_idx = rx_dma_size - 1;
1748 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1749 /* make sure that all changes to the dma ring are flushed before we
1750 * continue
1751 */
1752 wmb();
1753
1754 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1755 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1756 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1757 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1758
1759 return 0;
1760 }
1761
mtk_rx_clean(struct mtk_eth * eth,struct mtk_rx_ring * ring)1762 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1763 {
1764 int i;
1765
1766 if (ring->data && ring->dma) {
1767 for (i = 0; i < ring->dma_size; i++) {
1768 if (!ring->data[i])
1769 continue;
1770 if (!ring->dma[i].rxd1)
1771 continue;
1772 dma_unmap_single(eth->dev,
1773 ring->dma[i].rxd1,
1774 ring->buf_size,
1775 DMA_FROM_DEVICE);
1776 skb_free_frag(ring->data[i]);
1777 }
1778 kfree(ring->data);
1779 ring->data = NULL;
1780 }
1781
1782 if (ring->dma) {
1783 dma_free_coherent(eth->dev,
1784 ring->dma_size * sizeof(*ring->dma),
1785 ring->dma,
1786 ring->phys);
1787 ring->dma = NULL;
1788 }
1789 }
1790
mtk_hwlro_rx_init(struct mtk_eth * eth)1791 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1792 {
1793 int i;
1794 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1795 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1796
1797 /* set LRO rings to auto-learn modes */
1798 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1799
1800 /* validate LRO ring */
1801 ring_ctrl_dw2 |= MTK_RING_VLD;
1802
1803 /* set AGE timer (unit: 20us) */
1804 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1805 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1806
1807 /* set max AGG timer (unit: 20us) */
1808 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1809
1810 /* set max LRO AGG count */
1811 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1812 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1813
1814 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1815 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1816 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1817 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1818 }
1819
1820 /* IPv4 checksum update enable */
1821 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1822
1823 /* switch priority comparison to packet count mode */
1824 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1825
1826 /* bandwidth threshold setting */
1827 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1828
1829 /* auto-learn score delta setting */
1830 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1831
1832 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1833 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1834 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1835
1836 /* set HW LRO mode & the max aggregation count for rx packets */
1837 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1838
1839 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1840 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1841
1842 /* enable HW LRO */
1843 lro_ctrl_dw0 |= MTK_LRO_EN;
1844
1845 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1846 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1847
1848 return 0;
1849 }
1850
mtk_hwlro_rx_uninit(struct mtk_eth * eth)1851 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1852 {
1853 int i;
1854 u32 val;
1855
1856 /* relinquish lro rings, flush aggregated packets */
1857 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1858
1859 /* wait for relinquishments done */
1860 for (i = 0; i < 10; i++) {
1861 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1862 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1863 msleep(20);
1864 continue;
1865 }
1866 break;
1867 }
1868
1869 /* invalidate lro rings */
1870 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1871 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1872
1873 /* disable HW LRO */
1874 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1875 }
1876
mtk_hwlro_val_ipaddr(struct mtk_eth * eth,int idx,__be32 ip)1877 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1878 {
1879 u32 reg_val;
1880
1881 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1882
1883 /* invalidate the IP setting */
1884 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1885
1886 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1887
1888 /* validate the IP setting */
1889 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1890 }
1891
mtk_hwlro_inval_ipaddr(struct mtk_eth * eth,int idx)1892 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1893 {
1894 u32 reg_val;
1895
1896 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1897
1898 /* invalidate the IP setting */
1899 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1900
1901 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1902 }
1903
mtk_hwlro_get_ip_cnt(struct mtk_mac * mac)1904 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1905 {
1906 int cnt = 0;
1907 int i;
1908
1909 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1910 if (mac->hwlro_ip[i])
1911 cnt++;
1912 }
1913
1914 return cnt;
1915 }
1916
mtk_hwlro_add_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)1917 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1918 struct ethtool_rxnfc *cmd)
1919 {
1920 struct ethtool_rx_flow_spec *fsp =
1921 (struct ethtool_rx_flow_spec *)&cmd->fs;
1922 struct mtk_mac *mac = netdev_priv(dev);
1923 struct mtk_eth *eth = mac->hw;
1924 int hwlro_idx;
1925
1926 if ((fsp->flow_type != TCP_V4_FLOW) ||
1927 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1928 (fsp->location > 1))
1929 return -EINVAL;
1930
1931 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1932 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1933
1934 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1935
1936 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1937
1938 return 0;
1939 }
1940
mtk_hwlro_del_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)1941 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1942 struct ethtool_rxnfc *cmd)
1943 {
1944 struct ethtool_rx_flow_spec *fsp =
1945 (struct ethtool_rx_flow_spec *)&cmd->fs;
1946 struct mtk_mac *mac = netdev_priv(dev);
1947 struct mtk_eth *eth = mac->hw;
1948 int hwlro_idx;
1949
1950 if (fsp->location > 1)
1951 return -EINVAL;
1952
1953 mac->hwlro_ip[fsp->location] = 0;
1954 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1955
1956 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1957
1958 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1959
1960 return 0;
1961 }
1962
mtk_hwlro_netdev_disable(struct net_device * dev)1963 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1964 {
1965 struct mtk_mac *mac = netdev_priv(dev);
1966 struct mtk_eth *eth = mac->hw;
1967 int i, hwlro_idx;
1968
1969 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1970 mac->hwlro_ip[i] = 0;
1971 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1972
1973 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1974 }
1975
1976 mac->hwlro_ip_cnt = 0;
1977 }
1978
mtk_hwlro_get_fdir_entry(struct net_device * dev,struct ethtool_rxnfc * cmd)1979 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1980 struct ethtool_rxnfc *cmd)
1981 {
1982 struct mtk_mac *mac = netdev_priv(dev);
1983 struct ethtool_rx_flow_spec *fsp =
1984 (struct ethtool_rx_flow_spec *)&cmd->fs;
1985
1986 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
1987 return -EINVAL;
1988
1989 /* only tcp dst ipv4 is meaningful, others are meaningless */
1990 fsp->flow_type = TCP_V4_FLOW;
1991 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1992 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1993
1994 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1995 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1996 fsp->h_u.tcp_ip4_spec.psrc = 0;
1997 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1998 fsp->h_u.tcp_ip4_spec.pdst = 0;
1999 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
2000 fsp->h_u.tcp_ip4_spec.tos = 0;
2001 fsp->m_u.tcp_ip4_spec.tos = 0xff;
2002
2003 return 0;
2004 }
2005
mtk_hwlro_get_fdir_all(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2006 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
2007 struct ethtool_rxnfc *cmd,
2008 u32 *rule_locs)
2009 {
2010 struct mtk_mac *mac = netdev_priv(dev);
2011 int cnt = 0;
2012 int i;
2013
2014 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2015 if (mac->hwlro_ip[i]) {
2016 rule_locs[cnt] = i;
2017 cnt++;
2018 }
2019 }
2020
2021 cmd->rule_cnt = cnt;
2022
2023 return 0;
2024 }
2025
mtk_fix_features(struct net_device * dev,netdev_features_t features)2026 static netdev_features_t mtk_fix_features(struct net_device *dev,
2027 netdev_features_t features)
2028 {
2029 if (!(features & NETIF_F_LRO)) {
2030 struct mtk_mac *mac = netdev_priv(dev);
2031 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2032
2033 if (ip_cnt) {
2034 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
2035
2036 features |= NETIF_F_LRO;
2037 }
2038 }
2039
2040 return features;
2041 }
2042
mtk_set_features(struct net_device * dev,netdev_features_t features)2043 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
2044 {
2045 int err = 0;
2046
2047 if (!((dev->features ^ features) & NETIF_F_LRO))
2048 return 0;
2049
2050 if (!(features & NETIF_F_LRO))
2051 mtk_hwlro_netdev_disable(dev);
2052
2053 return err;
2054 }
2055
2056 /* wait for DMA to finish whatever it is doing before we start using it again */
mtk_dma_busy_wait(struct mtk_eth * eth)2057 static int mtk_dma_busy_wait(struct mtk_eth *eth)
2058 {
2059 unsigned long t_start = jiffies;
2060
2061 while (1) {
2062 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2063 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
2064 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
2065 return 0;
2066 } else {
2067 if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) &
2068 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
2069 return 0;
2070 }
2071
2072 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
2073 break;
2074 }
2075
2076 dev_err(eth->dev, "DMA init timeout\n");
2077 return -1;
2078 }
2079
mtk_dma_init(struct mtk_eth * eth)2080 static int mtk_dma_init(struct mtk_eth *eth)
2081 {
2082 int err;
2083 u32 i;
2084
2085 if (mtk_dma_busy_wait(eth))
2086 return -EBUSY;
2087
2088 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2089 /* QDMA needs scratch memory for internal reordering of the
2090 * descriptors
2091 */
2092 err = mtk_init_fq_dma(eth);
2093 if (err)
2094 return err;
2095 }
2096
2097 err = mtk_tx_alloc(eth);
2098 if (err)
2099 return err;
2100
2101 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2102 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
2103 if (err)
2104 return err;
2105 }
2106
2107 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
2108 if (err)
2109 return err;
2110
2111 if (eth->hwlro) {
2112 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2113 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
2114 if (err)
2115 return err;
2116 }
2117 err = mtk_hwlro_rx_init(eth);
2118 if (err)
2119 return err;
2120 }
2121
2122 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2123 /* Enable random early drop and set drop threshold
2124 * automatically
2125 */
2126 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
2127 FC_THRES_MIN, MTK_QDMA_FC_THRES);
2128 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
2129 }
2130
2131 return 0;
2132 }
2133
mtk_dma_free(struct mtk_eth * eth)2134 static void mtk_dma_free(struct mtk_eth *eth)
2135 {
2136 int i;
2137
2138 for (i = 0; i < MTK_MAC_COUNT; i++)
2139 if (eth->netdev[i])
2140 netdev_reset_queue(eth->netdev[i]);
2141 if (eth->scratch_ring) {
2142 dma_free_coherent(eth->dev,
2143 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
2144 eth->scratch_ring,
2145 eth->phy_scratch_ring);
2146 eth->scratch_ring = NULL;
2147 eth->phy_scratch_ring = 0;
2148 }
2149 mtk_tx_clean(eth);
2150 mtk_rx_clean(eth, ð->rx_ring[0]);
2151 mtk_rx_clean(eth, ð->rx_ring_qdma);
2152
2153 if (eth->hwlro) {
2154 mtk_hwlro_rx_uninit(eth);
2155 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2156 mtk_rx_clean(eth, ð->rx_ring[i]);
2157 }
2158
2159 kfree(eth->scratch_head);
2160 }
2161
mtk_tx_timeout(struct net_device * dev,unsigned int txqueue)2162 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
2163 {
2164 struct mtk_mac *mac = netdev_priv(dev);
2165 struct mtk_eth *eth = mac->hw;
2166
2167 eth->netdev[mac->id]->stats.tx_errors++;
2168 netif_err(eth, tx_err, dev,
2169 "transmit timed out\n");
2170 schedule_work(ð->pending_work);
2171 }
2172
mtk_handle_irq_rx(int irq,void * _eth)2173 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
2174 {
2175 struct mtk_eth *eth = _eth;
2176
2177 if (likely(napi_schedule_prep(ð->rx_napi))) {
2178 __napi_schedule(ð->rx_napi);
2179 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2180 }
2181
2182 return IRQ_HANDLED;
2183 }
2184
mtk_handle_irq_tx(int irq,void * _eth)2185 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
2186 {
2187 struct mtk_eth *eth = _eth;
2188
2189 if (likely(napi_schedule_prep(ð->tx_napi))) {
2190 __napi_schedule(ð->tx_napi);
2191 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2192 }
2193
2194 return IRQ_HANDLED;
2195 }
2196
mtk_handle_irq(int irq,void * _eth)2197 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
2198 {
2199 struct mtk_eth *eth = _eth;
2200
2201 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) {
2202 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT)
2203 mtk_handle_irq_rx(irq, _eth);
2204 }
2205 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) {
2206 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT)
2207 mtk_handle_irq_tx(irq, _eth);
2208 }
2209
2210 return IRQ_HANDLED;
2211 }
2212
2213 #ifdef CONFIG_NET_POLL_CONTROLLER
mtk_poll_controller(struct net_device * dev)2214 static void mtk_poll_controller(struct net_device *dev)
2215 {
2216 struct mtk_mac *mac = netdev_priv(dev);
2217 struct mtk_eth *eth = mac->hw;
2218
2219 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2220 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2221 mtk_handle_irq_rx(eth->irq[2], dev);
2222 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2223 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
2224 }
2225 #endif
2226
mtk_start_dma(struct mtk_eth * eth)2227 static int mtk_start_dma(struct mtk_eth *eth)
2228 {
2229 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
2230 int err;
2231
2232 err = mtk_dma_init(eth);
2233 if (err) {
2234 mtk_dma_free(eth);
2235 return err;
2236 }
2237
2238 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2239 mtk_w32(eth,
2240 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
2241 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
2242 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
2243 MTK_RX_BT_32DWORDS,
2244 MTK_QDMA_GLO_CFG);
2245
2246 mtk_w32(eth,
2247 MTK_RX_DMA_EN | rx_2b_offset |
2248 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
2249 MTK_PDMA_GLO_CFG);
2250 } else {
2251 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2252 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
2253 MTK_PDMA_GLO_CFG);
2254 }
2255
2256 return 0;
2257 }
2258
mtk_gdm_config(struct mtk_eth * eth,u32 config)2259 static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
2260 {
2261 int i;
2262
2263 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2264 return;
2265
2266 for (i = 0; i < MTK_MAC_COUNT; i++) {
2267 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
2268
2269 /* default setup the forward port to send frame to PDMA */
2270 val &= ~0xffff;
2271
2272 /* Enable RX checksum */
2273 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2274
2275 val |= config;
2276
2277 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2278 }
2279 /* Reset and enable PSE */
2280 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
2281 mtk_w32(eth, 0, MTK_RST_GL);
2282 }
2283
mtk_open(struct net_device * dev)2284 static int mtk_open(struct net_device *dev)
2285 {
2286 struct mtk_mac *mac = netdev_priv(dev);
2287 struct mtk_eth *eth = mac->hw;
2288 int err;
2289
2290 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
2291 if (err) {
2292 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
2293 err);
2294 return err;
2295 }
2296
2297 /* we run 2 netdevs on the same dma ring so we only bring it up once */
2298 if (!refcount_read(ð->dma_refcnt)) {
2299 int err = mtk_start_dma(eth);
2300
2301 if (err)
2302 if (err) {
2303 phylink_disconnect_phy(mac->phylink);
2304 return err;
2305 }
2306
2307 mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
2308
2309 napi_enable(ð->tx_napi);
2310 napi_enable(ð->rx_napi);
2311 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2312 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
2313 refcount_set(ð->dma_refcnt, 1);
2314 }
2315 else
2316 refcount_inc(ð->dma_refcnt);
2317
2318 phylink_start(mac->phylink);
2319 netif_start_queue(dev);
2320 return 0;
2321 }
2322
mtk_stop_dma(struct mtk_eth * eth,u32 glo_cfg)2323 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
2324 {
2325 u32 val;
2326 int i;
2327
2328 /* stop the dma engine */
2329 spin_lock_bh(ð->page_lock);
2330 val = mtk_r32(eth, glo_cfg);
2331 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
2332 glo_cfg);
2333 spin_unlock_bh(ð->page_lock);
2334
2335 /* wait for dma stop */
2336 for (i = 0; i < 10; i++) {
2337 val = mtk_r32(eth, glo_cfg);
2338 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
2339 msleep(20);
2340 continue;
2341 }
2342 break;
2343 }
2344 }
2345
mtk_stop(struct net_device * dev)2346 static int mtk_stop(struct net_device *dev)
2347 {
2348 struct mtk_mac *mac = netdev_priv(dev);
2349 struct mtk_eth *eth = mac->hw;
2350
2351 phylink_stop(mac->phylink);
2352
2353 netif_tx_disable(dev);
2354
2355 phylink_disconnect_phy(mac->phylink);
2356
2357 /* only shutdown DMA if this is the last user */
2358 if (!refcount_dec_and_test(ð->dma_refcnt))
2359 return 0;
2360
2361 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
2362
2363 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2364 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2365 napi_disable(ð->tx_napi);
2366 napi_disable(ð->rx_napi);
2367
2368 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2369 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
2370 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
2371
2372 mtk_dma_free(eth);
2373
2374 return 0;
2375 }
2376
ethsys_reset(struct mtk_eth * eth,u32 reset_bits)2377 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
2378 {
2379 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2380 reset_bits,
2381 reset_bits);
2382
2383 usleep_range(1000, 1100);
2384 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2385 reset_bits,
2386 ~reset_bits);
2387 mdelay(10);
2388 }
2389
mtk_clk_disable(struct mtk_eth * eth)2390 static void mtk_clk_disable(struct mtk_eth *eth)
2391 {
2392 int clk;
2393
2394 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
2395 clk_disable_unprepare(eth->clks[clk]);
2396 }
2397
mtk_clk_enable(struct mtk_eth * eth)2398 static int mtk_clk_enable(struct mtk_eth *eth)
2399 {
2400 int clk, ret;
2401
2402 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
2403 ret = clk_prepare_enable(eth->clks[clk]);
2404 if (ret)
2405 goto err_disable_clks;
2406 }
2407
2408 return 0;
2409
2410 err_disable_clks:
2411 while (--clk >= 0)
2412 clk_disable_unprepare(eth->clks[clk]);
2413
2414 return ret;
2415 }
2416
mtk_hw_init(struct mtk_eth * eth)2417 static int mtk_hw_init(struct mtk_eth *eth)
2418 {
2419 int i, val, ret;
2420
2421 if (test_and_set_bit(MTK_HW_INIT, ð->state))
2422 return 0;
2423
2424 pm_runtime_enable(eth->dev);
2425 pm_runtime_get_sync(eth->dev);
2426
2427 ret = mtk_clk_enable(eth);
2428 if (ret)
2429 goto err_disable_pm;
2430
2431 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2432 ret = device_reset(eth->dev);
2433 if (ret) {
2434 dev_err(eth->dev, "MAC reset failed!\n");
2435 goto err_disable_pm;
2436 }
2437
2438 /* enable interrupt delay for RX */
2439 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
2440
2441 /* disable delay and normal interrupt */
2442 mtk_tx_irq_disable(eth, ~0);
2443 mtk_rx_irq_disable(eth, ~0);
2444
2445 return 0;
2446 }
2447
2448 /* Non-MT7628 handling... */
2449 ethsys_reset(eth, RSTCTRL_FE);
2450 ethsys_reset(eth, RSTCTRL_PPE);
2451
2452 if (eth->pctl) {
2453 /* Set GE2 driving and slew rate */
2454 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
2455
2456 /* set GE2 TDSEL */
2457 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
2458
2459 /* set GE2 TUNE */
2460 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
2461 }
2462
2463 /* Set linkdown as the default for each GMAC. Its own MCR would be set
2464 * up with the more appropriate value when mtk_mac_config call is being
2465 * invoked.
2466 */
2467 for (i = 0; i < MTK_MAC_COUNT; i++)
2468 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
2469
2470 /* Indicates CDM to parse the MTK special tag from CPU
2471 * which also is working out for untag packets.
2472 */
2473 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
2474 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
2475
2476 /* Enable RX VLan Offloading */
2477 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
2478
2479 /* enable interrupt delay for RX */
2480 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
2481
2482 /* disable delay and normal interrupt */
2483 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
2484 mtk_tx_irq_disable(eth, ~0);
2485 mtk_rx_irq_disable(eth, ~0);
2486
2487 /* FE int grouping */
2488 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
2489 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
2490 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
2491 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
2492 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
2493
2494 return 0;
2495
2496 err_disable_pm:
2497 pm_runtime_put_sync(eth->dev);
2498 pm_runtime_disable(eth->dev);
2499
2500 return ret;
2501 }
2502
mtk_hw_deinit(struct mtk_eth * eth)2503 static int mtk_hw_deinit(struct mtk_eth *eth)
2504 {
2505 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
2506 return 0;
2507
2508 mtk_clk_disable(eth);
2509
2510 pm_runtime_put_sync(eth->dev);
2511 pm_runtime_disable(eth->dev);
2512
2513 return 0;
2514 }
2515
mtk_init(struct net_device * dev)2516 static int __init mtk_init(struct net_device *dev)
2517 {
2518 struct mtk_mac *mac = netdev_priv(dev);
2519 struct mtk_eth *eth = mac->hw;
2520 const char *mac_addr;
2521
2522 mac_addr = of_get_mac_address(mac->of_node);
2523 if (!IS_ERR(mac_addr))
2524 ether_addr_copy(dev->dev_addr, mac_addr);
2525
2526 /* If the mac address is invalid, use random mac address */
2527 if (!is_valid_ether_addr(dev->dev_addr)) {
2528 eth_hw_addr_random(dev);
2529 dev_err(eth->dev, "generated random MAC address %pM\n",
2530 dev->dev_addr);
2531 }
2532
2533 return 0;
2534 }
2535
mtk_uninit(struct net_device * dev)2536 static void mtk_uninit(struct net_device *dev)
2537 {
2538 struct mtk_mac *mac = netdev_priv(dev);
2539 struct mtk_eth *eth = mac->hw;
2540
2541 phylink_disconnect_phy(mac->phylink);
2542 mtk_tx_irq_disable(eth, ~0);
2543 mtk_rx_irq_disable(eth, ~0);
2544 }
2545
mtk_do_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)2546 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2547 {
2548 struct mtk_mac *mac = netdev_priv(dev);
2549
2550 switch (cmd) {
2551 case SIOCGMIIPHY:
2552 case SIOCGMIIREG:
2553 case SIOCSMIIREG:
2554 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
2555 default:
2556 break;
2557 }
2558
2559 return -EOPNOTSUPP;
2560 }
2561
mtk_pending_work(struct work_struct * work)2562 static void mtk_pending_work(struct work_struct *work)
2563 {
2564 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2565 int err, i;
2566 unsigned long restart = 0;
2567
2568 rtnl_lock();
2569
2570 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2571
2572 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
2573 cpu_relax();
2574
2575 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2576 /* stop all devices to make sure that dma is properly shut down */
2577 for (i = 0; i < MTK_MAC_COUNT; i++) {
2578 if (!eth->netdev[i])
2579 continue;
2580 mtk_stop(eth->netdev[i]);
2581 __set_bit(i, &restart);
2582 }
2583 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2584
2585 /* restart underlying hardware such as power, clock, pin mux
2586 * and the connected phy
2587 */
2588 mtk_hw_deinit(eth);
2589
2590 if (eth->dev->pins)
2591 pinctrl_select_state(eth->dev->pins->p,
2592 eth->dev->pins->default_state);
2593 mtk_hw_init(eth);
2594
2595 /* restart DMA and enable IRQs */
2596 for (i = 0; i < MTK_MAC_COUNT; i++) {
2597 if (!test_bit(i, &restart))
2598 continue;
2599 err = mtk_open(eth->netdev[i]);
2600 if (err) {
2601 netif_alert(eth, ifup, eth->netdev[i],
2602 "Driver up/down cycle failed, closing device.\n");
2603 dev_close(eth->netdev[i]);
2604 }
2605 }
2606
2607 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2608
2609 clear_bit_unlock(MTK_RESETTING, ð->state);
2610
2611 rtnl_unlock();
2612 }
2613
mtk_free_dev(struct mtk_eth * eth)2614 static int mtk_free_dev(struct mtk_eth *eth)
2615 {
2616 int i;
2617
2618 for (i = 0; i < MTK_MAC_COUNT; i++) {
2619 if (!eth->netdev[i])
2620 continue;
2621 free_netdev(eth->netdev[i]);
2622 }
2623
2624 return 0;
2625 }
2626
mtk_unreg_dev(struct mtk_eth * eth)2627 static int mtk_unreg_dev(struct mtk_eth *eth)
2628 {
2629 int i;
2630
2631 for (i = 0; i < MTK_MAC_COUNT; i++) {
2632 if (!eth->netdev[i])
2633 continue;
2634 unregister_netdev(eth->netdev[i]);
2635 }
2636
2637 return 0;
2638 }
2639
mtk_cleanup(struct mtk_eth * eth)2640 static int mtk_cleanup(struct mtk_eth *eth)
2641 {
2642 mtk_unreg_dev(eth);
2643 mtk_free_dev(eth);
2644 cancel_work_sync(ð->pending_work);
2645
2646 return 0;
2647 }
2648
mtk_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * cmd)2649 static int mtk_get_link_ksettings(struct net_device *ndev,
2650 struct ethtool_link_ksettings *cmd)
2651 {
2652 struct mtk_mac *mac = netdev_priv(ndev);
2653
2654 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2655 return -EBUSY;
2656
2657 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
2658 }
2659
mtk_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * cmd)2660 static int mtk_set_link_ksettings(struct net_device *ndev,
2661 const struct ethtool_link_ksettings *cmd)
2662 {
2663 struct mtk_mac *mac = netdev_priv(ndev);
2664
2665 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2666 return -EBUSY;
2667
2668 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
2669 }
2670
mtk_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)2671 static void mtk_get_drvinfo(struct net_device *dev,
2672 struct ethtool_drvinfo *info)
2673 {
2674 struct mtk_mac *mac = netdev_priv(dev);
2675
2676 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2677 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2678 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2679 }
2680
mtk_get_msglevel(struct net_device * dev)2681 static u32 mtk_get_msglevel(struct net_device *dev)
2682 {
2683 struct mtk_mac *mac = netdev_priv(dev);
2684
2685 return mac->hw->msg_enable;
2686 }
2687
mtk_set_msglevel(struct net_device * dev,u32 value)2688 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2689 {
2690 struct mtk_mac *mac = netdev_priv(dev);
2691
2692 mac->hw->msg_enable = value;
2693 }
2694
mtk_nway_reset(struct net_device * dev)2695 static int mtk_nway_reset(struct net_device *dev)
2696 {
2697 struct mtk_mac *mac = netdev_priv(dev);
2698
2699 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2700 return -EBUSY;
2701
2702 if (!mac->phylink)
2703 return -ENOTSUPP;
2704
2705 return phylink_ethtool_nway_reset(mac->phylink);
2706 }
2707
mtk_get_strings(struct net_device * dev,u32 stringset,u8 * data)2708 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2709 {
2710 int i;
2711
2712 switch (stringset) {
2713 case ETH_SS_STATS:
2714 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2715 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2716 data += ETH_GSTRING_LEN;
2717 }
2718 break;
2719 }
2720 }
2721
mtk_get_sset_count(struct net_device * dev,int sset)2722 static int mtk_get_sset_count(struct net_device *dev, int sset)
2723 {
2724 switch (sset) {
2725 case ETH_SS_STATS:
2726 return ARRAY_SIZE(mtk_ethtool_stats);
2727 default:
2728 return -EOPNOTSUPP;
2729 }
2730 }
2731
mtk_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2732 static void mtk_get_ethtool_stats(struct net_device *dev,
2733 struct ethtool_stats *stats, u64 *data)
2734 {
2735 struct mtk_mac *mac = netdev_priv(dev);
2736 struct mtk_hw_stats *hwstats = mac->hw_stats;
2737 u64 *data_src, *data_dst;
2738 unsigned int start;
2739 int i;
2740
2741 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2742 return;
2743
2744 if (netif_running(dev) && netif_device_present(dev)) {
2745 if (spin_trylock_bh(&hwstats->stats_lock)) {
2746 mtk_stats_update_mac(mac);
2747 spin_unlock_bh(&hwstats->stats_lock);
2748 }
2749 }
2750
2751 data_src = (u64 *)hwstats;
2752
2753 do {
2754 data_dst = data;
2755 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2756
2757 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2758 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2759 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2760 }
2761
mtk_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2762 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2763 u32 *rule_locs)
2764 {
2765 int ret = -EOPNOTSUPP;
2766
2767 switch (cmd->cmd) {
2768 case ETHTOOL_GRXRINGS:
2769 if (dev->hw_features & NETIF_F_LRO) {
2770 cmd->data = MTK_MAX_RX_RING_NUM;
2771 ret = 0;
2772 }
2773 break;
2774 case ETHTOOL_GRXCLSRLCNT:
2775 if (dev->hw_features & NETIF_F_LRO) {
2776 struct mtk_mac *mac = netdev_priv(dev);
2777
2778 cmd->rule_cnt = mac->hwlro_ip_cnt;
2779 ret = 0;
2780 }
2781 break;
2782 case ETHTOOL_GRXCLSRULE:
2783 if (dev->hw_features & NETIF_F_LRO)
2784 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2785 break;
2786 case ETHTOOL_GRXCLSRLALL:
2787 if (dev->hw_features & NETIF_F_LRO)
2788 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2789 rule_locs);
2790 break;
2791 default:
2792 break;
2793 }
2794
2795 return ret;
2796 }
2797
mtk_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2798 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2799 {
2800 int ret = -EOPNOTSUPP;
2801
2802 switch (cmd->cmd) {
2803 case ETHTOOL_SRXCLSRLINS:
2804 if (dev->hw_features & NETIF_F_LRO)
2805 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2806 break;
2807 case ETHTOOL_SRXCLSRLDEL:
2808 if (dev->hw_features & NETIF_F_LRO)
2809 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2810 break;
2811 default:
2812 break;
2813 }
2814
2815 return ret;
2816 }
2817
2818 static const struct ethtool_ops mtk_ethtool_ops = {
2819 .get_link_ksettings = mtk_get_link_ksettings,
2820 .set_link_ksettings = mtk_set_link_ksettings,
2821 .get_drvinfo = mtk_get_drvinfo,
2822 .get_msglevel = mtk_get_msglevel,
2823 .set_msglevel = mtk_set_msglevel,
2824 .nway_reset = mtk_nway_reset,
2825 .get_link = ethtool_op_get_link,
2826 .get_strings = mtk_get_strings,
2827 .get_sset_count = mtk_get_sset_count,
2828 .get_ethtool_stats = mtk_get_ethtool_stats,
2829 .get_rxnfc = mtk_get_rxnfc,
2830 .set_rxnfc = mtk_set_rxnfc,
2831 };
2832
2833 static const struct net_device_ops mtk_netdev_ops = {
2834 .ndo_init = mtk_init,
2835 .ndo_uninit = mtk_uninit,
2836 .ndo_open = mtk_open,
2837 .ndo_stop = mtk_stop,
2838 .ndo_start_xmit = mtk_start_xmit,
2839 .ndo_set_mac_address = mtk_set_mac_address,
2840 .ndo_validate_addr = eth_validate_addr,
2841 .ndo_do_ioctl = mtk_do_ioctl,
2842 .ndo_tx_timeout = mtk_tx_timeout,
2843 .ndo_get_stats64 = mtk_get_stats64,
2844 .ndo_fix_features = mtk_fix_features,
2845 .ndo_set_features = mtk_set_features,
2846 #ifdef CONFIG_NET_POLL_CONTROLLER
2847 .ndo_poll_controller = mtk_poll_controller,
2848 #endif
2849 };
2850
mtk_add_mac(struct mtk_eth * eth,struct device_node * np)2851 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2852 {
2853 const __be32 *_id = of_get_property(np, "reg", NULL);
2854 phy_interface_t phy_mode;
2855 struct phylink *phylink;
2856 struct mtk_mac *mac;
2857 int id, err;
2858
2859 if (!_id) {
2860 dev_err(eth->dev, "missing mac id\n");
2861 return -EINVAL;
2862 }
2863
2864 id = be32_to_cpup(_id);
2865 if (id >= MTK_MAC_COUNT) {
2866 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2867 return -EINVAL;
2868 }
2869
2870 if (eth->netdev[id]) {
2871 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2872 return -EINVAL;
2873 }
2874
2875 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2876 if (!eth->netdev[id]) {
2877 dev_err(eth->dev, "alloc_etherdev failed\n");
2878 return -ENOMEM;
2879 }
2880 mac = netdev_priv(eth->netdev[id]);
2881 eth->mac[id] = mac;
2882 mac->id = id;
2883 mac->hw = eth;
2884 mac->of_node = np;
2885
2886 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2887 mac->hwlro_ip_cnt = 0;
2888
2889 mac->hw_stats = devm_kzalloc(eth->dev,
2890 sizeof(*mac->hw_stats),
2891 GFP_KERNEL);
2892 if (!mac->hw_stats) {
2893 dev_err(eth->dev, "failed to allocate counter memory\n");
2894 err = -ENOMEM;
2895 goto free_netdev;
2896 }
2897 spin_lock_init(&mac->hw_stats->stats_lock);
2898 u64_stats_init(&mac->hw_stats->syncp);
2899 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2900
2901 /* phylink create */
2902 err = of_get_phy_mode(np, &phy_mode);
2903 if (err) {
2904 dev_err(eth->dev, "incorrect phy-mode\n");
2905 goto free_netdev;
2906 }
2907
2908 /* mac config is not set */
2909 mac->interface = PHY_INTERFACE_MODE_NA;
2910 mac->mode = MLO_AN_PHY;
2911 mac->speed = SPEED_UNKNOWN;
2912
2913 mac->phylink_config.dev = ð->netdev[id]->dev;
2914 mac->phylink_config.type = PHYLINK_NETDEV;
2915
2916 phylink = phylink_create(&mac->phylink_config,
2917 of_fwnode_handle(mac->of_node),
2918 phy_mode, &mtk_phylink_ops);
2919 if (IS_ERR(phylink)) {
2920 err = PTR_ERR(phylink);
2921 goto free_netdev;
2922 }
2923
2924 mac->phylink = phylink;
2925
2926 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2927 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2928 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2929 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2930
2931 eth->netdev[id]->hw_features = eth->soc->hw_features;
2932 if (eth->hwlro)
2933 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2934
2935 eth->netdev[id]->vlan_features = eth->soc->hw_features &
2936 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2937 eth->netdev[id]->features |= eth->soc->hw_features;
2938 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2939
2940 eth->netdev[id]->irq = eth->irq[0];
2941 eth->netdev[id]->dev.of_node = np;
2942
2943 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
2944
2945 return 0;
2946
2947 free_netdev:
2948 free_netdev(eth->netdev[id]);
2949 return err;
2950 }
2951
mtk_probe(struct platform_device * pdev)2952 static int mtk_probe(struct platform_device *pdev)
2953 {
2954 struct device_node *mac_np;
2955 struct mtk_eth *eth;
2956 int err, i;
2957
2958 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2959 if (!eth)
2960 return -ENOMEM;
2961
2962 eth->soc = of_device_get_match_data(&pdev->dev);
2963
2964 eth->dev = &pdev->dev;
2965 eth->base = devm_platform_ioremap_resource(pdev, 0);
2966 if (IS_ERR(eth->base))
2967 return PTR_ERR(eth->base);
2968
2969 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2970 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK;
2971 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS;
2972 } else {
2973 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK;
2974 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS;
2975 }
2976
2977 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2978 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA;
2979 eth->ip_align = NET_IP_ALIGN;
2980 } else {
2981 eth->rx_dma_l4_valid = RX_DMA_L4_VALID;
2982 }
2983
2984 spin_lock_init(ð->page_lock);
2985 spin_lock_init(ð->tx_irq_lock);
2986 spin_lock_init(ð->rx_irq_lock);
2987
2988 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2989 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2990 "mediatek,ethsys");
2991 if (IS_ERR(eth->ethsys)) {
2992 dev_err(&pdev->dev, "no ethsys regmap found\n");
2993 return PTR_ERR(eth->ethsys);
2994 }
2995 }
2996
2997 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
2998 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2999 "mediatek,infracfg");
3000 if (IS_ERR(eth->infra)) {
3001 dev_err(&pdev->dev, "no infracfg regmap found\n");
3002 return PTR_ERR(eth->infra);
3003 }
3004 }
3005
3006 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
3007 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
3008 GFP_KERNEL);
3009 if (!eth->sgmii)
3010 return -ENOMEM;
3011
3012 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
3013 eth->soc->ana_rgc3);
3014
3015 if (err)
3016 return err;
3017 }
3018
3019 if (eth->soc->required_pctl) {
3020 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
3021 "mediatek,pctl");
3022 if (IS_ERR(eth->pctl)) {
3023 dev_err(&pdev->dev, "no pctl regmap found\n");
3024 return PTR_ERR(eth->pctl);
3025 }
3026 }
3027
3028 for (i = 0; i < 3; i++) {
3029 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
3030 eth->irq[i] = eth->irq[0];
3031 else
3032 eth->irq[i] = platform_get_irq(pdev, i);
3033 if (eth->irq[i] < 0) {
3034 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
3035 return -ENXIO;
3036 }
3037 }
3038 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
3039 eth->clks[i] = devm_clk_get(eth->dev,
3040 mtk_clks_source_name[i]);
3041 if (IS_ERR(eth->clks[i])) {
3042 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
3043 return -EPROBE_DEFER;
3044 if (eth->soc->required_clks & BIT(i)) {
3045 dev_err(&pdev->dev, "clock %s not found\n",
3046 mtk_clks_source_name[i]);
3047 return -EINVAL;
3048 }
3049 eth->clks[i] = NULL;
3050 }
3051 }
3052
3053 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
3054 INIT_WORK(ð->pending_work, mtk_pending_work);
3055
3056 err = mtk_hw_init(eth);
3057 if (err)
3058 return err;
3059
3060 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
3061
3062 for_each_child_of_node(pdev->dev.of_node, mac_np) {
3063 if (!of_device_is_compatible(mac_np,
3064 "mediatek,eth-mac"))
3065 continue;
3066
3067 if (!of_device_is_available(mac_np))
3068 continue;
3069
3070 err = mtk_add_mac(eth, mac_np);
3071 if (err) {
3072 of_node_put(mac_np);
3073 goto err_deinit_hw;
3074 }
3075 }
3076
3077 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
3078 err = devm_request_irq(eth->dev, eth->irq[0],
3079 mtk_handle_irq, 0,
3080 dev_name(eth->dev), eth);
3081 } else {
3082 err = devm_request_irq(eth->dev, eth->irq[1],
3083 mtk_handle_irq_tx, 0,
3084 dev_name(eth->dev), eth);
3085 if (err)
3086 goto err_free_dev;
3087
3088 err = devm_request_irq(eth->dev, eth->irq[2],
3089 mtk_handle_irq_rx, 0,
3090 dev_name(eth->dev), eth);
3091 }
3092 if (err)
3093 goto err_free_dev;
3094
3095 /* No MT7628/88 support yet */
3096 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3097 err = mtk_mdio_init(eth);
3098 if (err)
3099 goto err_free_dev;
3100 }
3101
3102 for (i = 0; i < MTK_MAX_DEVS; i++) {
3103 if (!eth->netdev[i])
3104 continue;
3105
3106 err = register_netdev(eth->netdev[i]);
3107 if (err) {
3108 dev_err(eth->dev, "error bringing up device\n");
3109 goto err_deinit_mdio;
3110 } else
3111 netif_info(eth, probe, eth->netdev[i],
3112 "mediatek frame engine at 0x%08lx, irq %d\n",
3113 eth->netdev[i]->base_addr, eth->irq[0]);
3114 }
3115
3116 /* we run 2 devices on the same DMA ring so we need a dummy device
3117 * for NAPI to work
3118 */
3119 init_dummy_netdev(ð->dummy_dev);
3120 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx,
3121 MTK_NAPI_WEIGHT);
3122 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx,
3123 MTK_NAPI_WEIGHT);
3124
3125 platform_set_drvdata(pdev, eth);
3126
3127 return 0;
3128
3129 err_deinit_mdio:
3130 mtk_mdio_cleanup(eth);
3131 err_free_dev:
3132 mtk_free_dev(eth);
3133 err_deinit_hw:
3134 mtk_hw_deinit(eth);
3135
3136 return err;
3137 }
3138
mtk_remove(struct platform_device * pdev)3139 static int mtk_remove(struct platform_device *pdev)
3140 {
3141 struct mtk_eth *eth = platform_get_drvdata(pdev);
3142 struct mtk_mac *mac;
3143 int i;
3144
3145 /* stop all devices to make sure that dma is properly shut down */
3146 for (i = 0; i < MTK_MAC_COUNT; i++) {
3147 if (!eth->netdev[i])
3148 continue;
3149 mtk_stop(eth->netdev[i]);
3150 mac = netdev_priv(eth->netdev[i]);
3151 phylink_disconnect_phy(mac->phylink);
3152 }
3153
3154 mtk_hw_deinit(eth);
3155
3156 netif_napi_del(ð->tx_napi);
3157 netif_napi_del(ð->rx_napi);
3158 mtk_cleanup(eth);
3159 mtk_mdio_cleanup(eth);
3160
3161 return 0;
3162 }
3163
3164 static const struct mtk_soc_data mt2701_data = {
3165 .caps = MT7623_CAPS | MTK_HWLRO,
3166 .hw_features = MTK_HW_FEATURES,
3167 .required_clks = MT7623_CLKS_BITMAP,
3168 .required_pctl = true,
3169 };
3170
3171 static const struct mtk_soc_data mt7621_data = {
3172 .caps = MT7621_CAPS,
3173 .hw_features = MTK_HW_FEATURES,
3174 .required_clks = MT7621_CLKS_BITMAP,
3175 .required_pctl = false,
3176 };
3177
3178 static const struct mtk_soc_data mt7622_data = {
3179 .ana_rgc3 = 0x2028,
3180 .caps = MT7622_CAPS | MTK_HWLRO,
3181 .hw_features = MTK_HW_FEATURES,
3182 .required_clks = MT7622_CLKS_BITMAP,
3183 .required_pctl = false,
3184 };
3185
3186 static const struct mtk_soc_data mt7623_data = {
3187 .caps = MT7623_CAPS | MTK_HWLRO,
3188 .hw_features = MTK_HW_FEATURES,
3189 .required_clks = MT7623_CLKS_BITMAP,
3190 .required_pctl = true,
3191 };
3192
3193 static const struct mtk_soc_data mt7629_data = {
3194 .ana_rgc3 = 0x128,
3195 .caps = MT7629_CAPS | MTK_HWLRO,
3196 .hw_features = MTK_HW_FEATURES,
3197 .required_clks = MT7629_CLKS_BITMAP,
3198 .required_pctl = false,
3199 };
3200
3201 static const struct mtk_soc_data rt5350_data = {
3202 .caps = MT7628_CAPS,
3203 .hw_features = MTK_HW_FEATURES_MT7628,
3204 .required_clks = MT7628_CLKS_BITMAP,
3205 .required_pctl = false,
3206 };
3207
3208 const struct of_device_id of_mtk_match[] = {
3209 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
3210 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
3211 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
3212 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
3213 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
3214 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
3215 {},
3216 };
3217 MODULE_DEVICE_TABLE(of, of_mtk_match);
3218
3219 static struct platform_driver mtk_driver = {
3220 .probe = mtk_probe,
3221 .remove = mtk_remove,
3222 .driver = {
3223 .name = "mtk_soc_eth",
3224 .of_match_table = of_mtk_match,
3225 },
3226 };
3227
3228 module_platform_driver(mtk_driver);
3229
3230 MODULE_LICENSE("GPL");
3231 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3232 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
3233