1*4882a593Smuzhiyun // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2*4882a593Smuzhiyun /* Copyright (c) 2019-2020 Marvell International Ltd. All rights reserved */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/circ_buf.h>
5*4882a593Smuzhiyun #include <linux/device.h>
6*4882a593Smuzhiyun #include <linux/firmware.h>
7*4882a593Smuzhiyun #include <linux/iopoll.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/pci.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "prestera.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define PRESTERA_MSG_MAX_SIZE 1500
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define PRESTERA_SUPP_FW_MAJ_VER 2
17*4882a593Smuzhiyun #define PRESTERA_SUPP_FW_MIN_VER 0
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define PRESTERA_FW_PATH_FMT "mrvl/prestera/mvsw_prestera_fw-v%u.%u.img"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define PRESTERA_FW_HDR_MAGIC 0x351D9D06
22*4882a593Smuzhiyun #define PRESTERA_FW_DL_TIMEOUT_MS 50000
23*4882a593Smuzhiyun #define PRESTERA_FW_BLK_SZ 1024
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define PRESTERA_FW_VER_MAJ_MUL 1000000
26*4882a593Smuzhiyun #define PRESTERA_FW_VER_MIN_MUL 1000
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define PRESTERA_FW_VER_MAJ(v) ((v) / PRESTERA_FW_VER_MAJ_MUL)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define PRESTERA_FW_VER_MIN(v) \
31*4882a593Smuzhiyun (((v) - (PRESTERA_FW_VER_MAJ(v) * PRESTERA_FW_VER_MAJ_MUL)) / \
32*4882a593Smuzhiyun PRESTERA_FW_VER_MIN_MUL)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define PRESTERA_FW_VER_PATCH(v) \
35*4882a593Smuzhiyun ((v) - (PRESTERA_FW_VER_MAJ(v) * PRESTERA_FW_VER_MAJ_MUL) - \
36*4882a593Smuzhiyun (PRESTERA_FW_VER_MIN(v) * PRESTERA_FW_VER_MIN_MUL))
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun enum prestera_pci_bar_t {
39*4882a593Smuzhiyun PRESTERA_PCI_BAR_FW = 2,
40*4882a593Smuzhiyun PRESTERA_PCI_BAR_PP = 4,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct prestera_fw_header {
44*4882a593Smuzhiyun __be32 magic_number;
45*4882a593Smuzhiyun __be32 version_value;
46*4882a593Smuzhiyun u8 reserved[8];
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct prestera_ldr_regs {
50*4882a593Smuzhiyun u32 ldr_ready;
51*4882a593Smuzhiyun u32 pad1;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun u32 ldr_img_size;
54*4882a593Smuzhiyun u32 ldr_ctl_flags;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun u32 ldr_buf_offs;
57*4882a593Smuzhiyun u32 ldr_buf_size;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun u32 ldr_buf_rd;
60*4882a593Smuzhiyun u32 pad2;
61*4882a593Smuzhiyun u32 ldr_buf_wr;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun u32 ldr_status;
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define PRESTERA_LDR_REG_OFFSET(f) offsetof(struct prestera_ldr_regs, f)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define PRESTERA_LDR_READY_MAGIC 0xf00dfeed
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define PRESTERA_LDR_STATUS_IMG_DL BIT(0)
71*4882a593Smuzhiyun #define PRESTERA_LDR_STATUS_START_FW BIT(1)
72*4882a593Smuzhiyun #define PRESTERA_LDR_STATUS_INVALID_IMG BIT(2)
73*4882a593Smuzhiyun #define PRESTERA_LDR_STATUS_NOMEM BIT(3)
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define PRESTERA_LDR_REG_BASE(fw) ((fw)->ldr_regs)
76*4882a593Smuzhiyun #define PRESTERA_LDR_REG_ADDR(fw, reg) (PRESTERA_LDR_REG_BASE(fw) + (reg))
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* fw loader registers */
79*4882a593Smuzhiyun #define PRESTERA_LDR_READY_REG PRESTERA_LDR_REG_OFFSET(ldr_ready)
80*4882a593Smuzhiyun #define PRESTERA_LDR_IMG_SIZE_REG PRESTERA_LDR_REG_OFFSET(ldr_img_size)
81*4882a593Smuzhiyun #define PRESTERA_LDR_CTL_REG PRESTERA_LDR_REG_OFFSET(ldr_ctl_flags)
82*4882a593Smuzhiyun #define PRESTERA_LDR_BUF_SIZE_REG PRESTERA_LDR_REG_OFFSET(ldr_buf_size)
83*4882a593Smuzhiyun #define PRESTERA_LDR_BUF_OFFS_REG PRESTERA_LDR_REG_OFFSET(ldr_buf_offs)
84*4882a593Smuzhiyun #define PRESTERA_LDR_BUF_RD_REG PRESTERA_LDR_REG_OFFSET(ldr_buf_rd)
85*4882a593Smuzhiyun #define PRESTERA_LDR_BUF_WR_REG PRESTERA_LDR_REG_OFFSET(ldr_buf_wr)
86*4882a593Smuzhiyun #define PRESTERA_LDR_STATUS_REG PRESTERA_LDR_REG_OFFSET(ldr_status)
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define PRESTERA_LDR_CTL_DL_START BIT(0)
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define PRESTERA_EVT_QNUM_MAX 4
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct prestera_fw_evtq_regs {
93*4882a593Smuzhiyun u32 rd_idx;
94*4882a593Smuzhiyun u32 pad1;
95*4882a593Smuzhiyun u32 wr_idx;
96*4882a593Smuzhiyun u32 pad2;
97*4882a593Smuzhiyun u32 offs;
98*4882a593Smuzhiyun u32 len;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct prestera_fw_regs {
102*4882a593Smuzhiyun u32 fw_ready;
103*4882a593Smuzhiyun u32 pad;
104*4882a593Smuzhiyun u32 cmd_offs;
105*4882a593Smuzhiyun u32 cmd_len;
106*4882a593Smuzhiyun u32 evt_offs;
107*4882a593Smuzhiyun u32 evt_qnum;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun u32 cmd_req_ctl;
110*4882a593Smuzhiyun u32 cmd_req_len;
111*4882a593Smuzhiyun u32 cmd_rcv_ctl;
112*4882a593Smuzhiyun u32 cmd_rcv_len;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun u32 fw_status;
115*4882a593Smuzhiyun u32 rx_status;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun struct prestera_fw_evtq_regs evtq_list[PRESTERA_EVT_QNUM_MAX];
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun #define PRESTERA_FW_REG_OFFSET(f) offsetof(struct prestera_fw_regs, f)
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #define PRESTERA_FW_READY_MAGIC 0xcafebabe
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* fw registers */
125*4882a593Smuzhiyun #define PRESTERA_FW_READY_REG PRESTERA_FW_REG_OFFSET(fw_ready)
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #define PRESTERA_CMD_BUF_OFFS_REG PRESTERA_FW_REG_OFFSET(cmd_offs)
128*4882a593Smuzhiyun #define PRESTERA_CMD_BUF_LEN_REG PRESTERA_FW_REG_OFFSET(cmd_len)
129*4882a593Smuzhiyun #define PRESTERA_EVT_BUF_OFFS_REG PRESTERA_FW_REG_OFFSET(evt_offs)
130*4882a593Smuzhiyun #define PRESTERA_EVT_QNUM_REG PRESTERA_FW_REG_OFFSET(evt_qnum)
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #define PRESTERA_CMD_REQ_CTL_REG PRESTERA_FW_REG_OFFSET(cmd_req_ctl)
133*4882a593Smuzhiyun #define PRESTERA_CMD_REQ_LEN_REG PRESTERA_FW_REG_OFFSET(cmd_req_len)
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #define PRESTERA_CMD_RCV_CTL_REG PRESTERA_FW_REG_OFFSET(cmd_rcv_ctl)
136*4882a593Smuzhiyun #define PRESTERA_CMD_RCV_LEN_REG PRESTERA_FW_REG_OFFSET(cmd_rcv_len)
137*4882a593Smuzhiyun #define PRESTERA_FW_STATUS_REG PRESTERA_FW_REG_OFFSET(fw_status)
138*4882a593Smuzhiyun #define PRESTERA_RX_STATUS_REG PRESTERA_FW_REG_OFFSET(rx_status)
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* PRESTERA_CMD_REQ_CTL_REG flags */
141*4882a593Smuzhiyun #define PRESTERA_CMD_F_REQ_SENT BIT(0)
142*4882a593Smuzhiyun #define PRESTERA_CMD_F_REPL_RCVD BIT(1)
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /* PRESTERA_CMD_RCV_CTL_REG flags */
145*4882a593Smuzhiyun #define PRESTERA_CMD_F_REPL_SENT BIT(0)
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun #define PRESTERA_EVTQ_REG_OFFSET(q, f) \
148*4882a593Smuzhiyun (PRESTERA_FW_REG_OFFSET(evtq_list) + \
149*4882a593Smuzhiyun (q) * sizeof(struct prestera_fw_evtq_regs) + \
150*4882a593Smuzhiyun offsetof(struct prestera_fw_evtq_regs, f))
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun #define PRESTERA_EVTQ_RD_IDX_REG(q) PRESTERA_EVTQ_REG_OFFSET(q, rd_idx)
153*4882a593Smuzhiyun #define PRESTERA_EVTQ_WR_IDX_REG(q) PRESTERA_EVTQ_REG_OFFSET(q, wr_idx)
154*4882a593Smuzhiyun #define PRESTERA_EVTQ_OFFS_REG(q) PRESTERA_EVTQ_REG_OFFSET(q, offs)
155*4882a593Smuzhiyun #define PRESTERA_EVTQ_LEN_REG(q) PRESTERA_EVTQ_REG_OFFSET(q, len)
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun #define PRESTERA_FW_REG_BASE(fw) ((fw)->dev.ctl_regs)
158*4882a593Smuzhiyun #define PRESTERA_FW_REG_ADDR(fw, reg) PRESTERA_FW_REG_BASE((fw)) + (reg)
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #define PRESTERA_FW_CMD_DEFAULT_WAIT_MS 30000
161*4882a593Smuzhiyun #define PRESTERA_FW_READY_WAIT_MS 20000
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun struct prestera_fw_evtq {
164*4882a593Smuzhiyun u8 __iomem *addr;
165*4882a593Smuzhiyun size_t len;
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun struct prestera_fw {
169*4882a593Smuzhiyun struct workqueue_struct *wq;
170*4882a593Smuzhiyun struct prestera_device dev;
171*4882a593Smuzhiyun u8 __iomem *ldr_regs;
172*4882a593Smuzhiyun u8 __iomem *ldr_ring_buf;
173*4882a593Smuzhiyun u32 ldr_buf_len;
174*4882a593Smuzhiyun u32 ldr_wr_idx;
175*4882a593Smuzhiyun struct mutex cmd_mtx; /* serialize access to dev->send_req */
176*4882a593Smuzhiyun size_t cmd_mbox_len;
177*4882a593Smuzhiyun u8 __iomem *cmd_mbox;
178*4882a593Smuzhiyun struct prestera_fw_evtq evt_queue[PRESTERA_EVT_QNUM_MAX];
179*4882a593Smuzhiyun u8 evt_qnum;
180*4882a593Smuzhiyun struct work_struct evt_work;
181*4882a593Smuzhiyun u8 __iomem *evt_buf;
182*4882a593Smuzhiyun u8 *evt_msg;
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun static int prestera_fw_load(struct prestera_fw *fw);
186*4882a593Smuzhiyun
prestera_fw_write(struct prestera_fw * fw,u32 reg,u32 val)187*4882a593Smuzhiyun static void prestera_fw_write(struct prestera_fw *fw, u32 reg, u32 val)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun writel(val, PRESTERA_FW_REG_ADDR(fw, reg));
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
prestera_fw_read(struct prestera_fw * fw,u32 reg)192*4882a593Smuzhiyun static u32 prestera_fw_read(struct prestera_fw *fw, u32 reg)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun return readl(PRESTERA_FW_REG_ADDR(fw, reg));
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
prestera_fw_evtq_len(struct prestera_fw * fw,u8 qid)197*4882a593Smuzhiyun static u32 prestera_fw_evtq_len(struct prestera_fw *fw, u8 qid)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun return fw->evt_queue[qid].len;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
prestera_fw_evtq_avail(struct prestera_fw * fw,u8 qid)202*4882a593Smuzhiyun static u32 prestera_fw_evtq_avail(struct prestera_fw *fw, u8 qid)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun u32 wr_idx = prestera_fw_read(fw, PRESTERA_EVTQ_WR_IDX_REG(qid));
205*4882a593Smuzhiyun u32 rd_idx = prestera_fw_read(fw, PRESTERA_EVTQ_RD_IDX_REG(qid));
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun return CIRC_CNT(wr_idx, rd_idx, prestera_fw_evtq_len(fw, qid));
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
prestera_fw_evtq_rd_set(struct prestera_fw * fw,u8 qid,u32 idx)210*4882a593Smuzhiyun static void prestera_fw_evtq_rd_set(struct prestera_fw *fw,
211*4882a593Smuzhiyun u8 qid, u32 idx)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun u32 rd_idx = idx & (prestera_fw_evtq_len(fw, qid) - 1);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun prestera_fw_write(fw, PRESTERA_EVTQ_RD_IDX_REG(qid), rd_idx);
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
prestera_fw_evtq_buf(struct prestera_fw * fw,u8 qid)218*4882a593Smuzhiyun static u8 __iomem *prestera_fw_evtq_buf(struct prestera_fw *fw, u8 qid)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun return fw->evt_queue[qid].addr;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
prestera_fw_evtq_read32(struct prestera_fw * fw,u8 qid)223*4882a593Smuzhiyun static u32 prestera_fw_evtq_read32(struct prestera_fw *fw, u8 qid)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun u32 rd_idx = prestera_fw_read(fw, PRESTERA_EVTQ_RD_IDX_REG(qid));
226*4882a593Smuzhiyun u32 val;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun val = readl(prestera_fw_evtq_buf(fw, qid) + rd_idx);
229*4882a593Smuzhiyun prestera_fw_evtq_rd_set(fw, qid, rd_idx + 4);
230*4882a593Smuzhiyun return val;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
prestera_fw_evtq_read_buf(struct prestera_fw * fw,u8 qid,void * buf,size_t len)233*4882a593Smuzhiyun static ssize_t prestera_fw_evtq_read_buf(struct prestera_fw *fw,
234*4882a593Smuzhiyun u8 qid, void *buf, size_t len)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun u32 idx = prestera_fw_read(fw, PRESTERA_EVTQ_RD_IDX_REG(qid));
237*4882a593Smuzhiyun u8 __iomem *evtq_addr = prestera_fw_evtq_buf(fw, qid);
238*4882a593Smuzhiyun u32 *buf32 = buf;
239*4882a593Smuzhiyun int i;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun for (i = 0; i < len / 4; buf32++, i++) {
242*4882a593Smuzhiyun *buf32 = readl_relaxed(evtq_addr + idx);
243*4882a593Smuzhiyun idx = (idx + 4) & (prestera_fw_evtq_len(fw, qid) - 1);
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun prestera_fw_evtq_rd_set(fw, qid, idx);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun return i;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
prestera_fw_evtq_pick(struct prestera_fw * fw)251*4882a593Smuzhiyun static u8 prestera_fw_evtq_pick(struct prestera_fw *fw)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun int qid;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun for (qid = 0; qid < fw->evt_qnum; qid++) {
256*4882a593Smuzhiyun if (prestera_fw_evtq_avail(fw, qid) >= 4)
257*4882a593Smuzhiyun return qid;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun return PRESTERA_EVT_QNUM_MAX;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
prestera_fw_evt_work_fn(struct work_struct * work)263*4882a593Smuzhiyun static void prestera_fw_evt_work_fn(struct work_struct *work)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct prestera_fw *fw;
266*4882a593Smuzhiyun void *msg;
267*4882a593Smuzhiyun u8 qid;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun fw = container_of(work, struct prestera_fw, evt_work);
270*4882a593Smuzhiyun msg = fw->evt_msg;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun while ((qid = prestera_fw_evtq_pick(fw)) < PRESTERA_EVT_QNUM_MAX) {
273*4882a593Smuzhiyun u32 idx;
274*4882a593Smuzhiyun u32 len;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun len = prestera_fw_evtq_read32(fw, qid);
277*4882a593Smuzhiyun idx = prestera_fw_read(fw, PRESTERA_EVTQ_RD_IDX_REG(qid));
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun WARN_ON(prestera_fw_evtq_avail(fw, qid) < len);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun if (WARN_ON(len > PRESTERA_MSG_MAX_SIZE)) {
282*4882a593Smuzhiyun prestera_fw_evtq_rd_set(fw, qid, idx + len);
283*4882a593Smuzhiyun continue;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun prestera_fw_evtq_read_buf(fw, qid, msg, len);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun if (fw->dev.recv_msg)
289*4882a593Smuzhiyun fw->dev.recv_msg(&fw->dev, msg, len);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
prestera_fw_wait_reg32(struct prestera_fw * fw,u32 reg,u32 cmp,unsigned int waitms)293*4882a593Smuzhiyun static int prestera_fw_wait_reg32(struct prestera_fw *fw, u32 reg, u32 cmp,
294*4882a593Smuzhiyun unsigned int waitms)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun u8 __iomem *addr = PRESTERA_FW_REG_ADDR(fw, reg);
297*4882a593Smuzhiyun u32 val;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun return readl_poll_timeout(addr, val, cmp == val,
300*4882a593Smuzhiyun 1 * USEC_PER_MSEC, waitms * USEC_PER_MSEC);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
prestera_fw_cmd_send(struct prestera_fw * fw,void * in_msg,size_t in_size,void * out_msg,size_t out_size,unsigned int waitms)303*4882a593Smuzhiyun static int prestera_fw_cmd_send(struct prestera_fw *fw,
304*4882a593Smuzhiyun void *in_msg, size_t in_size,
305*4882a593Smuzhiyun void *out_msg, size_t out_size,
306*4882a593Smuzhiyun unsigned int waitms)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun u32 ret_size;
309*4882a593Smuzhiyun int err;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun if (!waitms)
312*4882a593Smuzhiyun waitms = PRESTERA_FW_CMD_DEFAULT_WAIT_MS;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun if (ALIGN(in_size, 4) > fw->cmd_mbox_len)
315*4882a593Smuzhiyun return -EMSGSIZE;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun /* wait for finish previous reply from FW */
318*4882a593Smuzhiyun err = prestera_fw_wait_reg32(fw, PRESTERA_CMD_RCV_CTL_REG, 0, 30);
319*4882a593Smuzhiyun if (err) {
320*4882a593Smuzhiyun dev_err(fw->dev.dev, "finish reply from FW is timed out\n");
321*4882a593Smuzhiyun return err;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun prestera_fw_write(fw, PRESTERA_CMD_REQ_LEN_REG, in_size);
325*4882a593Smuzhiyun memcpy_toio(fw->cmd_mbox, in_msg, in_size);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun prestera_fw_write(fw, PRESTERA_CMD_REQ_CTL_REG, PRESTERA_CMD_F_REQ_SENT);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun /* wait for reply from FW */
330*4882a593Smuzhiyun err = prestera_fw_wait_reg32(fw, PRESTERA_CMD_RCV_CTL_REG,
331*4882a593Smuzhiyun PRESTERA_CMD_F_REPL_SENT, waitms);
332*4882a593Smuzhiyun if (err) {
333*4882a593Smuzhiyun dev_err(fw->dev.dev, "reply from FW is timed out\n");
334*4882a593Smuzhiyun goto cmd_exit;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun ret_size = prestera_fw_read(fw, PRESTERA_CMD_RCV_LEN_REG);
338*4882a593Smuzhiyun if (ret_size > out_size) {
339*4882a593Smuzhiyun dev_err(fw->dev.dev, "ret_size (%u) > out_len(%zu)\n",
340*4882a593Smuzhiyun ret_size, out_size);
341*4882a593Smuzhiyun err = -EMSGSIZE;
342*4882a593Smuzhiyun goto cmd_exit;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun memcpy_fromio(out_msg, fw->cmd_mbox + in_size, ret_size);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun cmd_exit:
348*4882a593Smuzhiyun prestera_fw_write(fw, PRESTERA_CMD_REQ_CTL_REG, PRESTERA_CMD_F_REPL_RCVD);
349*4882a593Smuzhiyun return err;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
prestera_fw_send_req(struct prestera_device * dev,void * in_msg,size_t in_size,void * out_msg,size_t out_size,unsigned int waitms)352*4882a593Smuzhiyun static int prestera_fw_send_req(struct prestera_device *dev,
353*4882a593Smuzhiyun void *in_msg, size_t in_size, void *out_msg,
354*4882a593Smuzhiyun size_t out_size, unsigned int waitms)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun struct prestera_fw *fw;
357*4882a593Smuzhiyun ssize_t ret;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun fw = container_of(dev, struct prestera_fw, dev);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun mutex_lock(&fw->cmd_mtx);
362*4882a593Smuzhiyun ret = prestera_fw_cmd_send(fw, in_msg, in_size, out_msg, out_size, waitms);
363*4882a593Smuzhiyun mutex_unlock(&fw->cmd_mtx);
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun return ret;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
prestera_fw_init(struct prestera_fw * fw)368*4882a593Smuzhiyun static int prestera_fw_init(struct prestera_fw *fw)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun u8 __iomem *base;
371*4882a593Smuzhiyun int err;
372*4882a593Smuzhiyun u8 qid;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun fw->dev.send_req = prestera_fw_send_req;
375*4882a593Smuzhiyun fw->ldr_regs = fw->dev.ctl_regs;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun err = prestera_fw_load(fw);
378*4882a593Smuzhiyun if (err)
379*4882a593Smuzhiyun return err;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun err = prestera_fw_wait_reg32(fw, PRESTERA_FW_READY_REG,
382*4882a593Smuzhiyun PRESTERA_FW_READY_MAGIC,
383*4882a593Smuzhiyun PRESTERA_FW_READY_WAIT_MS);
384*4882a593Smuzhiyun if (err) {
385*4882a593Smuzhiyun dev_err(fw->dev.dev, "FW failed to start\n");
386*4882a593Smuzhiyun return err;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun base = fw->dev.ctl_regs;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun fw->cmd_mbox = base + prestera_fw_read(fw, PRESTERA_CMD_BUF_OFFS_REG);
392*4882a593Smuzhiyun fw->cmd_mbox_len = prestera_fw_read(fw, PRESTERA_CMD_BUF_LEN_REG);
393*4882a593Smuzhiyun mutex_init(&fw->cmd_mtx);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun fw->evt_buf = base + prestera_fw_read(fw, PRESTERA_EVT_BUF_OFFS_REG);
396*4882a593Smuzhiyun fw->evt_qnum = prestera_fw_read(fw, PRESTERA_EVT_QNUM_REG);
397*4882a593Smuzhiyun fw->evt_msg = kmalloc(PRESTERA_MSG_MAX_SIZE, GFP_KERNEL);
398*4882a593Smuzhiyun if (!fw->evt_msg)
399*4882a593Smuzhiyun return -ENOMEM;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun for (qid = 0; qid < fw->evt_qnum; qid++) {
402*4882a593Smuzhiyun u32 offs = prestera_fw_read(fw, PRESTERA_EVTQ_OFFS_REG(qid));
403*4882a593Smuzhiyun struct prestera_fw_evtq *evtq = &fw->evt_queue[qid];
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun evtq->len = prestera_fw_read(fw, PRESTERA_EVTQ_LEN_REG(qid));
406*4882a593Smuzhiyun evtq->addr = fw->evt_buf + offs;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun return 0;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
prestera_fw_uninit(struct prestera_fw * fw)412*4882a593Smuzhiyun static void prestera_fw_uninit(struct prestera_fw *fw)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun kfree(fw->evt_msg);
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
prestera_pci_irq_handler(int irq,void * dev_id)417*4882a593Smuzhiyun static irqreturn_t prestera_pci_irq_handler(int irq, void *dev_id)
418*4882a593Smuzhiyun {
419*4882a593Smuzhiyun struct prestera_fw *fw = dev_id;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun if (prestera_fw_read(fw, PRESTERA_RX_STATUS_REG)) {
422*4882a593Smuzhiyun prestera_fw_write(fw, PRESTERA_RX_STATUS_REG, 0);
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun if (fw->dev.recv_pkt)
425*4882a593Smuzhiyun fw->dev.recv_pkt(&fw->dev);
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun queue_work(fw->wq, &fw->evt_work);
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun return IRQ_HANDLED;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
prestera_ldr_write(struct prestera_fw * fw,u32 reg,u32 val)433*4882a593Smuzhiyun static void prestera_ldr_write(struct prestera_fw *fw, u32 reg, u32 val)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun writel(val, PRESTERA_LDR_REG_ADDR(fw, reg));
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
prestera_ldr_read(struct prestera_fw * fw,u32 reg)438*4882a593Smuzhiyun static u32 prestera_ldr_read(struct prestera_fw *fw, u32 reg)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun return readl(PRESTERA_LDR_REG_ADDR(fw, reg));
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
prestera_ldr_wait_reg32(struct prestera_fw * fw,u32 reg,u32 cmp,unsigned int waitms)443*4882a593Smuzhiyun static int prestera_ldr_wait_reg32(struct prestera_fw *fw,
444*4882a593Smuzhiyun u32 reg, u32 cmp, unsigned int waitms)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun u8 __iomem *addr = PRESTERA_LDR_REG_ADDR(fw, reg);
447*4882a593Smuzhiyun u32 val;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun return readl_poll_timeout(addr, val, cmp == val,
450*4882a593Smuzhiyun 10 * USEC_PER_MSEC, waitms * USEC_PER_MSEC);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
prestera_ldr_wait_buf(struct prestera_fw * fw,size_t len)453*4882a593Smuzhiyun static u32 prestera_ldr_wait_buf(struct prestera_fw *fw, size_t len)
454*4882a593Smuzhiyun {
455*4882a593Smuzhiyun u8 __iomem *addr = PRESTERA_LDR_REG_ADDR(fw, PRESTERA_LDR_BUF_RD_REG);
456*4882a593Smuzhiyun u32 buf_len = fw->ldr_buf_len;
457*4882a593Smuzhiyun u32 wr_idx = fw->ldr_wr_idx;
458*4882a593Smuzhiyun u32 rd_idx;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun return readl_poll_timeout(addr, rd_idx,
461*4882a593Smuzhiyun CIRC_SPACE(wr_idx, rd_idx, buf_len) >= len,
462*4882a593Smuzhiyun 1 * USEC_PER_MSEC, 100 * USEC_PER_MSEC);
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
prestera_ldr_wait_dl_finish(struct prestera_fw * fw)465*4882a593Smuzhiyun static int prestera_ldr_wait_dl_finish(struct prestera_fw *fw)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun u8 __iomem *addr = PRESTERA_LDR_REG_ADDR(fw, PRESTERA_LDR_STATUS_REG);
468*4882a593Smuzhiyun unsigned long mask = ~(PRESTERA_LDR_STATUS_IMG_DL);
469*4882a593Smuzhiyun u32 val;
470*4882a593Smuzhiyun int err;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun err = readl_poll_timeout(addr, val, val & mask, 10 * USEC_PER_MSEC,
473*4882a593Smuzhiyun PRESTERA_FW_DL_TIMEOUT_MS * USEC_PER_MSEC);
474*4882a593Smuzhiyun if (err) {
475*4882a593Smuzhiyun dev_err(fw->dev.dev, "Timeout to load FW img [state=%d]",
476*4882a593Smuzhiyun prestera_ldr_read(fw, PRESTERA_LDR_STATUS_REG));
477*4882a593Smuzhiyun return err;
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun return 0;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
prestera_ldr_wr_idx_move(struct prestera_fw * fw,unsigned int n)483*4882a593Smuzhiyun static void prestera_ldr_wr_idx_move(struct prestera_fw *fw, unsigned int n)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun fw->ldr_wr_idx = (fw->ldr_wr_idx + (n)) & (fw->ldr_buf_len - 1);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
prestera_ldr_wr_idx_commit(struct prestera_fw * fw)488*4882a593Smuzhiyun static void prestera_ldr_wr_idx_commit(struct prestera_fw *fw)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun prestera_ldr_write(fw, PRESTERA_LDR_BUF_WR_REG, fw->ldr_wr_idx);
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun
prestera_ldr_wr_ptr(struct prestera_fw * fw)493*4882a593Smuzhiyun static u8 __iomem *prestera_ldr_wr_ptr(struct prestera_fw *fw)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun return fw->ldr_ring_buf + fw->ldr_wr_idx;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
prestera_ldr_send(struct prestera_fw * fw,const u8 * buf,size_t len)498*4882a593Smuzhiyun static int prestera_ldr_send(struct prestera_fw *fw, const u8 *buf, size_t len)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun int err;
501*4882a593Smuzhiyun int i;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun err = prestera_ldr_wait_buf(fw, len);
504*4882a593Smuzhiyun if (err) {
505*4882a593Smuzhiyun dev_err(fw->dev.dev, "failed wait for sending firmware\n");
506*4882a593Smuzhiyun return err;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun for (i = 0; i < len; i += 4) {
510*4882a593Smuzhiyun writel_relaxed(*(u32 *)(buf + i), prestera_ldr_wr_ptr(fw));
511*4882a593Smuzhiyun prestera_ldr_wr_idx_move(fw, 4);
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun prestera_ldr_wr_idx_commit(fw);
515*4882a593Smuzhiyun return 0;
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun
prestera_ldr_fw_send(struct prestera_fw * fw,const char * img,u32 fw_size)518*4882a593Smuzhiyun static int prestera_ldr_fw_send(struct prestera_fw *fw,
519*4882a593Smuzhiyun const char *img, u32 fw_size)
520*4882a593Smuzhiyun {
521*4882a593Smuzhiyun u32 status;
522*4882a593Smuzhiyun u32 pos;
523*4882a593Smuzhiyun int err;
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun err = prestera_ldr_wait_reg32(fw, PRESTERA_LDR_STATUS_REG,
526*4882a593Smuzhiyun PRESTERA_LDR_STATUS_IMG_DL,
527*4882a593Smuzhiyun 5 * MSEC_PER_SEC);
528*4882a593Smuzhiyun if (err) {
529*4882a593Smuzhiyun dev_err(fw->dev.dev, "Loader is not ready to load image\n");
530*4882a593Smuzhiyun return err;
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun for (pos = 0; pos < fw_size; pos += PRESTERA_FW_BLK_SZ) {
534*4882a593Smuzhiyun if (pos + PRESTERA_FW_BLK_SZ > fw_size)
535*4882a593Smuzhiyun break;
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun err = prestera_ldr_send(fw, img + pos, PRESTERA_FW_BLK_SZ);
538*4882a593Smuzhiyun if (err)
539*4882a593Smuzhiyun return err;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun if (pos < fw_size) {
543*4882a593Smuzhiyun err = prestera_ldr_send(fw, img + pos, fw_size - pos);
544*4882a593Smuzhiyun if (err)
545*4882a593Smuzhiyun return err;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun err = prestera_ldr_wait_dl_finish(fw);
549*4882a593Smuzhiyun if (err)
550*4882a593Smuzhiyun return err;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun status = prestera_ldr_read(fw, PRESTERA_LDR_STATUS_REG);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun switch (status) {
555*4882a593Smuzhiyun case PRESTERA_LDR_STATUS_INVALID_IMG:
556*4882a593Smuzhiyun dev_err(fw->dev.dev, "FW img has bad CRC\n");
557*4882a593Smuzhiyun return -EINVAL;
558*4882a593Smuzhiyun case PRESTERA_LDR_STATUS_NOMEM:
559*4882a593Smuzhiyun dev_err(fw->dev.dev, "Loader has no enough mem\n");
560*4882a593Smuzhiyun return -ENOMEM;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun return 0;
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
prestera_fw_rev_parse(const struct prestera_fw_header * hdr,struct prestera_fw_rev * rev)566*4882a593Smuzhiyun static void prestera_fw_rev_parse(const struct prestera_fw_header *hdr,
567*4882a593Smuzhiyun struct prestera_fw_rev *rev)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun u32 version = be32_to_cpu(hdr->version_value);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun rev->maj = PRESTERA_FW_VER_MAJ(version);
572*4882a593Smuzhiyun rev->min = PRESTERA_FW_VER_MIN(version);
573*4882a593Smuzhiyun rev->sub = PRESTERA_FW_VER_PATCH(version);
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun
prestera_fw_rev_check(struct prestera_fw * fw)576*4882a593Smuzhiyun static int prestera_fw_rev_check(struct prestera_fw *fw)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun struct prestera_fw_rev *rev = &fw->dev.fw_rev;
579*4882a593Smuzhiyun u16 maj_supp = PRESTERA_SUPP_FW_MAJ_VER;
580*4882a593Smuzhiyun u16 min_supp = PRESTERA_SUPP_FW_MIN_VER;
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun if (rev->maj == maj_supp && rev->min >= min_supp)
583*4882a593Smuzhiyun return 0;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun dev_err(fw->dev.dev, "Driver supports FW version only '%u.%u.x'",
586*4882a593Smuzhiyun PRESTERA_SUPP_FW_MAJ_VER, PRESTERA_SUPP_FW_MIN_VER);
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun return -EINVAL;
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun
prestera_fw_hdr_parse(struct prestera_fw * fw,const struct firmware * img)591*4882a593Smuzhiyun static int prestera_fw_hdr_parse(struct prestera_fw *fw,
592*4882a593Smuzhiyun const struct firmware *img)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun struct prestera_fw_header *hdr = (struct prestera_fw_header *)img->data;
595*4882a593Smuzhiyun struct prestera_fw_rev *rev = &fw->dev.fw_rev;
596*4882a593Smuzhiyun u32 magic;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun magic = be32_to_cpu(hdr->magic_number);
599*4882a593Smuzhiyun if (magic != PRESTERA_FW_HDR_MAGIC) {
600*4882a593Smuzhiyun dev_err(fw->dev.dev, "FW img hdr magic is invalid");
601*4882a593Smuzhiyun return -EINVAL;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun prestera_fw_rev_parse(hdr, rev);
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun dev_info(fw->dev.dev, "FW version '%u.%u.%u'\n",
607*4882a593Smuzhiyun rev->maj, rev->min, rev->sub);
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun return prestera_fw_rev_check(fw);
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
prestera_fw_load(struct prestera_fw * fw)612*4882a593Smuzhiyun static int prestera_fw_load(struct prestera_fw *fw)
613*4882a593Smuzhiyun {
614*4882a593Smuzhiyun size_t hlen = sizeof(struct prestera_fw_header);
615*4882a593Smuzhiyun const struct firmware *f;
616*4882a593Smuzhiyun char fw_path[128];
617*4882a593Smuzhiyun int err;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun err = prestera_ldr_wait_reg32(fw, PRESTERA_LDR_READY_REG,
620*4882a593Smuzhiyun PRESTERA_LDR_READY_MAGIC,
621*4882a593Smuzhiyun 5 * MSEC_PER_SEC);
622*4882a593Smuzhiyun if (err) {
623*4882a593Smuzhiyun dev_err(fw->dev.dev, "waiting for FW loader is timed out");
624*4882a593Smuzhiyun return err;
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun fw->ldr_ring_buf = fw->ldr_regs +
628*4882a593Smuzhiyun prestera_ldr_read(fw, PRESTERA_LDR_BUF_OFFS_REG);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun fw->ldr_buf_len =
631*4882a593Smuzhiyun prestera_ldr_read(fw, PRESTERA_LDR_BUF_SIZE_REG);
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun fw->ldr_wr_idx = 0;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun snprintf(fw_path, sizeof(fw_path), PRESTERA_FW_PATH_FMT,
636*4882a593Smuzhiyun PRESTERA_SUPP_FW_MAJ_VER, PRESTERA_SUPP_FW_MIN_VER);
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun err = request_firmware_direct(&f, fw_path, fw->dev.dev);
639*4882a593Smuzhiyun if (err) {
640*4882a593Smuzhiyun dev_err(fw->dev.dev, "failed to request firmware file\n");
641*4882a593Smuzhiyun return err;
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun err = prestera_fw_hdr_parse(fw, f);
645*4882a593Smuzhiyun if (err) {
646*4882a593Smuzhiyun dev_err(fw->dev.dev, "FW image header is invalid\n");
647*4882a593Smuzhiyun goto out_release;
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun prestera_ldr_write(fw, PRESTERA_LDR_IMG_SIZE_REG, f->size - hlen);
651*4882a593Smuzhiyun prestera_ldr_write(fw, PRESTERA_LDR_CTL_REG, PRESTERA_LDR_CTL_DL_START);
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun dev_info(fw->dev.dev, "Loading %s ...", fw_path);
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun err = prestera_ldr_fw_send(fw, f->data + hlen, f->size - hlen);
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun out_release:
658*4882a593Smuzhiyun release_firmware(f);
659*4882a593Smuzhiyun return err;
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
prestera_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)662*4882a593Smuzhiyun static int prestera_pci_probe(struct pci_dev *pdev,
663*4882a593Smuzhiyun const struct pci_device_id *id)
664*4882a593Smuzhiyun {
665*4882a593Smuzhiyun const char *driver_name = pdev->driver->name;
666*4882a593Smuzhiyun struct prestera_fw *fw;
667*4882a593Smuzhiyun int err;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun err = pcim_enable_device(pdev);
670*4882a593Smuzhiyun if (err)
671*4882a593Smuzhiyun return err;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun err = pcim_iomap_regions(pdev, BIT(PRESTERA_PCI_BAR_FW) |
674*4882a593Smuzhiyun BIT(PRESTERA_PCI_BAR_PP),
675*4882a593Smuzhiyun pci_name(pdev));
676*4882a593Smuzhiyun if (err)
677*4882a593Smuzhiyun return err;
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(30));
680*4882a593Smuzhiyun if (err) {
681*4882a593Smuzhiyun dev_err(&pdev->dev, "fail to set DMA mask\n");
682*4882a593Smuzhiyun goto err_dma_mask;
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun pci_set_master(pdev);
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun fw = devm_kzalloc(&pdev->dev, sizeof(*fw), GFP_KERNEL);
688*4882a593Smuzhiyun if (!fw) {
689*4882a593Smuzhiyun err = -ENOMEM;
690*4882a593Smuzhiyun goto err_pci_dev_alloc;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun fw->dev.ctl_regs = pcim_iomap_table(pdev)[PRESTERA_PCI_BAR_FW];
694*4882a593Smuzhiyun fw->dev.pp_regs = pcim_iomap_table(pdev)[PRESTERA_PCI_BAR_PP];
695*4882a593Smuzhiyun fw->dev.dev = &pdev->dev;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun pci_set_drvdata(pdev, fw);
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun err = prestera_fw_init(fw);
700*4882a593Smuzhiyun if (err)
701*4882a593Smuzhiyun goto err_prestera_fw_init;
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun dev_info(fw->dev.dev, "Prestera FW is ready\n");
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun fw->wq = alloc_workqueue("prestera_fw_wq", WQ_HIGHPRI, 1);
706*4882a593Smuzhiyun if (!fw->wq) {
707*4882a593Smuzhiyun err = -ENOMEM;
708*4882a593Smuzhiyun goto err_wq_alloc;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun INIT_WORK(&fw->evt_work, prestera_fw_evt_work_fn);
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
714*4882a593Smuzhiyun if (err < 0) {
715*4882a593Smuzhiyun dev_err(&pdev->dev, "MSI IRQ init failed\n");
716*4882a593Smuzhiyun goto err_irq_alloc;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun err = request_irq(pci_irq_vector(pdev, 0), prestera_pci_irq_handler,
720*4882a593Smuzhiyun 0, driver_name, fw);
721*4882a593Smuzhiyun if (err) {
722*4882a593Smuzhiyun dev_err(&pdev->dev, "fail to request IRQ\n");
723*4882a593Smuzhiyun goto err_request_irq;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun err = prestera_device_register(&fw->dev);
727*4882a593Smuzhiyun if (err)
728*4882a593Smuzhiyun goto err_prestera_dev_register;
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun return 0;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun err_prestera_dev_register:
733*4882a593Smuzhiyun free_irq(pci_irq_vector(pdev, 0), fw);
734*4882a593Smuzhiyun err_request_irq:
735*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
736*4882a593Smuzhiyun err_irq_alloc:
737*4882a593Smuzhiyun destroy_workqueue(fw->wq);
738*4882a593Smuzhiyun err_wq_alloc:
739*4882a593Smuzhiyun prestera_fw_uninit(fw);
740*4882a593Smuzhiyun err_prestera_fw_init:
741*4882a593Smuzhiyun err_pci_dev_alloc:
742*4882a593Smuzhiyun err_dma_mask:
743*4882a593Smuzhiyun return err;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
prestera_pci_remove(struct pci_dev * pdev)746*4882a593Smuzhiyun static void prestera_pci_remove(struct pci_dev *pdev)
747*4882a593Smuzhiyun {
748*4882a593Smuzhiyun struct prestera_fw *fw = pci_get_drvdata(pdev);
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun prestera_device_unregister(&fw->dev);
751*4882a593Smuzhiyun free_irq(pci_irq_vector(pdev, 0), fw);
752*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
753*4882a593Smuzhiyun destroy_workqueue(fw->wq);
754*4882a593Smuzhiyun prestera_fw_uninit(fw);
755*4882a593Smuzhiyun }
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun static const struct pci_device_id prestera_pci_devices[] = {
758*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0xC804) },
759*4882a593Smuzhiyun { }
760*4882a593Smuzhiyun };
761*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, prestera_pci_devices);
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun static struct pci_driver prestera_pci_driver = {
764*4882a593Smuzhiyun .name = "Prestera DX",
765*4882a593Smuzhiyun .id_table = prestera_pci_devices,
766*4882a593Smuzhiyun .probe = prestera_pci_probe,
767*4882a593Smuzhiyun .remove = prestera_pci_remove,
768*4882a593Smuzhiyun };
769*4882a593Smuzhiyun module_pci_driver(prestera_pci_driver);
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
772*4882a593Smuzhiyun MODULE_DESCRIPTION("Marvell Prestera switch PCI interface");
773