1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _IXGBE_FCOE_H 5*4882a593Smuzhiyun #define _IXGBE_FCOE_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <scsi/fc/fc_fs.h> 8*4882a593Smuzhiyun #include <scsi/fc/fc_fcoe.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* shift bits within STAT fo FCSTAT */ 11*4882a593Smuzhiyun #define IXGBE_RXDADV_FCSTAT_SHIFT 4 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* ddp user buffer */ 14*4882a593Smuzhiyun #define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */ 15*4882a593Smuzhiyun #define IXGBE_FCPTR_ALIGN 16 16*4882a593Smuzhiyun #define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t)) 17*4882a593Smuzhiyun #define IXGBE_FCBUFF_4KB 0x0 18*4882a593Smuzhiyun #define IXGBE_FCBUFF_8KB 0x1 19*4882a593Smuzhiyun #define IXGBE_FCBUFF_16KB 0x2 20*4882a593Smuzhiyun #define IXGBE_FCBUFF_64KB 0x3 21*4882a593Smuzhiyun #define IXGBE_FCBUFF_MAX 65536 /* 64KB max */ 22*4882a593Smuzhiyun #define IXGBE_FCBUFF_MIN 4096 /* 4KB min */ 23*4882a593Smuzhiyun #define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */ 24*4882a593Smuzhiyun #define IXGBE_FCOE_DDP_MAX_X550 2048 /* 11 bits xid */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Default traffic class to use for FCoE */ 27*4882a593Smuzhiyun #define IXGBE_FCOE_DEFTC 3 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* fcerr */ 30*4882a593Smuzhiyun #define IXGBE_FCERR_BADCRC 0x00100000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* FCoE DDP for target mode */ 33*4882a593Smuzhiyun #define __IXGBE_FCOE_TARGET 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct ixgbe_fcoe_ddp { 36*4882a593Smuzhiyun int len; 37*4882a593Smuzhiyun u32 err; 38*4882a593Smuzhiyun unsigned int sgc; 39*4882a593Smuzhiyun struct scatterlist *sgl; 40*4882a593Smuzhiyun dma_addr_t udp; 41*4882a593Smuzhiyun u64 *udl; 42*4882a593Smuzhiyun struct dma_pool *pool; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* per cpu variables */ 46*4882a593Smuzhiyun struct ixgbe_fcoe_ddp_pool { 47*4882a593Smuzhiyun struct dma_pool *pool; 48*4882a593Smuzhiyun u64 noddp; 49*4882a593Smuzhiyun u64 noddp_ext_buff; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct ixgbe_fcoe { 53*4882a593Smuzhiyun struct ixgbe_fcoe_ddp_pool __percpu *ddp_pool; 54*4882a593Smuzhiyun atomic_t refcnt; 55*4882a593Smuzhiyun spinlock_t lock; 56*4882a593Smuzhiyun struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX_X550]; 57*4882a593Smuzhiyun void *extra_ddp_buffer; 58*4882a593Smuzhiyun dma_addr_t extra_ddp_buffer_dma; 59*4882a593Smuzhiyun unsigned long mode; 60*4882a593Smuzhiyun u8 up; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* _IXGBE_FCOE_H */ 64