1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _DCB_CONFIG_H_ 5*4882a593Smuzhiyun #define _DCB_CONFIG_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/dcbnl.h> 8*4882a593Smuzhiyun #include "ixgbe_type.h" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* DCB data structures */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define IXGBE_MAX_PACKET_BUFFERS 8 13*4882a593Smuzhiyun #define MAX_USER_PRIORITY 8 14*4882a593Smuzhiyun #define MAX_BW_GROUP 8 15*4882a593Smuzhiyun #define BW_PERCENT 100 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define DCB_TX_CONFIG 0 18*4882a593Smuzhiyun #define DCB_RX_CONFIG 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* DCB error Codes */ 21*4882a593Smuzhiyun #define DCB_SUCCESS 0 22*4882a593Smuzhiyun #define DCB_ERR_CONFIG -1 23*4882a593Smuzhiyun #define DCB_ERR_PARAM -2 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Transmit and receive Errors */ 26*4882a593Smuzhiyun /* Error in bandwidth group allocation */ 27*4882a593Smuzhiyun #define DCB_ERR_BW_GROUP -3 28*4882a593Smuzhiyun /* Error in traffic class bandwidth allocation */ 29*4882a593Smuzhiyun #define DCB_ERR_TC_BW -4 30*4882a593Smuzhiyun /* Traffic class has both link strict and group strict enabled */ 31*4882a593Smuzhiyun #define DCB_ERR_LS_GS -5 32*4882a593Smuzhiyun /* Link strict traffic class has non zero bandwidth */ 33*4882a593Smuzhiyun #define DCB_ERR_LS_BW_NONZERO -6 34*4882a593Smuzhiyun /* Link strict bandwidth group has non zero bandwidth */ 35*4882a593Smuzhiyun #define DCB_ERR_LS_BWG_NONZERO -7 36*4882a593Smuzhiyun /* Traffic class has zero bandwidth */ 37*4882a593Smuzhiyun #define DCB_ERR_TC_BW_ZERO -8 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define DCB_NOT_IMPLEMENTED 0x7FFFFFFF 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct dcb_pfc_tc_debug { 42*4882a593Smuzhiyun u8 tc; 43*4882a593Smuzhiyun u8 pause_status; 44*4882a593Smuzhiyun u64 pause_quanta; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun enum strict_prio_type { 48*4882a593Smuzhiyun prio_none = 0, 49*4882a593Smuzhiyun prio_group, 50*4882a593Smuzhiyun prio_link 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* DCB capability definitions */ 54*4882a593Smuzhiyun #define IXGBE_DCB_PG_SUPPORT 0x00000001 55*4882a593Smuzhiyun #define IXGBE_DCB_PFC_SUPPORT 0x00000002 56*4882a593Smuzhiyun #define IXGBE_DCB_BCN_SUPPORT 0x00000004 57*4882a593Smuzhiyun #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 58*4882a593Smuzhiyun #define IXGBE_DCB_GSP_SUPPORT 0x00000010 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define IXGBE_DCB_8_TC_SUPPORT 0x80 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct dcb_support { 63*4882a593Smuzhiyun /* DCB capabilities */ 64*4882a593Smuzhiyun u32 capabilities; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Each bit represents a number of TCs configurable in the hw. 67*4882a593Smuzhiyun * If 8 traffic classes can be configured, the value is 0x80. 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun u8 traffic_classes; 70*4882a593Smuzhiyun u8 pfc_traffic_classes; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Traffic class bandwidth allocation per direction */ 74*4882a593Smuzhiyun struct tc_bw_alloc { 75*4882a593Smuzhiyun u8 bwg_id; /* Bandwidth Group (BWG) ID */ 76*4882a593Smuzhiyun u8 bwg_percent; /* % of BWG's bandwidth */ 77*4882a593Smuzhiyun u8 link_percent; /* % of link bandwidth */ 78*4882a593Smuzhiyun u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ 79*4882a593Smuzhiyun u16 data_credits_refill; /* Credit refill amount in 64B granularity */ 80*4882a593Smuzhiyun u16 data_credits_max; /* Max credits for a configured packet buffer 81*4882a593Smuzhiyun * in 64B granularity.*/ 82*4882a593Smuzhiyun enum strict_prio_type prio_type; /* Link or Group Strict Priority */ 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun enum dcb_pfc_type { 86*4882a593Smuzhiyun pfc_disabled = 0, 87*4882a593Smuzhiyun pfc_enabled_full, 88*4882a593Smuzhiyun pfc_enabled_tx, 89*4882a593Smuzhiyun pfc_enabled_rx 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Traffic class configuration */ 93*4882a593Smuzhiyun struct tc_configuration { 94*4882a593Smuzhiyun struct tc_bw_alloc path[2]; /* One each for Tx/Rx */ 95*4882a593Smuzhiyun enum dcb_pfc_type dcb_pfc; /* Class based flow control setting */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun u16 desc_credits_max; /* For Tx Descriptor arbitration */ 98*4882a593Smuzhiyun u8 tc; /* Traffic class (TC) */ 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct dcb_num_tcs { 102*4882a593Smuzhiyun u8 pg_tcs; 103*4882a593Smuzhiyun u8 pfc_tcs; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun struct ixgbe_dcb_config { 107*4882a593Smuzhiyun struct dcb_support support; 108*4882a593Smuzhiyun struct dcb_num_tcs num_tcs; 109*4882a593Smuzhiyun struct tc_configuration tc_config[MAX_TRAFFIC_CLASS]; 110*4882a593Smuzhiyun u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */ 111*4882a593Smuzhiyun bool pfc_mode_enable; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun u32 dcb_cfg_version; /* Not used...OS-specific? */ 114*4882a593Smuzhiyun u32 link_speed; /* For bandwidth allocation validation purpose */ 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* DCB driver APIs */ 118*4882a593Smuzhiyun void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en); 119*4882a593Smuzhiyun void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *, int, u16 *); 120*4882a593Smuzhiyun void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *, u16 *); 121*4882a593Smuzhiyun void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *, int, u8 *); 122*4882a593Smuzhiyun void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *, int, u8 *); 123*4882a593Smuzhiyun void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *, int, u8 *); 124*4882a593Smuzhiyun u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8); 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* DCB credits calculation */ 127*4882a593Smuzhiyun s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *, 128*4882a593Smuzhiyun struct ixgbe_dcb_config *, int, u8); 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* DCB hw initialization */ 131*4882a593Smuzhiyun s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max); 132*4882a593Smuzhiyun s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, 133*4882a593Smuzhiyun u8 *bwg_id, u8 *prio_type, u8 *tc_prio); 134*4882a593Smuzhiyun s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *tc_prio); 135*4882a593Smuzhiyun s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *); 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map); 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* DCB definitions for credit calculation */ 140*4882a593Smuzhiyun #define DCB_CREDIT_QUANTUM 64 /* DCB Quantum */ 141*4882a593Smuzhiyun #define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */ 142*4882a593Smuzhiyun #define DCB_MAX_TSO_SIZE (32*1024) /* MAX TSO packet size supported in DCB mode */ 143*4882a593Smuzhiyun #define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */ 144*4882a593Smuzhiyun #define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */ 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* _DCB_CONFIG_H */ 147