1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2008 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* glue for the OS independent part of ixgb 5*4882a593Smuzhiyun * includes register access macros 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _IXGB_OSDEP_H_ 9*4882a593Smuzhiyun #define _IXGB_OSDEP_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/types.h> 12*4882a593Smuzhiyun #include <linux/delay.h> 13*4882a593Smuzhiyun #include <asm/io.h> 14*4882a593Smuzhiyun #include <linux/interrupt.h> 15*4882a593Smuzhiyun #include <linux/sched.h> 16*4882a593Smuzhiyun #include <linux/if_ether.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #undef ASSERT 19*4882a593Smuzhiyun #define ASSERT(x) BUG_ON(!(x)) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define ENTER() pr_debug("%s\n", __func__); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define IXGB_WRITE_REG(a, reg, value) ( \ 24*4882a593Smuzhiyun writel((value), ((a)->hw_addr + IXGB_##reg))) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define IXGB_READ_REG(a, reg) ( \ 27*4882a593Smuzhiyun readl((a)->hw_addr + IXGB_##reg)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \ 30*4882a593Smuzhiyun writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2)))) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \ 33*4882a593Smuzhiyun readl((a)->hw_addr + IXGB_##reg + ((offset) << 2))) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define IXGB_MEMCPY memcpy 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* _IXGB_OSDEP_H_ */ 40