1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2008 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _IXGB_EE_H_ 5*4882a593Smuzhiyun #define _IXGB_EE_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define IXGB_EEPROM_SIZE 64 /* Size in words */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* EEPROM Commands */ 10*4882a593Smuzhiyun #define EEPROM_READ_OPCODE 0x6 /* EEPROM read opcode */ 11*4882a593Smuzhiyun #define EEPROM_WRITE_OPCODE 0x5 /* EEPROM write opcode */ 12*4882a593Smuzhiyun #define EEPROM_ERASE_OPCODE 0x7 /* EEPROM erase opcode */ 13*4882a593Smuzhiyun #define EEPROM_EWEN_OPCODE 0x13 /* EEPROM erase/write enable */ 14*4882a593Smuzhiyun #define EEPROM_EWDS_OPCODE 0x10 /* EEPROM erase/write disable */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* EEPROM MAP (Word Offsets) */ 17*4882a593Smuzhiyun #define EEPROM_IA_1_2_REG 0x0000 18*4882a593Smuzhiyun #define EEPROM_IA_3_4_REG 0x0001 19*4882a593Smuzhiyun #define EEPROM_IA_5_6_REG 0x0002 20*4882a593Smuzhiyun #define EEPROM_COMPATIBILITY_REG 0x0003 21*4882a593Smuzhiyun #define EEPROM_PBA_1_2_REG 0x0008 22*4882a593Smuzhiyun #define EEPROM_PBA_3_4_REG 0x0009 23*4882a593Smuzhiyun #define EEPROM_INIT_CONTROL1_REG 0x000A 24*4882a593Smuzhiyun #define EEPROM_SUBSYS_ID_REG 0x000B 25*4882a593Smuzhiyun #define EEPROM_SUBVEND_ID_REG 0x000C 26*4882a593Smuzhiyun #define EEPROM_DEVICE_ID_REG 0x000D 27*4882a593Smuzhiyun #define EEPROM_VENDOR_ID_REG 0x000E 28*4882a593Smuzhiyun #define EEPROM_INIT_CONTROL2_REG 0x000F 29*4882a593Smuzhiyun #define EEPROM_SWDPINS_REG 0x0020 30*4882a593Smuzhiyun #define EEPROM_CIRCUIT_CTRL_REG 0x0021 31*4882a593Smuzhiyun #define EEPROM_D0_D3_POWER_REG 0x0022 32*4882a593Smuzhiyun #define EEPROM_FLASH_VERSION 0x0032 33*4882a593Smuzhiyun #define EEPROM_CHECKSUM_REG 0x003F 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Mask bits for fields in Word 0x0a of the EEPROM */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define EEPROM_ICW1_SIGNATURE_MASK 0xC000 38*4882a593Smuzhiyun #define EEPROM_ICW1_SIGNATURE_VALID 0x4000 39*4882a593Smuzhiyun #define EEPROM_ICW1_SIGNATURE_CLEAR 0x0000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 42*4882a593Smuzhiyun #define EEPROM_SUM 0xBABA 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* EEPROM Map Sizes (Byte Counts) */ 45*4882a593Smuzhiyun #define PBA_SIZE 4 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* EEPROM Map defines (WORD OFFSETS)*/ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* EEPROM structure */ 50*4882a593Smuzhiyun struct ixgb_ee_map_type { 51*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; 52*4882a593Smuzhiyun __le16 compatibility; 53*4882a593Smuzhiyun __le16 reserved1[4]; 54*4882a593Smuzhiyun __le32 pba_number; 55*4882a593Smuzhiyun __le16 init_ctrl_reg_1; 56*4882a593Smuzhiyun __le16 subsystem_id; 57*4882a593Smuzhiyun __le16 subvendor_id; 58*4882a593Smuzhiyun __le16 device_id; 59*4882a593Smuzhiyun __le16 vendor_id; 60*4882a593Smuzhiyun __le16 init_ctrl_reg_2; 61*4882a593Smuzhiyun __le16 oem_reserved[16]; 62*4882a593Smuzhiyun __le16 swdpins_reg; 63*4882a593Smuzhiyun __le16 circuit_ctrl_reg; 64*4882a593Smuzhiyun u8 d3_power; 65*4882a593Smuzhiyun u8 d0_power; 66*4882a593Smuzhiyun __le16 reserved2[28]; 67*4882a593Smuzhiyun __le16 checksum; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* EEPROM Functions */ 71*4882a593Smuzhiyun u16 ixgb_read_eeprom(struct ixgb_hw *hw, u16 reg); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun bool ixgb_validate_eeprom_checksum(struct ixgb_hw *hw); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun void ixgb_update_eeprom_checksum(struct ixgb_hw *hw); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun void ixgb_write_eeprom(struct ixgb_hw *hw, u16 reg, u16 data); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* IXGB_EE_H */ 80