1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2018 Intel Corporation */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _IGC_MAC_H_ 5*4882a593Smuzhiyun #define _IGC_MAC_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "igc_hw.h" 8*4882a593Smuzhiyun #include "igc_phy.h" 9*4882a593Smuzhiyun #include "igc_defines.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* forward declaration */ 12*4882a593Smuzhiyun s32 igc_disable_pcie_master(struct igc_hw *hw); 13*4882a593Smuzhiyun s32 igc_check_for_copper_link(struct igc_hw *hw); 14*4882a593Smuzhiyun s32 igc_config_fc_after_link_up(struct igc_hw *hw); 15*4882a593Smuzhiyun s32 igc_force_mac_fc(struct igc_hw *hw); 16*4882a593Smuzhiyun void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count); 17*4882a593Smuzhiyun s32 igc_setup_link(struct igc_hw *hw); 18*4882a593Smuzhiyun void igc_clear_hw_cntrs_base(struct igc_hw *hw); 19*4882a593Smuzhiyun s32 igc_get_auto_rd_done(struct igc_hw *hw); 20*4882a593Smuzhiyun void igc_put_hw_semaphore(struct igc_hw *hw); 21*4882a593Smuzhiyun void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index); 22*4882a593Smuzhiyun void igc_config_collision_dist(struct igc_hw *hw); 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed, 25*4882a593Smuzhiyun u16 *duplex); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun bool igc_enable_mng_pass_thru(struct igc_hw *hw); 28*4882a593Smuzhiyun void igc_update_mc_addr_list(struct igc_hw *hw, 29*4882a593Smuzhiyun u8 *mc_addr_list, u32 mc_addr_count); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum igc_mng_mode { 32*4882a593Smuzhiyun igc_mng_mode_none = 0, 33*4882a593Smuzhiyun igc_mng_mode_asf, 34*4882a593Smuzhiyun igc_mng_mode_pt, 35*4882a593Smuzhiyun igc_mng_mode_ipmi, 36*4882a593Smuzhiyun igc_mng_mode_host_if_only 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif 40