1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2020 Intel Corporation */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun bool igc_reg_test(struct igc_adapter *adapter, u64 *data); 5*4882a593Smuzhiyun bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data); 6*4882a593Smuzhiyun bool igc_link_test(struct igc_adapter *adapter, u64 *data); 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun struct igc_reg_test { 9*4882a593Smuzhiyun u16 reg; 10*4882a593Smuzhiyun u8 array_len; 11*4882a593Smuzhiyun u8 test_type; 12*4882a593Smuzhiyun u32 mask; 13*4882a593Smuzhiyun u32 write; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* In the hardware, registers are laid out either singly, in arrays 17*4882a593Smuzhiyun * spaced 0x40 bytes apart, or in contiguous tables. We assume 18*4882a593Smuzhiyun * most tests take place on arrays or single registers (handled 19*4882a593Smuzhiyun * as a single-element array) and special-case the tables. 20*4882a593Smuzhiyun * Table tests are always pattern tests. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * We also make provision for some required setup steps by specifying 23*4882a593Smuzhiyun * registers to be written without any read-back testing. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define PATTERN_TEST 1 27*4882a593Smuzhiyun #define SET_READ_TEST 2 28*4882a593Smuzhiyun #define TABLE32_TEST 3 29*4882a593Smuzhiyun #define TABLE64_TEST_LO 4 30*4882a593Smuzhiyun #define TABLE64_TEST_HI 5 31